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fpp.cpp
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fpp.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68881/68882/68040/68060 FPU emulation
*
* Copyright 1996 Herman ten Brugge
* Modified 2005 Peter Keunecke
* 68040+ exceptions and more by Toni Wilen
*/
#define __USE_ISOC9X /* We might be able to pick up a NaN */
#define FPU_TEST 0
#define FPU_LOG 0
#include <math.h>
#include <float.h>
#include <fenv.h>
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "uae/attributes.h"
#include "uae/vm.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "fpp.h"
#include "savestate.h"
#include "cpu_prefetch.h"
#include "cpummu.h"
#include "cpummu030.h"
#include "debug.h"
#ifndef CPU_TESTER
#define SUPPORT_MMU 1
#else
#define SUPPORT_MMU 0
#endif
#include "softfloat/softfloat.h"
// global variable for JIT FPU
#ifdef USE_LONG_DOUBLE
bool use_long_double = true;
#else
bool use_long_double = false;
#endif
static bool support_exceptions;
static bool support_denormals;
FPP_PRINT fpp_print;
FPP_IS fpp_unset_snan;
FPP_IS fpp_is_init;
FPP_IS fpp_is_snan;
FPP_IS fpp_is_nan;
FPP_IS fpp_is_infinity;
FPP_IS fpp_is_zero;
FPP_IS fpp_is_neg;
FPP_IS fpp_is_denormal;
FPP_IS fpp_is_unnormal;
FPP_A fpp_fix_infinity;
FPP_GET_STATUS fpp_get_status;
FPP_CLEAR_STATUS fpp_clear_status;
FPP_SET_MODE fpp_set_mode;
FPP_SUPPORT_FLAGS fpp_get_support_flags;
FPP_FROM_NATIVE fpp_from_native;
FPP_TO_NATIVE fpp_to_native;
FPP_TO_INT fpp_to_int;
FPP_FROM_INT fpp_from_int;
FPP_PACK fpp_to_pack;
FPP_PACK fpp_from_pack;
FPP_TO_SINGLE fpp_to_single;
FPP_FROM_SINGLE fpp_from_single;
FPP_TO_DOUBLE fpp_to_double;
FPP_FROM_DOUBLE fpp_from_double;
FPP_TO_EXTEN fpp_to_exten;
FPP_FROM_EXTEN fpp_from_exten;
FPP_TO_EXTEN fpp_to_exten_fmovem;
FPP_FROM_EXTEN fpp_from_exten_fmovem;
FPP_A fpp_normalize;
FPP_DENORMALIZE fpp_denormalize;
FPP_A fpp_get_internal_overflow;
FPP_A fpp_get_internal_underflow;
FPP_A fpp_get_internal_round_all;
FPP_A fpp_get_internal_round;
FPP_A fpp_get_internal_round_exten;
FPP_A fpp_get_internal;
FPP_GET32 fpp_get_internal_grs;
FPP_A fpp_round_single;
FPP_A fpp_round_double;
FPP_A fpp_round32;
FPP_A fpp_round64;
FPP_AB fpp_int;
FPP_AB fpp_sinh;
FPP_AB fpp_intrz;
FPP_ABP fpp_sqrt;
FPP_AB fpp_lognp1;
FPP_AB fpp_etoxm1;
FPP_AB fpp_tanh;
FPP_AB fpp_atan;
FPP_AB fpp_atanh;
FPP_AB fpp_sin;
FPP_AB fpp_asin;
FPP_AB fpp_tan;
FPP_AB fpp_etox;
FPP_AB fpp_twotox;
FPP_AB fpp_tentox;
FPP_AB fpp_logn;
FPP_AB fpp_log10;
FPP_AB fpp_log2;
FPP_ABP fpp_abs;
FPP_AB fpp_cosh;
FPP_ABP fpp_neg;
FPP_AB fpp_acos;
FPP_AB fpp_cos;
FPP_AB fpp_getexp;
FPP_AB fpp_getman;
FPP_ABP fpp_div;
FPP_ABQS fpp_mod;
FPP_ABP fpp_add;
FPP_ABP fpp_mul;
FPP_ABQS fpp_rem;
FPP_AB fpp_scale;
FPP_ABP fpp_sub;
FPP_AB fpp_sgldiv;
FPP_AB fpp_sglmul;
FPP_AB fpp_cmp;
FPP_AB fpp_tst;
FPP_ABP fpp_move;
#define DEBUG_FPP 0
#define EXCEPTION_FPP 0
STATIC_INLINE int isinrom (void)
{
return (munge24 (m68k_getpc ()) & 0xFFF80000) == 0xF80000 && !currprefs.mmu_model;
}
static bool jit_fpu(void)
{
return currprefs.cachesize && currprefs.compfpu;
}
static int warned = 100;
struct fpp_cr_entry {
uae_u32 val[3];
uae_u8 inexact;
uae_s8 rndoff[4];
};
static const struct fpp_cr_entry fpp_cr[22] = {
{ {0x40000000, 0xc90fdaa2, 0x2168c235}, 1, {0,-1,-1, 0} }, // 0 = pi
{ {0x3ffd0000, 0x9a209a84, 0xfbcff798}, 1, {0, 0, 0, 1} }, // 1 = log10(2)
{ {0x40000000, 0xadf85458, 0xa2bb4a9a}, 1, {0, 0, 0, 1} }, // 2 = e
{ {0x3fff0000, 0xb8aa3b29, 0x5c17f0bc}, 1, {0,-1,-1, 0} }, // 3 = log2(e)
{ {0x3ffd0000, 0xde5bd8a9, 0x37287195}, 0, {0, 0, 0, 0} }, // 4 = log10(e)
{ {0x00000000, 0x00000000, 0x00000000}, 0, {0, 0, 0, 0} }, // 5 = 0.0
{ {0x3ffe0000, 0xb17217f7, 0xd1cf79ac}, 1, {0,-1,-1, 0} }, // 6 = ln(2)
{ {0x40000000, 0x935d8ddd, 0xaaa8ac17}, 1, {0,-1,-1, 0} }, // 7 = ln(10)
{ {0x3fff0000, 0x80000000, 0x00000000}, 0, {0, 0, 0, 0} }, // 8 = 1e0
{ {0x40020000, 0xa0000000, 0x00000000}, 0, {0, 0, 0, 0} }, // 9 = 1e1
{ {0x40050000, 0xc8000000, 0x00000000}, 0, {0, 0, 0, 0} }, // 10 = 1e2
{ {0x400c0000, 0x9c400000, 0x00000000}, 0, {0, 0, 0, 0} }, // 11 = 1e4
{ {0x40190000, 0xbebc2000, 0x00000000}, 0, {0, 0, 0, 0} }, // 12 = 1e8
{ {0x40340000, 0x8e1bc9bf, 0x04000000}, 0, {0, 0, 0, 0} }, // 13 = 1e16
{ {0x40690000, 0x9dc5ada8, 0x2b70b59e}, 1, {0,-1,-1, 0} }, // 14 = 1e32
{ {0x40d30000, 0xc2781f49, 0xffcfa6d5}, 1, {0, 0, 0, 1} }, // 15 = 1e64
{ {0x41a80000, 0x93ba47c9, 0x80e98ce0}, 1, {0,-1,-1, 0} }, // 16 = 1e128
{ {0x43510000, 0xaa7eebfb, 0x9df9de8e}, 1, {0,-1,-1, 0} }, // 17 = 1e256
{ {0x46a30000, 0xe319a0ae, 0xa60e91c7}, 1, {0,-1,-1, 0} }, // 18 = 1e512
{ {0x4d480000, 0xc9767586, 0x81750c17}, 1, {0, 0, 0, 1} }, // 19 = 1e1024
{ {0x5a920000, 0x9e8b3b5d, 0xc53d5de5}, 1, {0,-1,-1, 0} }, // 20 = 1e2048
{ {0x75250000, 0xc4605202, 0x8a20979b}, 1, {0,-1,-1, 0} } // 21 = 1e4094
};
#define FPP_CR_PI 0
#define FPP_CR_LOG10_2 1
#define FPP_CR_E 2
#define FPP_CR_LOG2_E 3
#define FPP_CR_LOG10_E 4
#define FPP_CR_ZERO 5
#define FPP_CR_LN_2 6
#define FPP_CR_LN_10 7
#define FPP_CR_1E0 8
#define FPP_CR_1E1 9
#define FPP_CR_1E2 10
#define FPP_CR_1E4 11
#define FPP_CR_1E8 12
#define FPP_CR_1E16 13
#define FPP_CR_1E32 14
#define FPP_CR_1E64 15
#define FPP_CR_1E128 16
#define FPP_CR_1E256 17
#define FPP_CR_1E512 18
#define FPP_CR_1E1024 19
#define FPP_CR_1E2048 20
#define FPP_CR_1E4096 21
struct fpp_cr_entry_undef {
uae_u32 val[3];
};
#define FPP_CR_NUM_SPECIAL_UNDEFINED 10
// 68881 and 68882 have identical undefined fields
static const struct fpp_cr_entry_undef fpp_cr_undef[] = {
{ {0x40000000, 0x00000000, 0x00000000} },
{ {0x40010000, 0xfe000682, 0x00000000} },
{ {0x40010000, 0xffc00503, 0x80000000} },
{ {0x20000000, 0x7fffffff, 0x00000000} },
{ {0x00000000, 0xffffffff, 0xffffffff} },
{ {0x3c000000, 0xffffffff, 0xfffff800} },
{ {0x3f800000, 0xffffff00, 0x00000000} },
{ {0x00010000, 0xf65d8d9c, 0x00000000} },
{ {0x7fff0000, 0x001e0000, 0x00000000} },
{ {0x43ff0000, 0x000e0000, 0x00000000} },
{ {0x407f0000, 0x00060000, 0x00000000} }
};
uae_u32 xhex_nan[] ={0x7fff0000, 0xffffffff, 0xffffffff};
static bool fpu_mmu_fixup;
/* Floating Point Control Register (FPCR)
*
* Exception Enable Byte
* x--- ---- ---- ---- bit 15: BSUN (branch/set on unordered)
* -x-- ---- ---- ---- bit 14: SNAN (signaling not a number)
* --x- ---- ---- ---- bit 13: OPERR (operand error)
* ---x ---- ---- ---- bit 12: OVFL (overflow)
* ---- x--- ---- ---- bit 11: UNFL (underflow)
* ---- -x-- ---- ---- bit 10: DZ (divide by zero)
* ---- --x- ---- ---- bit 9: INEX 2 (inexact operation)
* ---- ---x ---- ---- bit 8: INEX 1 (inexact decimal input)
*
* Mode Control Byte
* ---- ---- xx-- ---- bits 7 and 6: PREC (rounding precision)
* ---- ---- --xx ---- bits 5 and 4: RND (rounding mode)
* ---- ---- ---- xxxx bits 3 to 0: all 0
*/
#define FPCR_PREC 0x00C0
#define FPCR_RND 0x0030
/* Floating Point Status Register (FPSR)
*
* Condition Code Byte
* xxxx ---- ---- ---- ---- ---- ---- ---- bits 31 to 28: all 0
* ---- x--- ---- ---- ---- ---- ---- ---- bit 27: N (negative)
* ---- -x-- ---- ---- ---- ---- ---- ---- bit 26: Z (zero)
* ---- --x- ---- ---- ---- ---- ---- ---- bit 25: I (infinity)
* ---- ---x ---- ---- ---- ---- ---- ---- bit 24: NAN (not a number or unordered)
*
* Quotient Byte (set and reset only by FMOD and FREM)
* ---- ---- x--- ---- ---- ---- ---- ---- bit 23: sign of quotient
* ---- ---- -xxx xxxx ---- ---- ---- ---- bits 22 to 16: 7 least significant bits of quotient
*
* Exception Status Byte
* ---- ---- ---- ---- x--- ---- ---- ---- bit 15: BSUN (branch/set on unordered)
* ---- ---- ---- ---- -x-- ---- ---- ---- bit 14: SNAN (signaling not a number)
* ---- ---- ---- ---- --x- ---- ---- ---- bit 13: OPERR (operand error)
* ---- ---- ---- ---- ---x ---- ---- ---- bit 12: OVFL (overflow)
* ---- ---- ---- ---- ---- x--- ---- ---- bit 11: UNFL (underflow)
* ---- ---- ---- ---- ---- -x-- ---- ---- bit 10: DZ (divide by zero)
* ---- ---- ---- ---- ---- --x- ---- ---- bit 9: INEX 2 (inexact operation)
* ---- ---- ---- ---- ---- ---x ---- ---- bit 8: INEX 1 (inexact decimal input)
*
* Accrued Exception Byte
* ---- ---- ---- ---- ---- ---- x--- ---- bit 7: IOP (invalid operation)
* ---- ---- ---- ---- ---- ---- -x-- ---- bit 6: OVFL (overflow)
* ---- ---- ---- ---- ---- ---- --x- ---- bit 5: UNFL (underflow)
* ---- ---- ---- ---- ---- ---- ---x ---- bit 4: DZ (divide by zero)
* ---- ---- ---- ---- ---- ---- ---- x--- bit 3: INEX (inexact)
* ---- ---- ---- ---- ---- ---- ---- -xxx bits 2 to 0: all 0
*/
#define FPSR_ZEROBITS 0xF0000007
#define FPSR_CC_N 0x08000000
#define FPSR_CC_Z 0x04000000
#define FPSR_CC_I 0x02000000
#define FPSR_CC_NAN 0x01000000
#define FPSR_QUOT_SIGN 0x00800000
#define FPSR_QUOT_LSB 0x007F0000
#define FPSR_AE_IOP 0x00000080
#define FPSR_AE_OVFL 0x00000040
#define FPSR_AE_UNFL 0x00000020
#define FPSR_AE_DZ 0x00000010
#define FPSR_AE_INEX 0x00000008
static struct {
// 6888x and 68060
uae_u32 ccr;
uae_u32 eo[3];
// 68060
uae_u32 v;
// 68040
uae_u32 fpiarcu;
uae_u32 cmdreg3b;
uae_u32 cmdreg1b;
uae_u32 stag, dtag;
uae_u32 e1, e3, t;
uae_u32 fpt[3];
uae_u32 et[3];
uae_u32 wbt[3];
uae_u32 grs;
uae_u32 wbte15;
uae_u32 wbtm66;
} fsave_data;
static void reset_fsave_data(void)
{
int i;
for (i = 0; i < 3; i++) {
fsave_data.eo[i] = 0;
fsave_data.fpt[i] = 0;
fsave_data.et[i] = 0;
fsave_data.wbt[i] = 0;
}
fsave_data.ccr = 0;
fsave_data.v = 0;
fsave_data.fpiarcu = 0;
fsave_data.cmdreg1b = 0;
fsave_data.cmdreg3b = 0;
fsave_data.stag = 0;
fsave_data.dtag = 0;
fsave_data.e1 = 0;
fsave_data.e3 = 0;
fsave_data.t = 0;
fsave_data.wbte15 = 0;
fsave_data.wbtm66 = 0;
fsave_data.grs = 0;
}
static uae_u32 get_ftag(fpdata *src, int size)
{
fpp_is_init(src);
if (fpp_is_zero(src)) {
return 1; // ZERO
} else if (fpp_is_unnormal(src) || fpp_is_denormal(src)) {
if (size == 1 || size == 5)
return 5; // Single/double DENORMAL
return 4; // Extended DENORMAL or UNNORMAL
} else if (fpp_is_nan(src)) {
return 3; // NAN
} else if (fpp_is_infinity(src)) {
return 2; // INF
}
return 0; // NORMAL
}
STATIC_INLINE bool fp_is_dyadic(uae_u16 extra)
{
return ((extra & 0x30) == 0x20 || (extra & 0x7f) == 0x38);
}
static bool fp_exception_pending(bool pre)
{
// first check for pending arithmetic exceptions
if (support_exceptions && !jit_fpu()) {
if (regs.fp_exp_pend) {
if (warned > 0) {
write_log (_T("FPU ARITHMETIC EXCEPTION (%d)\n"), regs.fp_exp_pend);
}
regs.fpu_exp_pre = pre;
Exception(regs.fp_exp_pend);
if (currprefs.fpu_model != 68882)
regs.fp_exp_pend = 0;
return true;
}
}
// no arithmetic exceptions pending, check for unimplemented datatype
if (regs.fp_unimp_pend) {
if (warned > 0) {
write_log (_T("FPU unimplemented datatype exception (%s)\n"), pre ? _T("pre") : _T("mid/post"));
}
regs.fpu_exp_pre = pre;
Exception(55);
regs.fp_unimp_pend = 0;
return true;
}
return false;
}
static void fp_unimp_instruction_exception_pending(void)
{
if (regs.fp_unimp_ins) {
if (warned > 0) {
write_log (_T("FPU UNIMPLEMENTED INSTRUCTION/FPU DISABLED EXCEPTION PC=%08x\n"), M68K_GETPC);
}
regs.fpu_exp_pre = true;
Exception(11);
regs.fp_unimp_ins = false;
regs.fp_unimp_pend = 0;
}
}
void fpsr_set_exception(uae_u32 exception)
{
regs.fpsr |= exception;
}
static uae_u32 fpsr_get_vector(uae_u32 exception)
{
static const int vtable[8] = { 49, 49, 50, 51, 53, 52, 54, 48 };
int i;
exception >>= 8;
for (i = 7; i >= 0; i--) {
if (exception & (1 << i)) {
return vtable[i];
}
}
return 0;
}
static void fpsr_check_arithmetic_exception(uae_u32 mask, fpdata *src, uae_u32 opcode, uae_u16 extra, uae_u32 ea)
{
if (!support_exceptions || jit_fpu())
return;
bool nonmaskable;
uae_u32 exception;
// Any exception status bit and matching exception enable bits set?
exception = regs.fpsr & regs.fpcr & 0xff00;
// Add 68040/68060 nonmaskable exceptions. Only if no unimplemented instruction emulation.
if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented) {
exception |= regs.fpsr & (FPSR_OVFL | FPSR_UNFL | mask);
}
if (exception) {
regs.fp_exp_pend = fpsr_get_vector(exception);
nonmaskable = (regs.fp_exp_pend != fpsr_get_vector(regs.fpsr & regs.fpcr));
if (warned > 0) {
write_log(_T("FPU %s arithmetic exception pending: FPSR: %08x, FPCR: %04x (vector: %d)!\n"),
nonmaskable ? _T("nonmaskable") : _T(""), regs.fpsr, regs.fpcr, regs.fp_exp_pend);
#if EXCEPTION_FPP == 0
warned--;
#endif
}
if (!support_exceptions || jit_fpu()) {
// log message and exit
regs.fp_exp_pend = 0;
return;
}
regs.fp_opword = opcode;
regs.fp_ea = ea;
// data for FSAVE stack frame
fpdata eo;
uae_u32 opclass = (extra >> 13) & 7;
reset_fsave_data();
if (currprefs.fpu_model == 68881 || currprefs.fpu_model == 68882) {
// fsave data for 68881 and 68882
if (opclass == 3) { // 011
fsave_data.ccr = ((uae_u32)extra << 16) | extra;
} else { // 000 or 010
fsave_data.ccr = ((uae_u32)(opcode | 0x0080) << 16) | extra;
}
if (regs.fp_exp_pend == 54 || regs.fp_exp_pend == 52 || regs.fp_exp_pend == 50) { // SNAN, OPERR, DZ
fpp_from_exten_fmovem(src, &fsave_data.eo[0], &fsave_data.eo[1], &fsave_data.eo[2]);
if (regs.fp_exp_pend == 52 && opclass == 3) { // OPERR from move to integer or packed
fsave_data.eo[0] &= 0x4fff0000;
fsave_data.eo[1] = fsave_data.eo[2] = 0;
}
} else if (regs.fp_exp_pend == 53) { // OVFL
fpp_get_internal_overflow(&eo);
fpp_from_exten_fmovem(&eo, &fsave_data.eo[0], &fsave_data.eo[1], &fsave_data.eo[2]);
} else if (regs.fp_exp_pend == 51) { // UNFL
fpp_get_internal_underflow(&eo);
fpp_from_exten_fmovem(&eo, &fsave_data.eo[0], &fsave_data.eo[1], &fsave_data.eo[2]);
} // else INEX1, INEX2: do nothing
} else if (currprefs.cpu_model == 68060) {
// fsave data for 68060
regs.fpu_exp_state = 2; // 68060 EXCP frame
fsave_data.v = regs.fp_exp_pend & 7;
fpp_from_exten_fmovem(src, &fsave_data.eo[0], &fsave_data.eo[1], &fsave_data.eo[2]);
} else {
// fsave data for 68040
regs.fpu_exp_state = 1; // 68040 UNIMP frame
uae_u32 reg = (extra >> 7) & 7;
int size = (extra >> 10) & 7;
fsave_data.fpiarcu = regs.fpiar;
if (regs.fp_exp_pend == 54) { // SNAN (undocumented)
fsave_data.wbte15 = 1;
fsave_data.grs = 7;
} else {
fsave_data.grs = 1;
}
if (opclass == 3) { // OPCLASS 011
fsave_data.cmdreg1b = extra;
fsave_data.e1 = 1;
fsave_data.t = 1;
fsave_data.wbte15 = (regs.fp_exp_pend == 51 || regs.fp_exp_pend == 54) ? 1 : 0; // UNFL, SNAN
fpp_is_init(src);
if (fpp_is_snan(src)) {
fpp_unset_snan(src);
}
fpp_from_exten_fmovem(src, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]);
fsave_data.stag = get_ftag(src, -1);
} else { // OPCLASS 000 and 010
fsave_data.cmdreg1b = extra;
fsave_data.e1 = 1;
fsave_data.wbte15 = (regs.fp_exp_pend == 54) ? 1 : 0; // SNAN (undocumented)
if (regs.fp_exp_pend == 51 || regs.fp_exp_pend == 53 || regs.fp_exp_pend == 49) { // UNFL, OVFL, INEX
if ((extra & 0x30) == 0x20 || (extra & 0x3f) == 0x04) { // FADD, FSUB, FMUL, FDIV, FSQRT
regs.fpu_exp_state = 2; // 68040 BUSY frame
fsave_data.e3 = 1;
fsave_data.e1 = 0;
fsave_data.cmdreg3b = (extra & 0x3C3) | ((extra & 0x038)>>1) | ((extra & 0x004)<<3);
if (regs.fp_exp_pend == 51) { // UNFL
fpp_get_internal(&eo);
} else { // OVFL, INEX
fpp_get_internal_round(&eo);
}
fsave_data.grs = fpp_get_internal_grs();
fpp_from_exten_fmovem(&eo, &fsave_data.wbt[0], &fsave_data.wbt[1], &fsave_data.wbt[2]);
fsave_data.wbte15 = (regs.fp_exp_pend == 51) ? 1 : 0; // UNFL
// src and dst is stored (undocumented)
fpp_from_exten_fmovem(src, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]);
fsave_data.stag = get_ftag(src, (opclass == 0) ? -1 : size);
if (fp_is_dyadic(extra)) {
fpp_from_exten_fmovem(®s.fp[reg], &fsave_data.fpt[0], &fsave_data.fpt[1], &fsave_data.fpt[2]);
fsave_data.dtag = get_ftag(®s.fp[reg], -1);
}
} else { // FMOVE to register, FABS, FNEG
fpp_get_internal_round_exten(&eo);
fsave_data.grs = fpp_get_internal_grs();
fpp_from_exten_fmovem(&eo, &fsave_data.fpt[0], &fsave_data.fpt[1], &fsave_data.fpt[2]);
fpp_get_internal_round_all(&eo); // weird
fpp_from_exten_fmovem(&eo, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]); // undocumented
fsave_data.stag = get_ftag(src, (opclass == 0) ? -1 : size);
}
} else { // SNAN, OPERR, DZ
fpp_from_exten_fmovem(src, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]);
fsave_data.stag = get_ftag(src, (opclass == 0) ? -1 : size);
if (fp_is_dyadic(extra)) {
fpp_from_exten_fmovem(®s.fp[reg], &fsave_data.fpt[0], &fsave_data.fpt[1], &fsave_data.fpt[2]);
fsave_data.dtag = get_ftag(®s.fp[reg], -1);
}
}
}
}
}
}
static void fpsr_set_result(fpdata *result)
{
#ifdef JIT
regs.fp_result = *result;
#endif
// condition code byte
regs.fpsr &= 0x00fffff8; // clear cc
fpp_is_init(result);
if (fpp_is_nan(result)) {
regs.fpsr |= FPSR_CC_NAN;
} else if (fpp_is_zero(result)) {
regs.fpsr |= FPSR_CC_Z;
} else if (fpp_is_infinity(result)) {
regs.fpsr |= FPSR_CC_I;
}
if (fpp_is_neg(result))
regs.fpsr |= FPSR_CC_N;
}
static void fpsr_clear_status(void)
{
// clear exception status byte only
regs.fpsr &= 0x0fff00f8;
// clear external status
fpp_clear_status();
}
static uae_u32 fpsr_make_status(void)
{
uae_u32 exception;
// get external status
fpp_get_status(®s.fpsr);
// update accrued exception byte
if (regs.fpsr & (FPSR_BSUN | FPSR_SNAN | FPSR_OPERR))
regs.fpsr |= FPSR_AE_IOP; // IOP = BSUN || SNAN || OPERR
if (regs.fpsr & FPSR_OVFL)
regs.fpsr |= FPSR_AE_OVFL; // OVFL = OVFL
if ((regs.fpsr & FPSR_UNFL) && (regs.fpsr & FPSR_INEX2))
regs.fpsr |= FPSR_AE_UNFL; // UNFL = UNFL && INEX2
if (regs.fpsr & FPSR_DZ)
regs.fpsr |= FPSR_AE_DZ; // DZ = DZ
if (regs.fpsr & (FPSR_OVFL | FPSR_INEX2 | FPSR_INEX1))
regs.fpsr |= FPSR_AE_INEX; // INEX = INEX1 || INEX2 || OVFL
if (!support_exceptions || jit_fpu())
return 0;
// return exceptions that interrupt calculation
exception = regs.fpsr & regs.fpcr & (FPSR_SNAN | FPSR_OPERR | FPSR_DZ);
if (currprefs.cpu_model >= 68040 && currprefs.fpu_model && currprefs.fpu_no_unimplemented)
exception |= regs.fpsr & (FPSR_OVFL | FPSR_UNFL);
return exception;
}
static int fpsr_set_bsun(void)
{
regs.fpsr |= FPSR_BSUN;
regs.fpsr |= FPSR_AE_IOP;
if (regs.fpcr & FPSR_BSUN) {
// logging only so far
write_log (_T("FPU exception: BSUN! (FPSR: %08x, FPCR: %04x)\n"), regs.fpsr, regs.fpcr);
if (support_exceptions && !jit_fpu()) {
regs.fp_exp_pend = fpsr_get_vector(FPSR_BSUN);
fp_exception_pending(true);
return 1;
}
}
return 0;
}
static void fpsr_set_quotient(uae_u64 quot, uae_u8 sign)
{
regs.fpsr &= 0x0f00fff8;
regs.fpsr |= (quot << 16) & FPSR_QUOT_LSB;
regs.fpsr |= sign ? FPSR_QUOT_SIGN : 0;
}
static void fpsr_get_quotient(uae_u64 *quot, uae_u8 *sign)
{
*quot = (regs.fpsr & FPSR_QUOT_LSB) >> 16;
*sign = (regs.fpsr & FPSR_QUOT_SIGN) ? 1 : 0;
}
uae_u32 fpp_get_fpsr (void)
{
#ifdef JIT
if (currprefs.cachesize && currprefs.compfpu) {
regs.fpsr &= 0x00fffff8; // clear cc
fpp_is_init(®s.fp_result);
if (fpp_is_nan(®s.fp_result)) {
regs.fpsr |= FPSR_CC_NAN;
} else if (fpp_is_zero(®s.fp_result)) {
regs.fpsr |= FPSR_CC_Z;
} else if (fpp_is_infinity(®s.fp_result)) {
regs.fpsr |= FPSR_CC_I;
}
if (fpp_is_neg(®s.fp_result))
regs.fpsr |= FPSR_CC_N;
}
#endif
return regs.fpsr & 0x0ffffff8;
}
uae_u32 fpp_get_fpcr(void)
{
return regs.fpcr & (currprefs.fpu_model == 68040 ? 0xffff : 0xfff0);
}
void fpp_set_fpcr (uae_u32 val)
{
fpp_set_mode(val);
regs.fpcr = val & 0xffff;
}
static void fpnan (fpdata *fpd)
{
fpp_to_exten(fpd, xhex_nan[0], xhex_nan[1], xhex_nan[2]);
}
static void fpclear (fpdata *fpd)
{
fpp_from_int(fpd, 0);
}
static void fpset (fpdata *fpd, uae_s32 val)
{
fpp_from_int(fpd, val);
}
void fpp_set_fpsr (uae_u32 val)
{
regs.fpsr = val;
#ifdef JIT
// check comment in fpp_cond
if (currprefs.cachesize && currprefs.compfpu) {
if (val & 0x01000000)
fpnan(®s.fp_result);
else if (val & 0x04000000)
fpset(®s.fp_result, 0);
else if (val & 0x08000000)
fpset(®s.fp_result, -1);
else
fpset(®s.fp_result, 1);
}
#endif
}
void fpp_set_fpiar(uae_u32 val)
{
regs.fpiar = val;
}
uae_u32 fpp_get_fpiar(void)
{
return regs.fpiar;
}
bool fpu_get_constant(fpdata *fpd, int cr)
{
uae_u32 f[3] = { 0, 0, 0 };
int entry = 0;
bool round = true;
int mode = (regs.fpcr >> 4) & 3;
int prec = (regs.fpcr >> 6) & 3;
switch (cr)
{
case 0x00: // pi
entry = FPP_CR_PI;
break;
case 0x0b: // log10(2)
entry = FPP_CR_LOG10_2;
break;
case 0x0c: // e
entry = FPP_CR_E;
break;
case 0x0d: // log2(e)
entry = FPP_CR_LOG2_E;
break;
case 0x0e: // log10(e)
entry = FPP_CR_LOG10_E;
break;
case 0x0f: // 0.0
entry = FPP_CR_ZERO;
break;
case 0x30: // ln(2)
entry = FPP_CR_LN_2;
break;
case 0x31: // ln(10)
entry = FPP_CR_LN_10;
break;
case 0x32: // 1e0
entry = FPP_CR_1E0;
break;
case 0x33: // 1e1
entry = FPP_CR_1E1;
break;
case 0x34: // 1e2
entry = FPP_CR_1E2;
break;
case 0x35: // 1e4
entry = FPP_CR_1E4;
break;
case 0x36: // 1e8
entry = FPP_CR_1E8;
break;
case 0x37: // 1e16
entry = FPP_CR_1E16;
break;
case 0x38: // 1e32
entry = FPP_CR_1E32;
break;
case 0x39: // 1e64
entry = FPP_CR_1E64;
break;
case 0x3a: // 1e128
entry = FPP_CR_1E128;
break;
case 0x3b: // 1e256
entry = FPP_CR_1E256;
break;
case 0x3c: // 1e512
entry = FPP_CR_1E512;
break;
case 0x3d: // 1e1024
entry = FPP_CR_1E1024;
break;
case 0x3e: // 1e2048
entry = FPP_CR_1E2048;
break;
case 0x3f: // 1e4096
entry = FPP_CR_1E4096;
break;
default: // undefined
{
bool check_f1_adjust = false;
int f1_adjust = 0;
uae_u32 sr = 0;
if (cr > FPP_CR_NUM_SPECIAL_UNDEFINED) {
cr = 0; // Most undefined fields contain this
}
f[0] = fpp_cr_undef[cr].val[0];
f[1] = fpp_cr_undef[cr].val[1];
f[2] = fpp_cr_undef[cr].val[2];
// Rounding mode and precision works very strangely here..
switch (cr)
{
case 1:
check_f1_adjust = true;
break;
case 2:
if (prec == 1 && mode == 3)
f1_adjust = -1;
break;
case 3:
if (prec == 1 && (mode == 0 || mode == 3))
sr |= FPSR_CC_I;
else
sr |= FPSR_CC_NAN;
break;
case 7:
sr |= FPSR_CC_NAN;
check_f1_adjust = true;
break;
}
if (check_f1_adjust) {
if (prec == 1) {
if (mode == 0) {
f1_adjust = -1;
} else if (mode == 1 || mode == 2) {
f1_adjust = 1;
}
}
}
fpp_to_exten_fmovem(fpd, f[0], f[1], f[2]);
if (prec == 1)
fpp_round32(fpd);
if (prec >= 2)
fpp_round64(fpd);
if (f1_adjust) {
fpp_from_exten_fmovem(fpd, &f[0], &f[1], &f[2]);
f[1] += f1_adjust * 0x80;
fpp_to_exten_fmovem(fpd, f[0], f[1], f[2]);
}
fpsr_set_result(fpd);
regs.fpsr |= sr;
return false;
}
}
f[0] = fpp_cr[entry].val[0];
f[1] = fpp_cr[entry].val[1];
f[2] = fpp_cr[entry].val[2];
// if constant is inexact, set inexact bit and round
// note: with valid constants, LSB never wraps
if (fpp_cr[entry].inexact) {
fpsr_set_exception(FPSR_INEX2);
f[2] += fpp_cr[entry].rndoff[mode];
}
fpp_to_exten_fmovem(fpd, f[0], f[1], f[2]);
if (prec == 1)
fpp_round32(fpd);
if (prec >= 2)
fpp_round64(fpd);
fpsr_set_result(fpd);
return true;
}
#if 0
static void fpu_format_error (void)
{
uaecptr newpc;
regs.t0 = regs.t1 = 0;
MakeSR ();
if (!regs.s) {
regs.usp = m68k_areg (regs, 7);
m68k_areg (regs, 7) = regs.isp;
}
regs.s = 1;
m68k_areg (regs, 7) -= 2;
x_cp_put_long (m68k_areg (regs, 7), 0x0000 + 14 * 4);
m68k_areg (regs, 7) -= 4;
x_cp_put_long (m68k_areg (regs, 7), m68k_getpc ());
m68k_areg (regs, 7) -= 2;
x_cp_put_long (m68k_areg (regs, 7), regs.sr);
newpc = x_cp_get_long (regs.vbr + 14 * 4);
m68k_setpc (newpc);
#ifdef JIT
set_special (SPCFLAG_END_COMPILE);
#endif
regs.fp_exception = true;
}
#endif
static void fp_unimp_instruction(uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc, fpdata *src, int reg, int size)
{
if ((extra & 0x7f) == 4) // FSQRT 4->5
extra |= 1;
// data for fsave stack frame
regs.fpu_exp_state = 1; // 68060 IDLE frame, 68040 UNIMP frame
if (currprefs.cpu_model == 68060) {
// fsave data for 68060
reset_fsave_data();
} else if(currprefs.cpu_model == 68040) {
// fsave data for 68040
fsave_data.fpiarcu = regs.fpiar;
if (regs.fp_unimp_pend == 0) { // else data has been saved by fp_unimp_datatype
reset_fsave_data();
fsave_data.cmdreg3b = (extra & 0x3C3) | ((extra & 0x038) >> 1) | ((extra & 0x004) << 3);
fsave_data.cmdreg1b = extra;
fpp_from_exten_fmovem(src, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]);
fsave_data.stag = get_ftag(src, size);
if (reg >= 0) {
fpp_from_exten_fmovem(®s.fp[reg], &fsave_data.fpt[0], &fsave_data.fpt[1], &fsave_data.fpt[2]);
fsave_data.dtag = get_ftag(®s.fp[reg], -1);
}
}
}
if (warned > 0) {
write_log (_T("FPU unimplemented instruction: OP=%04X-%04X SRC=%08X-%08X-%08X EA=%08X PC=%08X\n"),
opcode, extra, fsave_data.et[0],fsave_data.et[1],fsave_data.et[2], ea, oldpc);
#if EXCEPTION_FPP == 0
warned--;
#endif
}
regs.fp_ea = ea;
regs.fp_unimp_ins = true;
fp_unimp_instruction_exception_pending();
regs.fp_exception = true;
}
static void fp_unimp_datatype(uae_u16 opcode, uae_u16 extra, uae_u32 ea, uaecptr oldpc, fpdata *src, uae_u32 *packed)
{
uae_u32 reg = (extra >> 7) & 7;
uae_u32 size = (extra >> 10) & 7;
uae_u32 opclass = (extra >> 13) & 7;
regs.fp_opword = opcode;
regs.fp_ea = ea;
regs.fp_unimp_pend = packed ? 2 : 1;
if((extra & 0x7f) == 4) // FSQRT 4->5
extra |= 1;
// data for fsave stack frame
reset_fsave_data();
regs.fpu_exp_state = 2; // 68060 EXCP frame, 68040 BUSY frame
if (currprefs.cpu_model == 68060) {
// fsave data for 68060
if (packed) {
regs.fpu_exp_state = 1; // 68060 IDLE frame
} else {
fsave_data.v = 7; // vector & 0x7
fpp_from_exten_fmovem(src, &fsave_data.eo[0], &fsave_data.eo[1], &fsave_data.eo[2]);
}
} else if (currprefs.cpu_model == 68040) {
// fsave data for 68040
fsave_data.cmdreg1b = extra;
fsave_data.fpiarcu = regs.fpiar;
if (packed) {
fsave_data.e1 = 1; // used to distinguish packed operands
}
if (opclass == 3) { // OPCLASS 011
fsave_data.t = 1;
fpp_from_exten_fmovem(src, &fsave_data.et[0], &fsave_data.et[1], &fsave_data.et[2]);
fsave_data.stag = get_ftag(src, -1);
fpp_from_exten_fmovem(src, &fsave_data.fpt[0], &fsave_data.fpt[1], &fsave_data.fpt[2]); // undocumented
fsave_data.dtag = get_ftag(src, -1); // undocumented
} else { // OPCLASS 000 and 010
if (packed) {