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custom.cpp
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custom.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* Copyright 1995-2002 Bernd Schmidt
* Copyright 1995 Alessandro Bissacco
* Copyright 2000-2015 Toni Wilen
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include <assert.h>
#include <math.h>
#include "options.h"
#include "uae.h"
#include "gensound.h"
#include "audio.h"
#include "sounddep/sound.h"
#include "events.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cia.h"
#include "disk.h"
#include "blitter.h"
#include "xwin.h"
#include "inputdevice.h"
#include "serial.h"
#include "autoconf.h"
#include "traps.h"
#include "gui.h"
#include "picasso96.h"
#include "drawing.h"
#include "savestate.h"
#include "ar.h"
#include "debug.h"
#include "akiko.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
#include "threaddep/thread.h"
#include "luascript.h"
#include "devices.h"
#include "rommgr.h"
#include "specialmonitors.h"
#define CUSTOM_DEBUG 0
#define SPRITE_DEBUG 0
#define SPRITE_DEBUG_MINY 0
#define SPRITE_DEBUG_MAXY 0x30
#define SPR0_HPOS 0x15
#define MAX_SPRITES 8
#define SPEEDUP 1
#define AUTOSCALE_SPRITES 1
#define ALL_SUBPIXEL 1
#define SPRBORDER 0
extern uae_u16 serper;
STATIC_INLINE bool nocustom (void)
{
struct amigadisplay *ad = &adisplays[0];
if (ad->picasso_on && currprefs.picasso96_nocustom)
return true;
return false;
}
static void uae_abort (const TCHAR *format,...)
{
static int nomore;
va_list parms;
TCHAR buffer[1000];
va_start (parms, format);
_vsntprintf (buffer, sizeof (buffer) / sizeof(TCHAR) - 1, format, parms );
va_end (parms);
if (nomore) {
write_log (_T("%s\n"), buffer);
return;
}
gui_message (buffer);
nomore = 1;
}
#if 0
void customhack_put (struct customhack *ch, uae_u16 v, int hpos)
{
ch->v = v;
ch->vpos = vpos;
ch->hpos = hpos;
}
uae_u16 customhack_get (struct customhack *ch, int hpos)
{
if (ch->vpos == vpos && ch->hpos == hpos) {
ch->vpos = -1;
return 0xffff;
}
return ch->v;
}
#endif
static unsigned int n_consecutive_skipped = 0;
static unsigned int total_skipped = 0;
extern int cpu_last_stop_vpos, cpu_stopped_lines;
static int cpu_sleepmode, cpu_sleepmode_cnt;
extern int vsync_activeheight, vsync_totalheight;
extern float vsync_vblank, vsync_hblank;
STATIC_INLINE void sync_copper (int hpos);
/* Events */
unsigned long int vsync_cycles;
static int extra_cycle;
static int rpt_did_reset;
struct ev eventtab[ev_max];
struct ev2 eventtab2[ev2_max];
int hpos_offset;
int vpos;
static int vpos_count, vpos_count_diff;
int lof_store; // real bit in custom registers
static int lof_current; // what display device thinks
static bool lof_lastline, lof_prev_lastline;
static int lol;
static int next_lineno, prev_lineno;
static enum nln_how nextline_how;
static int lof_changed = 0, lof_changing = 0, interlace_changed = 0;
static int lof_changed_previous_field;
static int vposw_change;
static bool lof_lace;
static bool bplcon0_interlace_seen;
static int scandoubled_line;
static bool vsync_rendered, frame_rendered, frame_shown;
static int vsynctimeperline;
static int frameskiptime;
static bool genlockhtoggle;
static bool genlockvtoggle;
static bool graphicsbuffer_retry;
static int scanlinecount;
static int cia_hsync;
static bool toscr_scanline_complex_bplcon1;
#define LOF_TOGGLES_NEEDED 3
//#define NLACE_CNT_NEEDED 50
static int lof_togglecnt_lace, lof_togglecnt_nlace; //, nlace_cnt;
/* Stupid genlock-detection prevention hack.
* We should stop calling vsync_handler() and
* hstop_handler() completely but it is not
* worth the trouble..
*/
static int vpos_previous, hpos_previous;
static int vpos_lpen, hpos_lpen, hhpos_lpen, lightpen_triggered;
int lightpen_x[2], lightpen_y[2];
int lightpen_cx[2], lightpen_cy[2], lightpen_active, lightpen_enabled, lightpen_enabled2;
static uae_u32 sprtaba[256],sprtabb[256];
static uae_u32 sprite_ab_merge[256];
/* Tables for collision detection. */
static uae_u32 sprclx[16], clxmask[16];
/* T genlock bit in ECS Denise and AGA color registers */
static uae_u8 color_regs_genlock[256];
/*
* Hardware registers of all sorts.
*/
static int REGPARAM3 custom_wput_1 (int, uaecptr, uae_u32, int) REGPARAM;
static uae_u16 cregs[256];
uae_u16 intena, intreq;
uae_u16 dmacon;
uae_u16 adkcon; /* used by audio code */
uae_u32 last_custom_value1;
uae_u16 last_custom_value2;
static uae_u32 cop1lc, cop2lc, copcon;
int maxhpos = MAXHPOS_PAL;
int maxhpos_short = MAXHPOS_PAL;
int maxvpos = MAXVPOS_PAL;
int maxvpos_nom = MAXVPOS_PAL; // nominal value (same as maxvpos but "faked" maxvpos in fake 60hz modes)
int maxvpos_display = MAXVPOS_PAL; // value used for display size
int hsyncendpos, hsyncstartpos;
static int maxvpos_total = 511;
int minfirstline = VBLANK_ENDLINE_PAL;
int firstblankedline;
static int equ_vblank_endline = EQU_ENDLINE_PAL;
static bool equ_vblank_toggle = true;
float vblank_hz = VBLANK_HZ_PAL, fake_vblank_hz, vblank_hz_stored, vblank_hz_nom;
float hblank_hz;
static float vblank_hz_lof, vblank_hz_shf, vblank_hz_lace;
static int vblank_hz_mult, vblank_hz_state;
static struct chipset_refresh *stored_chipset_refresh;
int doublescan;
bool programmedmode;
int syncbase;
static int fmode_saved, fmode;
uae_u16 beamcon0, new_beamcon0;
static uae_u16 beamcon0_saved;
static uae_u16 bplcon0_saved, bplcon1_saved, bplcon2_saved;
static uae_u16 bplcon3_saved, bplcon4_saved;
static bool varsync_changed;
uae_u16 vtotal = MAXVPOS_PAL, htotal = MAXHPOS_PAL;
static int maxvpos_stored, maxhpos_stored;
static uae_u16 hsstop, hbstrt, hbstop, vsstop, vbstrt, vbstop, hsstrt, vsstrt, hcenter;
static uae_u16 sprhstrt, sprhstop, bplhstrt, bplhstop, hhpos, hhpos_hpos;
static int hhbpl, hhspr;
static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static int diw_hcounter;
static uae_u16 refptr;
static uae_u32 refptr_val;
#define HSYNCTIME (maxhpos * CYCLE_UNIT)
struct sprite {
uaecptr pt;
int xpos;
int vstart;
int vstop;
int dblscan; /* AGA SSCAN2 */
int armed;
int dmastate;
int dmacycle;
int ptxhpos;
int ptxhpos2, ptxvpos2;
bool ignoreverticaluntilnextline;
int width;
uae_u16 ctl, pos;
#ifdef AGA
uae_u16 data[4], datb[4];
#else
uae_u16 data[1], datb[1];
#endif
};
static struct sprite spr[MAX_SPRITES];
static int plfstrt_sprite;
static bool sprite_ignoreverticaluntilnextline;
uaecptr sprite_0;
int sprite_0_width, sprite_0_height, sprite_0_doubled;
uae_u32 sprite_0_colors[4];
static uae_u8 magic_sprite_mask = 0xff;
static int sprite_vblank_endline = VBLANK_SPRITE_PAL;
static int last_sprite_point, nr_armed;
static int sprite_width, sprres;
static int sprite_sprctlmask;
int sprite_buffer_res;
#ifdef CPUEMU_13
uae_u8 cycle_line[256 + 1];
#endif
static bool bpl1dat_written, bpl1dat_written_at_least_once;
static bool bpldmawasactive;
static uae_s16 bpl1mod, bpl2mod, dbpl1mod, dbpl2mod;
static int dbpl1mod_on, dbpl2mod_on;
static uaecptr prevbpl[2][MAXVPOS][8];
static uaecptr bplpt[8], bplptx[8];
#if 0
static uaecptr dbplptl[8], dbplpth[8];
static int dbplptl_on[8], dbplpth_on[8], dbplptl_on2, dbplpth_on2;
#endif
static int bitplane_line_crossing;
static struct color_entry current_colors;
uae_u16 bplcon0;
static uae_u16 bplcon1, bplcon2, bplcon3, bplcon4;
static int bplcon0d, bplcon0d_old;
static uae_u32 bplcon0_res, bplcon0_planes, bplcon0_planes_limit;
static int bplcon0_res_hr;
static int diwstrt, diwstop, diwhigh;
static int diwhigh_written;
static int ddfstrt, ddfstop;
static int line_cyclebased, badmode, diw_change;
static int bplcon1_fetch;
static int hpos_is_zero_bplcon1_hack = -1;
#define SET_LINE_CYCLEBASED line_cyclebased = 2;
/* The display and data fetch windows */
enum diw_states
{
DIW_waiting_start, DIW_waiting_stop
};
static int plffirstline, plflastline;
int plffirstline_total, plflastline_total;
static int autoscale_bordercolors;
static int plfstrt, plfstop;
static int sprite_minx;
static int first_bpl_vpos;
static int last_ddf_pix_hpos;
static int last_decide_line_hpos;
static int last_fetch_hpos, last_sprite_hpos;
static int diwfirstword, diwlastword;
static int last_hdiw;
static enum diw_states diwstate, hdiwstate, ddfstate;
static int bpl_hstart;
int first_planes_vpos, last_planes_vpos;
static int first_bplcon0, first_bplcon0_old;
static int first_planes_vpos_old, last_planes_vpos_old;
int diwfirstword_total, diwlastword_total;
int ddffirstword_total, ddflastword_total;
static int diwfirstword_total_old, diwlastword_total_old;
static int ddffirstword_total_old, ddflastword_total_old;
bool vertical_changed, horizontal_changed;
int firstword_bplcon1;
static int last_copper_hpos;
static int copper_access;
/* Sprite collisions */
static unsigned int clxdat, clxcon, clxcon2, clxcon_bpl_enable, clxcon_bpl_match;
enum copper_states {
COP_stop,
COP_waitforever,
COP_read1,
COP_read2,
COP_bltwait,
COP_wait_in2,
COP_skip_in2,
COP_wait1,
COP_wait,
COP_skip1,
COP_strobe_delay1,
COP_strobe_delay2,
COP_strobe_delay1x,
COP_strobe_delay2x,
COP_strobe_extra, // just to skip current cycle when CPU wrote to COPJMP
COP_start_delay
};
struct copper {
/* The current instruction words. */
unsigned int i1, i2;
unsigned int saved_i1, saved_i2;
enum copper_states state, state_prev;
/* Instruction pointer. */
uaecptr ip, saved_ip;
int hpos, vpos;
unsigned int ignore_next;
int vcmp, hcmp;
int strobe; /* COPJMP1 / COPJMP2 accessed */
int last_strobe;
int moveaddr, movedata, movedelay;
};
static struct copper cop_state;
static int copper_enabled_thisline;
static int cop_min_waittime;
/*
* Statistics
*/
unsigned long int frametime = 0, lastframetime = 0, timeframes = 0;
unsigned long hsync_counter = 0, vsync_counter = 0;
unsigned long int idletime;
int bogusframe;
/* Recording of custom chip register changes. */
static int current_change_set;
static struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
static struct color_change color_changes[2][MAX_REG_CHANGE];
struct decision line_decisions[2 * (MAXVPOS + 2) + 1];
static struct draw_info line_drawinfo[2][2 * (MAXVPOS + 2) + 1];
#define COLOR_TABLE_SIZE (MAXVPOS + 2) * 2
static struct color_entry color_tables[2][COLOR_TABLE_SIZE];
static int next_sprite_entry = 0;
static int prev_next_sprite_entry;
static int next_sprite_forced = 1;
struct sprite_entry *curr_sprite_entries, *prev_sprite_entries;
struct color_change *curr_color_changes, *prev_color_changes;
struct draw_info *curr_drawinfo, *prev_drawinfo;
struct color_entry *curr_color_tables, *prev_color_tables;
static int next_color_change;
static int next_color_entry, remembered_color_entry;
static int color_src_match, color_dest_match, color_compare_result;
static uae_u32 thisline_changed;
#ifdef SMART_UPDATE
#define MARK_LINE_CHANGED do { thisline_changed = 1; } while (0)
#else
#define MARK_LINE_CHANGED do { ; } while (0)
#endif
static struct decision thisline_decision;
static int fetch_cycle, fetch_modulo_cycle;
static int aga_plf_passed_stop2;
static int plf_start_hpos, plf_end_hpos;
static int ddfstop_written_hpos;
static int bitplane_off_delay;
static bool ocs_agnus_ddf_enable_toggle;
static int bpl_dma_off_when_active;
static int bitplane_maybe_start_hpos;
static bool ddfstop_matched;
static int bitplane_overrun, bitplane_overrun_hpos;
static int bitplane_overrun_fetch_cycle, bitplane_overrun_cycle_diagram_shift;
struct custom_store custom_storage[256];
enum plfstate
{
plf_idle,
// enable passed
plf_passed_enable,
// ddfstrt match
plf_passed_start,
// active (ddfstrt + 4 match)
plf_active,
// inactive, waiting
plf_wait,
// ddfstop passed
plf_passed_stop,
// ddfstop+4 passed
plf_passed_stop_act,
// last block finished
plf_passed_stop2,
plf_end
} plf_state;
enum plfrenderstate
{
plfr_idle,
plfr_active,
plfr_end,
plfr_finished
} plfr_state;
enum fetchstate {
fetch_not_started,
fetch_started_first,
fetch_started,
fetch_was_plane0
} fetch_state;
/*
* helper functions
*/
STATIC_INLINE int ecsshres(void)
{
return bplcon0_res == RES_SUPERHIRES && (currprefs.chipset_mask & CSMASK_ECS_DENISE) && !(currprefs.chipset_mask & CSMASK_AGA);
}
STATIC_INLINE int nodraw(void)
{
struct amigadisplay *ad = &adisplays[0];
return !currprefs.cpu_memory_cycle_exact && ad->framecnt != 0;
}
static int doflickerfix (void)
{
return currprefs.gfx_vresolution && doublescan < 0 && vpos < MAXVPOS;
}
uae_u32 get_copper_address (int copno)
{
switch (copno) {
case 1: return cop1lc;
case 2: return cop2lc;
case -1: return cop_state.ip;
default: return 0;
}
}
void reset_frame_rate_hack (void)
{
if (currprefs.m68k_speed >= 0)
return;
rpt_did_reset = 1;
events_reset_syncline();
vsyncmintime = read_processor_time () + vsynctimebase;
write_log (_T("Resetting frame rate hack\n"));
}
STATIC_INLINE void setclr (uae_u16 *p, uae_u16 val)
{
if (val & 0x8000)
*p |= val & 0x7FFF;
else
*p &= ~val;
}
STATIC_INLINE void alloc_cycle (int hpos, int type)
{
#ifdef CPUEMU_13
#if 0
if (cycle_line[hpos])
write_log (_T("hpos=%d, old=%d, new=%d\n"), hpos, cycle_line[hpos], type);
if ((type == CYCLE_COPPER) && (hpos & 1) && hpos != maxhpos - 2)
write_log (_T("odd %d cycle %d\n"), hpos);
if (!(hpos & 1) && (type == CYCLE_SPRITE || type == CYCLE_REFRESH || type == CYCLE_MISC))
write_log (_T("even %d cycle %d\n"), type, hpos);
#endif
cycle_line[hpos] = type;
#endif
}
STATIC_INLINE void alloc_cycle_maybe (int hpos, int type)
{
if ((cycle_line[hpos] & CYCLE_MASK) == 0)
alloc_cycle (hpos, type);
}
void alloc_cycle_ext (int hpos, int type)
{
alloc_cycle (hpos, type);
}
void alloc_cycle_blitter (int hpos, uaecptr *ptr, int chnum)
{
if (cycle_line[hpos] & CYCLE_COPPER_SPECIAL) {
if ((currprefs.cs_hacks & 1) && currprefs.cpu_model == 68000) {
uaecptr srcptr = cop_state.strobe == 1 ? cop1lc : cop2lc;
//if (currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact && currprefs.blitter_cycle_exact) {
// batman group / batman vuelve triggers this incorrectly. More testing needed.
*ptr = srcptr;
//activate_debugger();
}
}
alloc_cycle (hpos, CYCLE_BLITTER);
}
static int expand_sprres(uae_u16 con0, uae_u16 con3)
{
int res;
switch ((con3 >> 6) & 3)
{
default:
res = RES_LORES;
break;
#ifdef ECS_DENISE
case 0: /* ECS defaults (LORES,HIRES=LORES sprite,SHRES=HIRES sprite) */
if ((currprefs.chipset_mask & CSMASK_ECS_DENISE) && GET_RES_DENISE(con0) == RES_SUPERHIRES)
res = RES_HIRES;
else
res = RES_LORES;
break;
#endif
#ifdef AGA
case 1:
res = RES_LORES;
break;
case 2:
res = RES_HIRES;
break;
case 3:
res = RES_SUPERHIRES;
break;
#endif
}
return res;
}
STATIC_INLINE uae_u8 *pfield_xlateptr (uaecptr plpt, int bytecount)
{
if (!chipmem_check_indirect (plpt, bytecount)) {
static int count = 0;
if (!count)
count++, write_log (_T("Warning: Bad playfield pointer %08x\n"), plpt);
return NULL;
}
return chipmem_xlate_indirect (plpt);
}
static void docols (struct color_entry *colentry)
{
int i;
#ifdef AGA
if (currprefs.chipset_mask & CSMASK_AGA) {
for (i = 0; i < 256; i++) {
int v = color_reg_get (colentry, i);
if (v < 0 || v > 16777215)
continue;
colentry->acolors[i] = getxcolor (v);
}
} else {
#endif
for (i = 0; i < 32; i++) {
int v = color_reg_get (colentry, i);
if (v < 0 || v > 4095)
continue;
colentry->acolors[i] = getxcolor (v);
}
#ifdef AGA
}
#endif
}
static void do_sprites (int currhp);
static void remember_ctable (void)
{
/* This can happen when program crashes very badly */
if (next_color_entry >= COLOR_TABLE_SIZE)
return;
if (remembered_color_entry < 0) {
/* The colors changed since we last recorded a color map. Record a
* new one. */
color_reg_cpy (curr_color_tables + next_color_entry, ¤t_colors);
remembered_color_entry = next_color_entry++;
}
thisline_decision.ctable = remembered_color_entry;
if (color_src_match < 0 || color_dest_match != remembered_color_entry
|| line_decisions[next_lineno].ctable != color_src_match)
{
/* The remembered comparison didn't help us - need to compare again. */
int oldctable = line_decisions[next_lineno].ctable;
int changed = 0;
if (oldctable < 0) {
changed = 1;
color_src_match = color_dest_match = -1;
} else {
color_compare_result = color_reg_cmp (&prev_color_tables[oldctable], ¤t_colors) != 0;
if (color_compare_result)
changed = 1;
color_src_match = oldctable;
color_dest_match = remembered_color_entry;
}
thisline_changed |= changed;
} else {
/* We know the result of the comparison */
if (color_compare_result)
thisline_changed = 1;
}
}
static void remember_ctable_for_border (void)
{
remember_ctable ();
}
STATIC_INLINE int get_equ_vblank_endline (void)
{
return equ_vblank_endline + (equ_vblank_toggle ? (lof_current ? 1 : 0) : 0);
}
#define DDF_OFFSET 4
#define HARD_DDF_LIMITS_DISABLED ((beamcon0 & 0x80) || (beamcon0 & 0x4000) || (bplcon0 & 0x40))
/* The HRM says 0xD8, but that can't work... */
#define HARD_DDF_STOP (HARD_DDF_LIMITS_DISABLED ? maxhpos : 0xd4)
#define HARD_DDF_START_REAL 0x14
/* Programmed rates or superhires (!) disable normal DMA limits */
#define HARD_DDF_START (HARD_DDF_LIMITS_DISABLED ? 0x04 : 0x14)
/* Called to determine the state of the horizontal display window state
* machine at the current position. It might have changed since we last
* checked. */
static void decide_diw(int hpos)
{
/* Last hpos = hpos + 0.5, eg. normal PAL end hpos is 227.5 * 2 = 455
OCS Denise: 9 bit hdiw counter does not reset during lines 0 to 9
(PAL) or lines 0 to 10 (NTSC). A1000 PAL: 1 to 9, NTSC: 1 to 10.
ECS Denise and AGA: no above "features"
*/
int hdiw = hpos >= maxhpos ? maxhpos * 2 + 1 : hpos * 2 + 2;
if (!(currprefs.chipset_mask & CSMASK_ECS_DENISE) && vpos <= get_equ_vblank_endline())
hdiw = diw_hcounter;
/* always mask, bad programs may have set maxhpos = 256 */
hdiw &= 511;
for (;;) {
int lhdiw = hdiw;
if (last_hdiw > lhdiw)
lhdiw = 512;
if (lhdiw >= diw_hstrt && last_hdiw < diw_hstrt && hdiwstate == DIW_waiting_start) {
if (thisline_decision.diwfirstword < 0)
thisline_decision.diwfirstword = diwfirstword < 0 ? min_diwlastword : diwfirstword;
hdiwstate = DIW_waiting_stop;
}
if ((lhdiw >= diw_hstop && last_hdiw < diw_hstop) && hdiwstate == DIW_waiting_stop) {
if (thisline_decision.diwlastword < 0)
thisline_decision.diwlastword = diwlastword < 0 ? 0 : diwlastword;
hdiwstate = DIW_waiting_start;
}
if (lhdiw != 512)
break;
last_hdiw = 0 - 1;
}
last_hdiw = hdiw;
}
static int fetchmode, fetchmode_size, fetchmode_mask, fetchmode_bytes;
static int fetchmode_fmode_bpl, fetchmode_fmode_spr;
static int fetchmode_size_hr, fetchmode_mask_hr;
static int real_bitplane_number[3][3][9];
/* Disable bitplane DMA if planes > available DMA slots. This is needed
e.g. by the Sanity WOC demo (at the "Party Effect"). */
STATIC_INLINE int GET_PLANES_LIMIT(uae_u16 bc0)
{
int res = GET_RES_AGNUS(bc0);
int planes = GET_PLANES(bc0);
return real_bitplane_number[fetchmode][res][planes];
}
#if 0
static void reset_dbplh(int hpos, int num)
{
if (dbplpth_on[num] && hpos >= dbplpth_on[num]) {
bplpt[num] = dbplpth[num] | (bplpt[num] & 0x0000fffe);
dbplpth_on[num] = 0;
dbplpth_on2--;
}
}
static void reset_dbplh_all(int hpos)
{
if (dbplpth_on2) {
for (int num = 0; num < MAX_PLANES; num++) {
reset_dbplh(hpos, num);
}
dbplpth_on2 = 0;
}
}
static void reset_dbpll(int hpos, int num)
{
if (dbplptl_on[num] && hpos >= dbplptl_on[num]) {
bplpt[num] = (bplpt[num] & 0xffff0000) | dbplptl[num];
dbplptl_on[num] = 0;
dbplptl_on2--;
}
}
static void reset_dbpll_all(int hpos)
{
if (dbplptl_on2) {
for (int num = 0; num < MAX_PLANES; num++) {
reset_dbpll(hpos, num);
}
dbplptl_on2 = 0;
}
}
#endif
static void reset_moddelays(void)
{
if (dbpl1mod_on > 0) {
bpl1mod = dbpl1mod;
dbpl1mod_on = 0;
}
if (dbpl2mod_on > 0) {
bpl2mod = dbpl2mod;
dbpl2mod_on = 0;
}
}
static void add_mod(int nr, int mod)
{
#ifdef AGA
if (fetchmode_fmode_bpl == 1 || fetchmode_fmode_bpl == 2) {
// FMODE=1/2, unaligned bpl and modulo: bit 1 carry is ignored.
if ((bplpt[nr] & 2) && (mod & 2)) {
mod -= 4;
}
} else if (fetchmode_fmode_bpl == 3) {
// FMODE=3, unaligned bpl and modulo: bit 2 carry is ignored.
if ((bplpt[nr] & (4 | 2)) + (mod & (4 | 2)) >= 8) {
mod -= 8;
}
}
#endif
bplpt[nr] += mod;
bplptx[nr] += mod;
}
static void add_modulo (int hpos, int nr)
{
int mod;
if (dbpl1mod_on != hpos && dbpl1mod_on) {
bpl1mod = dbpl1mod;
dbpl1mod_on = 0;
}
if (dbpl2mod_on != hpos && dbpl2mod_on) {
bpl2mod = dbpl2mod;
dbpl2mod_on = 0;
}
if (fmode & 0x4000) {
if (((diwstrt >> 8) ^ vpos) & 1)
mod = bpl2mod;
else
mod = bpl1mod;
} else if (nr & 1)
mod = bpl2mod;
else
mod = bpl1mod;
add_mod(nr, mod);
reset_moddelays ();
#if 0
reset_dbpll_all (-1);
#endif
}
static void add_modulos (void)
{
int m1, m2;
reset_moddelays ();
#if 0
reset_dbpll_all(-1);
#endif
if (fmode & 0x4000) {
if (((diwstrt >> 8) ^ vpos) & 1)
m1 = m2 = bpl2mod;
else
m1 = m2 = bpl1mod;
} else {
m1 = bpl1mod;
m2 = bpl2mod;
}
switch (bplcon0_planes_limit) {
#ifdef AGA
case 8: add_mod(7, m2);
case 7: add_mod(6, m1);
#endif
case 6: add_mod(5, m2);
case 5: add_mod(4, m1);
case 4: add_mod(3, m2);
case 3: add_mod(2, m1);
case 2: add_mod(1, m2);
case 1: add_mod(0, m1);
}
}
static void finish_playfield_line (void)
{
/* The latter condition might be able to happen in interlaced frames. */
if (vpos >= minfirstline && (thisframe_first_drawn_line < 0 || vpos < thisframe_first_drawn_line))
thisframe_first_drawn_line = vpos;
thisframe_last_drawn_line = vpos;
#ifdef SMART_UPDATE
if (line_decisions[next_lineno].plflinelen != thisline_decision.plflinelen
|| line_decisions[next_lineno].plfleft != thisline_decision.plfleft
|| line_decisions[next_lineno].bplcon0 != thisline_decision.bplcon0
|| line_decisions[next_lineno].bplcon2 != thisline_decision.bplcon2
#ifdef ECS_DENISE
|| line_decisions[next_lineno].bplcon3 != thisline_decision.bplcon3
#endif
#ifdef AGA
|| line_decisions[next_lineno].bplcon4 != thisline_decision.bplcon4
|| line_decisions[next_lineno].fmode != thisline_decision.fmode
#endif
)
#endif /* SMART_UPDATE */
thisline_changed = 1;
}
/* The fetch unit mainly controls ddf stop. It's the number of cycles that
are contained in an indivisible block during which ddf is active. E.g.
if DDF starts at 0x30, and fetchunit is 8, then possible DDF stops are
0x30 + n * 8. */
static int fetchunit, fetchunit_mask;
/* The delay before fetching the same bitplane again. Can be larger than
the number of bitplanes; in that case there are additional empty cycles
with no data fetch (this happens for high fetchmodes and low
resolutions). */
static int fetchstart, fetchstart_shift, fetchstart_mask;
/* fm_maxplane holds the maximum number of planes possible with the current
fetch mode. This selects the cycle diagram:
8 planes: 73516240
4 planes: 3120
2 planes: 10. */
static int fm_maxplane, fm_maxplane_shift;
/* The corresponding values, by fetchmode and display resolution. */
static const int fetchunits[] = { 8,8,8,0, 16,8,8,0, 32,16,8,0 };
static const int fetchstarts[] = { 3,2,1,0, 4,3,2,0, 5,4,3,0 };
static const int fm_maxplanes[] = { 3,2,1,0, 3,3,2,0, 3,3,3,0 };
static int cycle_diagram_table[3][3][9][32];
static int cycle_diagram_free_cycles[3][3][9];
static int cycle_diagram_total_cycles[3][3][9];
static int *curr_diagram;
static const int cycle_sequences[3 * 8] = { 2,1,2,1,2,1,2,1, 4,2,3,1,4,2,3,1, 8,4,6,2,7,3,5,1 };
static void debug_cycle_diagram (void)
{
int fm, res, planes, cycle, v;
TCHAR aa;
for (fm = 0; fm <= 2; fm++) {
write_log (_T("FMODE %d\n=======\n"), fm);
for (res = 0; res <= 2; res++) {
for (planes = 0; planes <= 8; planes++) {
write_log (_T("%d: "),planes);
for (cycle = 0; cycle < 32; cycle++) {
v=cycle_diagram_table[fm][res][planes][cycle];
if (v==0) aa='-'; else if(v>0) aa='1'; else aa='X';
write_log (_T("%c"),aa);
}
write_log (_T(" %d:%d\n"),
cycle_diagram_free_cycles[fm][res][planes], cycle_diagram_total_cycles[fm][res][planes]);
}
write_log (_T("\n"));
}
}
fm=0;
}
static void create_cycle_diagram_table (void)
{
int fm, res, cycle, planes, rplanes, v;
int fetch_start, max_planes, freecycles;
const int *cycle_sequence;
for (fm = 0; fm <= 2; fm++) {
for (res = 0; res <= 2; res++) {
max_planes = fm_maxplanes[fm * 4 + res];
fetch_start = 1 << fetchstarts[fm * 4 + res];
cycle_sequence = &cycle_sequences[(max_planes - 1) * 8];
max_planes = 1 << max_planes;
for (planes = 0; planes <= 8; planes++) {
freecycles = 0;
for (cycle = 0; cycle < 32; cycle++)
cycle_diagram_table[fm][res][planes][cycle] = -1;
if (planes <= max_planes) {
for (cycle = 0; cycle < fetch_start; cycle++) {
if (cycle < max_planes && planes >= cycle_sequence[cycle & 7]) {
v = cycle_sequence[cycle & 7];
} else {
v = 0;
freecycles++;
}
cycle_diagram_table[fm][res][planes][cycle] = v;
}
}
cycle_diagram_free_cycles[fm][res][planes] = freecycles;
cycle_diagram_total_cycles[fm][res][planes] = fetch_start;
rplanes = planes;
if (rplanes > max_planes)
rplanes = 0;
if (rplanes == 7 && fm == 0 && res == 0 && !(currprefs.chipset_mask & CSMASK_AGA))
rplanes = 4;
real_bitplane_number[fm][res][planes] = rplanes;
}
}
}
#if 0
debug_cycle_diagram ();
#endif
}
/* Used by the copper. */
static int estimated_last_fetch_cycle;
static int cycle_diagram_shift;
static void estimate_last_fetch_cycle (int hpos)
{
int fetchunit = fetchunits[fetchmode * 4 + bplcon0_res];
// Last fetch is always max 8 even if fetchunit is larger.
int lastfetchunit = fetchunit >= 8 ? 8 : fetchunit;
if (plf_state < plf_passed_stop) {
int stop;
if (currprefs.chipset_mask & CSMASK_ECS_AGNUS) {
// ECS: stop wins if start == stop
stop = plfstop + DDF_OFFSET < hpos || plfstop > HARD_DDF_STOP ? HARD_DDF_STOP : plfstop;
} else {
// OCS: start wins if start == stop
stop = plfstop + DDF_OFFSET <= hpos || plfstop > HARD_DDF_STOP ? HARD_DDF_STOP : plfstop;
}
/* We know that fetching is up-to-date up until hpos, so we can use fetch_cycle. */
int fetch_cycle_at_stop = fetch_cycle + (stop - hpos + DDF_OFFSET);