Simple steering layout

[Alex-Walsh]

Ready for design review. The board shape needs to be changed (to fit the electronics) and I think some designators should be removed/ changed, just not sure which ones to do that to.

[ethanmpeterson]

Let's start with the layout checklist

Layout Checklist

• No DRC errors => Still has 20 hole to hole distance errors. Otherwise looks really good!
• All SMD parts on one layer
• IR Calculations for high current traces
  The width should be large enough such that temperature increase for the expected current is no more than 5 to 10 degrees celsius => Going to waive this one, board is very low power.
• Board is mechanically sound, dimensions are correct and component height does not create mechanical conflicts => This board does not need to fit on the car this year. If we end up using it in future, it would probably make sense to re do the layout to follow the steering package design.
• IO ports and connectors double checked such that they are accessible when the board is fully assembled
  No unconnected ground (remove dead copper button checked on Altium polygon object or add stitching via)
• Ground pour on top and bottom layers. => Let's add a top layer pour.
• Stitching vias
• Length matching for high speed signals and differential pairs => N/A
• Proper filter capacitor placement for MCU layout (as close to the pin as possible and in the path of current flow) => I think most are good, will comment more below.

General Comments

• No via sharing. each capacitor and resistor here should get their own via. This avoids coupling between the components and reduces the induction in the path to ground. Vias also don't cost us anything here, so might as well use them freely.
  

• Extend the polygon to wrap fully around the pad so it connects at all four points. I see a few other instances of this in the design as well. Do a quick check to correct any of them that you see
  

• Nitpick: clean up the edges
  

• we should widen up the thermal relief for 5V / GND power nets. I can show you how to do this.
  

• This is reset right? Name the net ATMEGA_RST_n or something readable
  

• 90 degree traces are sometimes ill advised because they can create acid traps. I don't think any of our fabs use this process but it is still one to avoid.
  

• This section can also be cleaned up a little bit, I would inline the resistor like so:
  

• I would also do something similar here:
  
  

• Why this polygon cutout here?
  

• Also, it is good for digital signals with higher switching frequencies to place a GND via nearby to shorten the return path. Like so:
  

• Remember to add ground underneath for this to work

• Avoid via sharing and via in pad
  

• Straighten out these polygon edges. clean up the capacitor connection
  

• Straighten out this edge and ensure the polygon connects on all four sides.
  

• Avoid shared vias
  

• Bring this via in closer the pad, longer trace = more inductance
  

• We wired this CAN termination resistor wrong. Should be bridging CAN_P/N
  

• Polygon cutout not needed.
  
  

• Combine this, no need to swiss cheese it.
  

• These vias are floating. and should be removed. The ground pads are already connected in the ground plane. With the vias here, you are effectively asking them to drill an area that has already been drilled.
  

• Bring this via in:
  

• Silkscreen designator clean up required
  

• Remove this small kink in the SPI trace. Otherwise the routing for SPI looks great!
  

• Move this cap down a bit so it is directly in the path of current going into the ATMEGA 5V pin
  

• Bypass cap layout is good, but this would be an example of where you can just use a trace rather than a polygon
  

[Alex-Walsh]

changes have been made from the design review, I need help with some of the things on the checklist though.