From d75ffb1d9dfe54e6621b26d2615b45046a6580d2 Mon Sep 17 00:00:00 2001 From: Quincy Date: Thu, 31 Oct 2024 14:41:00 +0800 Subject: [PATCH] Add support for ARM China Star-MC2. --- pyocd/coresight/component_ids.py | 9 +++++++++ pyocd/coresight/core_ids.py | 2 ++ 2 files changed, 11 insertions(+) diff --git a/pyocd/coresight/component_ids.py b/pyocd/coresight/component_ids.py index 8b8b8284b..0f5823c71 100644 --- a/pyocd/coresight/component_ids.py +++ b/pyocd/coresight/component_ids.py @@ -252,5 +252,14 @@ class CmpInfo(NamedTuple): (ARM_CHINA_ID, CORESIGHT_CLASS, 0x132, 0x00, 0x2a04) : CmpInfo('SCS', 'Star-MC1', CortexM_v8M.factory ), (ARM_CHINA_ID, CORESIGHT_CLASS, 0x132, 0x13, 0x4a13) : CmpInfo('ETM', 'Star-MC1', None ), (ARM_CHINA_ID, CORESIGHT_CLASS, 0x132, 0x11, 0) : CmpInfo('TPIU', 'Star-MC1', TPIU.factory ), + # Designer |Component Class |Part |Type |Archid |Name |Product |Factory + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x31, 0x0a31) : CmpInfo('MTB', 'Star-MC2', None ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x43, 0x1a01) : CmpInfo('ITM', 'Star-MC2', ITM.factory ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x00, 0x1a02) : CmpInfo('DWT', 'Star-MC2', DWTv2.factory ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x00, 0x1a03) : CmpInfo('BPU', 'Star-MC2', FPB.factory ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x14, 0x1a14) : CmpInfo('CTI', 'Star-MC2', None ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x00, 0x2a04) : CmpInfo('SCS', 'Star-MC2', CortexM_v8M.factory ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0xD24, 0x13, 0x4a13) : CmpInfo('ETM', 'Star-MC2', None ), + (ARM_CHINA_ID, CORESIGHT_CLASS, 0x132, 0x11, 0) : CmpInfo('TPIU', 'Star-MC2', TPIU.factory ), } diff --git a/pyocd/coresight/core_ids.py b/pyocd/coresight/core_ids.py index 7398325e6..e3882bf20 100644 --- a/pyocd/coresight/core_ids.py +++ b/pyocd/coresight/core_ids.py @@ -39,6 +39,7 @@ ARM_CortexM55 = 0xD22 ARM_CortexM85 = 0xD23 ARM_China_StarMC1 = 0x132 +ARM_China_StarMC2 = 0xD24 # pylint: enable=invalid_name @@ -58,6 +59,7 @@ (CPUID_ARM, ARM_CortexM55): "Cortex-M55", (CPUID_ARM, ARM_CortexM85): "Cortex-M85", (CPUID_ARM_CHINA, ARM_China_StarMC1): "Star-MC1", + (CPUID_ARM_CHINA, ARM_China_StarMC2): "Star-MC2", } class CoreArchitecture(Enum):