diff --git a/pyocd/coresight/ap.py b/pyocd/coresight/ap.py index b685e6c7a..fbc810e7f 100644 --- a/pyocd/coresight/ap.py +++ b/pyocd/coresight/ap.py @@ -798,7 +798,10 @@ def _init_rom_table_base() -> None: is_adiv5_base = (base & AP_BASE_FORMAT_MASK) != 0 is_base_present = (base & AP_BASE_ENTRY_PRESENT_MASK) != 0 is_legacy_base_present = not is_adiv5_base and not is_base_present - if is_legacy_base_present: + if base == 0xe00fe002: + self.has_rom_table = True + self.rom_addr = 0xe00fe000 + elif is_legacy_base_present: self.has_rom_table = True self.rom_addr = base & AP_BASE_LEGACY_BASEADDR_MASK # clear format and present bits elif (base == AP_BASE_LEGACY_NOTPRESENT) or (not is_base_present): diff --git a/pyocd/debug/svd/data/nrf54l15.svd b/pyocd/debug/svd/data/nrf54l15.svd new file mode 100644 index 000000000..f426c8a76 --- /dev/null +++ b/pyocd/debug/svd/data/nrf54l15.svd @@ -0,0 +1,92803 @@ + + + + Nordic Semiconductor + Nordic + nrf54l15_application + nrf54l + 1 + System-on-chip with a 32-bit Arm Cortex-M33 microcontroller + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 270 + 4 + + system_nrf54l15_application + + 480 + + + + GLOBAL_FICR_NS + Factory Information Configuration Registers + 0x00FFC000 + FICR + + + + 0 + 0x1000 + registers + + FICR + 0x20 + + + INFO + Device info + FICR_INFO + read-write + 0x300 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + HWID + Identification number for the HW + 0 + 15 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + UUID[%s] + Description collection: 128-bit Universally Unique IDentifier (UUID). + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + UUID + Device UUID [n]. + 0 + 31 + + + + + PART + Part code + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + PART + Part code + 0 + 31 + + + N54L15 + nRF54L15 + 0x00054B15 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x020 + read-only + 0xFFFFFFFF + 0x20 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x024 + read-only + 0xFFFFFFFF + 0x20 + + + PACKAGE + Package option + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM size (KB) + 0x028 + read-only + 0xFFFFFFFF + 0x20 + + + RAM + RAM size (KB) + 0 + 31 + + + K256 + 256 kByte RAM + 0x00000100 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RRAM + RRAM size (KB) + 0x02C + read-only + 0xFFFFFFFF + 0x20 + + + RRAM + RRAM size (KB) + 0 + 31 + + + K1524 + 1524 KByte RRAM + 0x000005F4 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Common encryption root key, word n + 0x380 + read-only + 0xFFFFFFFF + 0x20 + + + ER + Encryption Root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Common identity root key, word n + 0x390 + read-only + 0xFFFFFFFF + 0x20 + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x3A0 + read-only + 0xFFFFFFFF + 0x20 + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0x0 + + + Random + Random address + 0x1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x3A4 + read-only + 0xFFFFFFFF + 0x20 + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + 64 + 0x008 + TRIMCNF[%s] + Unspecified + FICR_TRIMCNF + read-write + 0x400 + + ADDR + Description cluster: Address of the register which will be written + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + Address + Address + 0 + 31 + + + + + DATA + Description cluster: Data to be written into the register + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + Data + Data + 0 + 31 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x600 + + TAGHEADER0 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + 0x20 + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + 0x20 + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + XOSC32MTRIM + XOSC32M capacitor selection trim values + 0x620 + read-only + 0xFFFFFFFF + 0x20 + + + SLOPE + Slope trim factor on twos complement form + 0 + 8 + + + OFFSET + Offset trim factor on integer form + 16 + 25 + + + + + XOSC32KTRIM + XOSC32K capacitor selection trim values + 0x624 + read-only + 0xFFFFFFFF + 0x20 + + + SLOPE + Slope trim factor on twos complement form + 0 + 8 + + + OFFSET + Offset trim factor on integer form + 16 + 25 + + + + + + + GLOBAL_UICR_S + User Information Configuration Registers + 0x00FFD000 + UICR + + + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 1 + 0x020 + APPROTECT[%s] + Access Port Protection Registers + UICR_APPROTECT + read-writeonce + 0x000 + + PROTECT0 + Description cluster: Access port protection + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + PROTECT1 + Description cluster: Access port protection + 0x01C + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + + 1 + 0x020 + SECUREAPPROTECT[%s] + Access Port Protection Registers + UICR_SECUREAPPROTECT + read-writeonce + 0x020 + + PROTECT0 + Description cluster: Access port protection + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + PROTECT1 + Description cluster: Access port protection register + 0x01C + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + + 1 + 0x020 + AUXAPPROTECT[%s] + Access Port Protection Registers + UICR_AUXAPPROTECT + read-writeonce + 0x040 + + PROTECT0 + Description cluster: Access port protection + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + PROTECT1 + Description cluster: Access port protection register + 0x01C + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF + + + + + + + + 1 + 0x020 + ERASEPROTECT[%s] + Erase Protection Registers + UICR_ERASEPROTECT + read-writeonce + 0x060 + + PROTECT0 + Description cluster: Erase protection + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + The device can be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF + + + + + + + PROTECT1 + Description cluster: Erase protection + 0x01C + read-writeonce + 0xFFFFFFFF + 0x20 + + + PALL + 0 + 31 + + + Unprotected + The device canbe erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF + + + + + + + + BOOTCONF + Immutable boot region configuration. + 0x080 + read-writeonce + 0xFFFFFFFF + 0x20 + + + READ + Read access + 0 + 0 + + + NotAllowed + Reading from the region is not allowed + 0x0 + + + Allowed + Reading from the region is allowed + 0x1 + + + + + WRITE + Write access + 1 + 1 + + + NotAllowed + Writing to the region is not allowed + 0x0 + + + Allowed + Writing to the region is allowed + 0x1 + + + + + EXECUTE + Execute access + 2 + 2 + + + NotAllowed + Executing code from the region is not allowed + 0x0 + + + Allowed + Executing code from the region is allowed + 0x1 + + + + + SECURE + Secure access + 3 + 3 + + + NonSecure + Both secure and non-secure access to region is allowed + 0x0 + + + Secure + Only secure access to region is allowed + 0x1 + + + + + WRITEONCE + Write-once + 12 + 12 + + + Disabled + Write-once disabled + 0x0 + + + Enabled + Write-once enabled + 0x1 + + + + + LOCK + Enable lock of configuration register + 13 + 13 + + + Disabled + Lock is disabled, and the RRAMC region configuration registers for the + immutable boot region are writable. + 0x0 + + + Enabled + Lock is enabled, and the RRAMC configuration registers for the + immutable boot region are read-only. + 0x1 + + + + + SIZE + Immutable boot region size + 16 + 20 + + + + + USER + Unspecified + UICR_USER + read-writeonce + 0x200 + + ROT + Assets installed to establish initial Root of Trust in the device. + UICR_USER_ROT + read-writeonce + 0x000 + + 4 + 0x02C + PUBKEY[%s] + Unspecified + UICR_USER_ROT_PUBKEY + read-writeonce + 0x000 + + 0x8 + 0x4 + DIGEST[%s] + Description collection: First 256 bits of SHA2-512 digest over RoT public key generation [n]. + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + VALUE + Value for word [o] in the key digest [n]. + 0 + 31 + + + + + 0x3 + 0x4 + REVOKE[%s] + Description collection: Revocation status for RoT public key generation [n]. + 0x020 + read-writeonce + 0xFFFFFFFF + 0x20 + + + STATUS + Revocation status. + 0 + 31 + + + NotRevoked + Key not revoked. + 0xFFFFFFFF + + + + + + + + 4 + 0x02C + AUTHOPKEY[%s] + Unspecified + UICR_USER_ROT_AUTHOPKEY + read-writeonce + 0x0B0 + + 0x8 + 0x4 + DIGEST[%s] + Description collection: First 256 bits of SHA2-512 digest over RoT authenticated operation public key generation [n]. + 0x000 + read-writeonce + 0xFFFFFFFF + 0x20 + + + VALUE + Value for word [o] in the key digest [n]. + 0 + 31 + + + + + 0x3 + 0x4 + REVOKE[%s] + Description collection: Revocation status for RoT authenticated operation public key generation [n]. + 0x020 + read-writeonce + 0xFFFFFFFF + 0x20 + + + STATUS + Revocation status. + 0 + 31 + + + NotRevoked + Key not revoked. + 0xFFFFFFFF + + + + + + + + + + 0x140 + 0x4 + OTP[%s] + Description collection: One time programmable memory + 0x500 + read-writeonce + 0xFFFFFFFF + 0x20 + + + OTP + OTP word + 0 + 31 + + + + + + + GLOBAL_SICR_S + Factory Information Configuration Registers + 0x00FFE000 + SICR + + + + 0 + 0x1000 + registers + + SICR + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + ICACHEDATA_S + CACHEDATA + 0x12F00000 + CACHEDATA + + + + 0 + 0x1000 + registers + + CACHEDATA + 0x20 + + + 128 + 0x040 + SET[%s] + Unspecified + CACHEDATA_SET + read-write + 0x0 + + 2 + 0x020 + WAY[%s] + Unspecified + CACHEDATA_SET_WAY + read-write + 0x0 + + 4 + 0x008 + DU[%s] + Unspecified + CACHEDATA_SET_WAY_DU + read-write + 0x0 + + 0x2 + 0x4 + DATA[%s] + Description collection: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + Data + Data + 0 + 31 + read-only + + + + + + + + + + ICACHEINFO_S + CACHEINFO + 0x12F10000 + CACHEINFO + + + + 0 + 0x1000 + registers + + CACHEINFO + 0x20 + + + 128 + 0x008 + SET[%s] + Unspecified + CACHEINFO_SET + read-write + 0x0 + + 2 + 0x004 + WAY[%s] + Unspecified + CACHEINFO_SET_WAY + read-write + 0x0 + + INFO + Description cluster: Cache information for SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + TAG + Cache tag. + 0 + 23 + read-only + + + DUV_0 + Data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_1 + Data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_2 + Data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_3 + Data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + V + Line valid bit. + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0x0 + + + Valid + Valid cache line + 0x1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0x0 + + + Way1 + Way1 was most recently used + 0x1 + + + + + + + + + + + GLOBAL_CRACENCORE_S + CRACENCORE + 0x51800000 + CRACENCORE + + + + 0 + 0x1000 + registers + + CRACENCORE + 0x20 + + + CRYPTMSTRDMA + Unspecified + CRACENCORE_CRYPTMSTRDMA + read-write + 0x000 + + FETCHADDRLSB + Fetch Address Least Significant Bit + 0x000 + read-write + 0x00000000 + 0x20 + + + FETCHADDRLSB + 0 + 31 + + + + + FETCHADDRMSB + Fetch Address Most Significant Bit + 0x004 + read-write + 0x00000000 + 0x20 + + + FETCHADDRMSB + 0 + 31 + + + + + FETCHLEN + Fetch Length + 0x008 + read-write + 0x00000000 + 0x20 + + + FETCHLEN + 0 + 27 + + + FETCHCSTADDR + 28 + 28 + + + FETCHREALIGN + 29 + 29 + + + FETCHZPADDING + 30 + 30 + + + + + FETCHTAG + Fetch Tag + 0x00C + read-write + 0x00000000 + 0x20 + + + FETCHTAG + 0 + 31 + + + + + PUSHADDRLSB + Push Address Least Significant Bit + 0x010 + read-write + 0x00000000 + 0x20 + + + PUSHADDRLSB + 0 + 31 + + + + + PUSHADDRMSB + Push Address Most Significant Bit + 0x014 + read-write + 0x00000000 + 0x20 + + + PUSHADDRMSB + 0 + 31 + + + + + PUSHLEN + Push Length + 0x018 + read-write + 0x00000000 + 0x20 + + + PUSHLEN + 0 + 27 + + + PUSHCSTADDR + 28 + 28 + + + PUSHREALIGN + 29 + 29 + + + PUSHDISCARD + 30 + 30 + + + + + INTEN + Interrupt Enable + 0x01C + read-write + 0x00000000 + 0x20 + + + INTEN + 0 + 5 + + + + + INTENSET + Interrupt Set + 0x020 + read-write + 0x00000000 + 0x20 + + + INTENSET + 0 + 5 + write-only + + + + + INTENCLR + Interrupt Clear + 0x024 + read-write + 0x00000000 + 0x20 + + + INTENCLR + 0 + 5 + write-only + + + + + INTSTATRAW + Interrupt Status Raw + 0x028 + read-write + 0x00000000 + 0x20 + + + INTSTATRAW + 0 + 31 + read-only + + + + + INTSTAT + Interrupt Status + 0x02C + read-write + 0x00000000 + 0x20 + + + INTSTAT + 0 + 31 + read-only + + + + + INTSTATCLR + Interrupt Status Clear + 0x030 + read-write + 0x00000000 + 0x20 + + + INTSTATCLR + 0 + 31 + write-only + + + + + CONFIG + Configuration + 0x034 + read-write + 0x00000000 + 0x20 + + + FETCHCTRLINDIRECT + 0 + 0 + + + PUSHCTRLINDIRECT + 1 + 1 + + + FETCHSTOP + 2 + 2 + + + PUSHSTOP + 3 + 3 + + + SOFTRST + 4 + 4 + + + + + START + Start + 0x038 + read-write + 0x00000000 + 0x20 + + + STARTFETCH + 0 + 0 + write-only + + + STARTPUSH + 1 + 1 + write-only + + + + + STATUS + Status + 0x03C + read-write + 0x00000000 + 0x20 + + + FETCHBUSY + 0 + 0 + read-only + + + PUSHBUSY + 1 + 1 + read-only + + + FETCHNOTEMPTY + 4 + 4 + read-only + + + PUSHWAITINGFIFO + 5 + 5 + read-only + + + SOFTRSTBUSY + 6 + 6 + read-only + + + PUSHNBDATA + 16 + 31 + read-only + + + + + + CRYPTMSTRHW + Unspecified + CRACENCORE_CRYPTMSTRHW + read-write + 0x400 + + INCLIPSHWCFG + Incuded IPs Hardware configuration + 0x00 + read-write + 0x00000771 + 0x20 + + + BA411AESINCLUDED + Generic g_IncludeAES value. + 0 + 0 + read-only + + + BA415HPAESGCMINCLUDED + Generic g_IncludeAESGCM value. + 1 + 1 + read-only + + + BA416HPAESXTSINCLUDED + Generic g_IncludeAESXTS value. + 2 + 2 + read-only + + + BA412DESINCLUDED + Generic g_IncludeDES value. + 3 + 3 + read-only + + + BA413HASHINCLUDED + Generic g_IncludeHASH value. + 4 + 4 + read-only + + + BA417CHACHAPOLYINCLUDED + Generic g_IncludeChachaPoly value. + 5 + 5 + read-only + + + BA418SHA3INCLUDED + Generic g_IncludeSHA3 value. + 6 + 6 + read-only + + + BA421ZUCINCLUDED + Generic g_IncludeZUC value. + 7 + 7 + read-only + + + BA419SM4INCLUDED + Generic g_IncludeSM4 value. + 8 + 8 + read-only + + + BA414EPPKEINCLUDED + Generic g_IncludePKE value. + 9 + 9 + read-only + + + BA431NDRNGINCLUDED + Generic g_IncludeNDRNG value. + 10 + 10 + read-only + + + BA420HPCHACHAPOLYINCLUDED + Generic g_IncludeHPChachaPoly value. + 11 + 11 + read-only + + + BA423SNOW3GINCLUDED + Generic g_IncludeSnow3G value. + 12 + 12 + read-only + + + BA422KASUMIINCLUDED + Generic g_IncludeKasumi value. + 13 + 13 + read-only + + + + + BA411EAESHWCFG1 + Generic g_AesModesPoss value. + 0x004 + read-write + 0x070301FF + 0x20 + + + BA411EAESHWCFGMODE + Generic g_AesModesPoss value. + 0 + 8 + read-only + + + BA411EAESHWCFGCS + Generic g_CS value. + 16 + 16 + read-only + + + BA411EAESHWCFGMASKING + Generic g_UseMasking value. + 17 + 17 + read-only + + + BA411EAESHWCFGKEYSIZE + Generic g_Keysize value. + 24 + 26 + read-only + + + + + BA411EAESHWCFG2 + Generic g_CtrSize value. + 0x008 + read-write + 0x00000080 + 0x20 + + + BA411EAESHWCFG2 + Generic g_CtrSize value. + 0 + 15 + read-only + + + + + BA413HASHHWCFG + Generic g_Hash value + 0x00C + read-write + 0x0003003F + 0x20 + + + BA413HASHHWCFGMASK + Generic g_HashMaskFunc value. + 0 + 6 + read-only + + + BA413HASHHWCFGPADDING + Generic g_HashPadding value. + 16 + 16 + read-only + + + BA413HASHHWCFGHMAC + Generic g_HMAC_enabled value. + 17 + 17 + read-only + + + BA413HASHHWCFGVERIFYDIGEST + Generic g_HashVerifyDigest value. + 18 + 18 + read-only + + + + + BA418SHA3HWCFG + Generic g_Sha3CtxtEn value. + 0x010 + read-write + 0x00000001 + 0x20 + + + BA418SHA3HWCFG + Generic g_Sha3CtxtEn value. + 0 + 0 + read-only + + + + + BA419SM4HWCFG + Generic g_SM4ModesPoss value. + 0x014 + read-write + 0x000201FF + 0x20 + + + BA419SM4HWCFG + Generic g_SM4ModesPoss value. + 0 + 9 + read-only + + + USEMASKING + Generic g_sm4UseMasking value. + 17 + 17 + read-only + + + + + BA424ARIAHWCFG + Generic g_aria_modePoss value. + 0x018 + read-write + 0x0000017F + 0x20 + + + BA424ARIAHWCFG + Generic g_aria_modePoss value. + 0 + 8 + read-only + + + + + + RNGCONTROL + Unspecified + CRACENCORE_RNGCONTROL + read-write + 0x1000 + + CONTROL + Control register + 0x000 + read-write + 0x00040000 + 0x20 + + + ENABLE + Enable the NDRNG. + 0 + 0 + + + LFSREN + Select between the NDRNG with asynchronous free running oscillators (when 0) and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when 1). + 1 + 1 + + + TESTEN + Select input for conditioning function and continuous tests: + 2 + 2 + + + NORMAL + Noise source (normal mode). + 0x0 + + + TEST + Test data register (test mode). + 0x1 + + + + + CONDBYPASS + Conditioning function bypass. + 3 + 3 + + + NORMAL + the conditioning function is used (normal mode). + 0x0 + + + BYPASS + the conditioning function is bypassed (to observe entropy source directly). + 0x1 + + + + + INTENREP + Interrupt enable for Repetition Count Test failure. + 4 + 4 + + + INTENPROP + Interrupt enable for Adaptive Proportion Test failure (1024-sample window). + 5 + 5 + + + INTENFULL + Interrupt enable for FIFO full. + 7 + 7 + + + SOFTRST + Software reset: + 8 + 8 + + + NORMAL + Normal mode. + 0x0 + + + CTEST + The continuous test, the conditioning function and the FIFO are reset. + 0x1 + + + + + INTENPRE + Interrupt enable for AIS31 preliminary noise alarm. + 9 + 9 + + + INTENALM + Interrupt enable for AIS31 noise alarm. + 10 + 10 + + + FORCEACTIVEROS + Force oscillators to run when FIFO is full. + 11 + 11 + + + HEALTHTESTBYPASS + Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state. + 12 + 12 + + + AIS31BYPASS + Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state. + 13 + 13 + + + HEALTHTESTSEL + Select input to health test module: + 14 + 14 + + + BEFORE + Before conditioning. + 0x0 + + + AFTER + After conditioning. + 0x1 + + + + + AIS31TESTSEL + Select input to the AIS31 test module: + 15 + 15 + + + BEFORE + Before conditioning. + 0x0 + + + AFTER + After conditioning. + 0x1 + + + + + NB128BITBLOCKS + Number of 128 bit blocks used in AES-CBCMAC post-processing. + 16 + 19 + + + FIFOWRITESTARTUP + Enable write of the samples in the FIFO during start-up. + 20 + 20 + + + + + FIFOLEVEL + FIFO level register. + 0x004 + read-write + 0x00000000 + 0x20 + + + FIFOLEVEL + Number of 32 bits words of random available in the FIFO. + 0 + 31 + + + + + FIFOTHRESHOLD + FIFO threshold register. + 0x008 + read-write + 0x00000003 + 0x20 + + + FIFOTHRESHOLD + FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks. + 0 + 2 + + + + + FIFODEPTH + FIFO depth register. + 0x00C + read-write + 0x00000010 + 0x20 + + + FIFODEPTH + Maximum number of 32 bits words that can be stored in the FIFO: 2**g_fifodepth. + 0 + 31 + read-only + + + + + 0x4 + 0x4 + KEY[%s] + Description collection: Key register. + 0x010 + read-write + 0x00000000 + 0x20 + + + KEY + Key register. + 0 + 31 + + + + + TESTDATA + Test data register. + 0x020 + read-write + 0x00000000 + 0x20 + + + TESTDATA + Test data register. + 0 + 31 + write-only + + + + + REPEATTHRESHOLD + Repetition Test Count Cut-Off value. + 0x024 + read-write + 0x00000029 + 0x20 + + + REPEATTHRESHOLD + Repetition Test Count Cut-Off value. + 0 + 5 + + + + + PROPTHRESHOLD + Adaptive Proportion Test (1024-sample window) Cut-Off value. + 0x028 + read-write + 0x00000319 + 0x20 + + + PROPTHRESHOLD + Adaptive Proportion Test (1024-sample window) Cut-Off value. + 0 + 9 + + + + + STATUS + Status register. + 0x030 + read-write + 0x00000000 + 0x20 + + + TESTDATABUSY + High when data written to TestData register is being processed. + 0 + 0 + read-only + + + STATE + State of the control FSM: + 1 + 3 + read-only + + + RESET + Reset + 0x0 + + + STARTUP + Startup + 0x1 + + + IDLERON + Idle (Rings On) + 0x2 + + + IDLEROFF + Idle (Rings Off) + 0x3 + + + FILLFIFO + Fill FIFO + 0x4 + + + ERROR + Error + 0x5 + + + + + REPFAIL + NIST-800-90B repetition Count Test interrupt status. + 4 + 4 + + + PROPFAIL + NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status. + 5 + 5 + + + FULLINT + FIFO full status. + 7 + 7 + + + PREINT + AIS31 preliminary noise alarm interrupt status. + 8 + 8 + + + ALMINT + AIS31 noise alarm interrupt status. + 9 + 9 + + + STARTUPFAIL + Start-up test failure. + 10 + 10 + read-only + + + FIFOACCFAIL + Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0). + 11 + 11 + + + + + INITWAITVAL + Initial wait counter value. + 0x034 + read-write + 0x0000FFFF + 0x20 + + + INITWAITVAL + Number of clock cycles to wait before sampling data from the noise source. + 0 + 15 + + + + + 0x2 + 0x4 + DISABLEOSC[%s] + Description collection: Disable oscillator rings #n*32 to #((n+1)*32)-1. + 0x038 + read-write + 0x00000000 + 0x20 + + + DISABLEOSC + Disable oscillator rings #n*32 to #((n+1)*32)-1. + 0 + 31 + + + + + SWOFFTMRVAL + Switch off timer value. + 0x040 + read-write + 0x0000FFFF + 0x20 + + + SWOFFTMRVAL + Number of clk cycles to wait before stopping the rings after the FIFO is full. + 0 + 15 + + + + + CLKDIV + Sample clock divider. + 0x044 + read-write + 0x00000000 + 0x20 + + + CLKDIV + Sample clock divider. + 0 + 7 + + + + + AIS31CONF0 + AIS31 configuration register 0. + 0x048 + read-write + 0x43401040 + 0x20 + + + STARTUPTHRESHOLD + Start-up test threshold. + 0 + 14 + + + ONLINETHRESHOLD + Online threshold. + 16 + 30 + + + + + AIS31CONF1 + AIS31 configuration register 1. + 0x04C + read-write + 0x03C00680 + 0x20 + + + ONLINEREPTHRESHOLD + Online repeat threshold. + 0 + 14 + + + HEXPECTEDVALUE + Expected history value. + 16 + 30 + + + + + AIS31CONF2 + AIS31 configuration register 2. + 0x050 + read-write + 0x04400340 + 0x20 + + + HMIN + Minimum allowed history value. + 0 + 14 + + + HMAX + Maximum allowed history value. + 16 + 30 + + + + + AIS31STATUS + AIS31 status register. + 0x054 + read-write + 0x00000000 + 0x20 + + + NUMPRELIMALARMS + Number of preliminary noise alarms since counter was last cleared. + 0 + 15 + + + PRELIMNOISEALARMRNG + Last preliminary noise alarm occurred due to history value out of range. + 16 + 16 + + + PRELIMNOISEALARMREP + Last preliminary noise alarm occurred due to consecutive high Χ**2. + 17 + 17 + + + + + HWCONFIG + Hardware configuration register. + 0x058 + read-write + 0x00000337 + 0x20 + + + NUMBOFRINGS + Generic g_NumRings value. + 0 + 7 + read-only + + + AIS31 + Generic g_AIS31 value. + 8 + 8 + read-only + + + AIS31FULL + Generic g_AIS31Full value. + 9 + 9 + read-only + + + + + 0x10 + 0x4 + FIFO[%s] + Description collection: FIFO data + 0x080 + read-only + 0x00000000 + 0x20 + + + DATA + FIFO data + 0 + 31 + + + + + + PK + Unspecified + CRACENCORE_PK + read-write + 0x2000 + + POINTERS + Pointers register. + 0x000 + read-write + 0x00000000 + 0x20 + + + OPPTRA + When executing primitive arithmetic operations, this pointer defines where operand A is located in memory (location 0x0 to 0xF). + 0 + 3 + + + OPPTRB + When executing primitive arithmetic operations, this pointer defines where operand B is located in memory (location 0x0 to 0xF). + 8 + 11 + + + OPPTRC + When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where the result will be stored in memory. + 16 + 19 + + + OPPTRN + When executing primitive arithmetic operations, this pointer defines the location where the modulus is located in memory (location 0x0 to 0xF). + 24 + 27 + + + + + COMMAND + Command register. + 0x004 + read-write + 0x0000000F + 0x20 + + + OPEADDR + This field defines the operation to be performed. + 0 + 6 + + + FIELDF + 0: Field is GF(p) 1: Field is GF(2**m) + 7 + 7 + + + OPBYTESM1 + This field defines the size (= number of bytes minus one) of the operands for the current operation. + 8 + 17 + + + RANDMOD + Enable randomization of modulus (counter-measure). + 19 + 19 + + + SELCURVE + Enable accelerator for specific curve modulus: + 20 + 22 + + + NOACCEL + Unspecified + 0x0 + + + P256 + Unspecified + 0x1 + + + P384 + Unspecified + 0x2 + + + P521 + Unspecified + 0x3 + + + P192 + Unspecified + 0x4 + + + CURVE25519 + Unspecified + 0x5 + + + ED25519 + Unspecified + 0x6 + + + + + RANDKE + Enable randomization of exponent/scalar (counter-measure). + 24 + 24 + + + RANDPROJ + Enable randomization of projective coordinates (counter-measure). + 25 + 25 + + + EDWARDS + Enable Edwards curve. + 26 + 26 + + + SWAPBYTES + Swap the bytes on AHB interface: + 28 + 28 + + + NATIVE + Native format (little endian). + 0x0 + + + SWAPPED + Byte swapped (big endian). + 0x1 + + + + + FLAGA + Flag A. + 29 + 29 + + + FLAGB + Flag B. + 30 + 30 + + + CALCR2 + This bit indicates if the IP has to calculate R**2 mod N for the next operation. + 31 + 31 + + + NRECALCULATE + don't recalculate R² mod N + 0x0 + + + RECALCULATE + re-calculate R² mod N + 0x1 + + + + + + + CONTROL + Command register. + 0x008 + read-write + 0x00000000 + 0x20 + + + START + Writing a 1 starts the processing. + 0 + 0 + write-only + + + CLEARIRQ + Writing a 1 clears the IRQ output. + 1 + 1 + write-only + + + + + STATUS + Status register. + 0x00C + read-write + 0x00000000 + 0x20 + + + ERRORFLAGS + These bits indicate an error condition. + 4 + 15 + read-only + + + PKBUSY + This bit reflects the BUSY output value. + 16 + 16 + read-only + + + INTRPTSTATUS + This bit reflects the IRQ output value. + 17 + 17 + read-only + + + FAILPTR + These bits indicate which data location generated the error flag. + 24 + 28 + read-only + + + + + TIMER + Timer register. + 0x014 + read-write + 0x00000000 + 0x20 + + + TIMER + Number of core clock cycles. + 0 + 31 + + + + + HWCONFIG + Hardware configuration register. + 0x018 + read-write + 0x01F72200 + 0x20 + + + MAXOPSIZE + Maximum operand size (number of bytes). + 0 + 11 + read-only + + + NBMULT + Number of multipliers: + 12 + 15 + read-only + + + MULT1 + 1 multiplier + 0x0 + + + MULT4 + 4 multipliers + 0x1 + + + MULT16 + 16 multipliers + 0x2 + + + MULT64 + 64 multipliers + 0x4 + + + MULT256 + 256 multipliers + 0x8 + + + + + PRIMEFIELD + Support prime field. + 16 + 16 + read-only + + + BINARYFIELD + Support binary field. + 17 + 17 + read-only + + + ECC + Support error correction. + 18 + 18 + read-only + + + P256 + Support ECC P256 acceleration. + 20 + 20 + read-only + + + P384 + Support ECC P384 acceleration. + 21 + 21 + read-only + + + P521 + Support ECC P521 acceleration. + 22 + 22 + read-only + + + P192 + Support ECC P192 acceleration. + 23 + 23 + read-only + + + X25519 + Support Curve25519/Ed25519 acceleration. + 24 + 24 + read-only + + + AHBMASTER + Memory access + 25 + 25 + read-only + + + SLAVE + Memory access through AHB Slave and internally in the PKE. + 0x0 + + + MASTER + Memory access through AHB Master, outside the PKE. + 0x1 + + + + + DISABLESMX + State of DisableSMx input (high when SM2/SM9 operations are disabled). + 29 + 29 + read-only + + + DISABLECLRMEM + State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled). + 30 + 30 + read-only + + + DISABLECM + State of DisableCM input (high when counter-measures are disabled). + 31 + 31 + read-only + + + + + OPSIZE + Operand size register. + 0x01C + read-write + 0x00001000 + 0x20 + + + OPSIZE + Operand size (number of bytes): + This register is used when the memory is accessed via AHB Master + 0 + 12 + + + OPSIZE256 + 256 bytes. + 0x0100 + + + OPSIZE521 + 521 bytes. + 0x0209 + + + OPSIZE2048 + 2048 bytes. + 0x0800 + + + OPSIZE3072 + 3072 bytes. + 0x0C00 + + + OPSIZE4096 + 4096 bytes. + 0x1000 + + + + + + + RAMERRORINJECT + RAM error injection register. + 0x040 + read-write + 0x03FF03FF + 0x20 + + + BITERROR1 + Bit position of first error + 0 + 9 + + + BITERROR2 + Bit position of second error + 16 + 25 + + + + + RAMERRORSTATUS + RAM error status register. + 0x044 + read-write + 0x00000000 + 0x20 + + + RAMCORRECTION + This bit indicates that a 1-bit error has been detected and corrected on RAM interface + 0 + 0 + read-only + + + RAMFAILURE + This bit indicates that an uncorrectable error has been detected on the data RAM interface + 1 + 1 + read-only + + + + + + IKG + Unspecified + CRACENCORE_IKG + read-write + 0x3000 + + START + Start register. + 0x000 + read-write + 0x00000000 + 0x20 + + + START + Start the Isolated Key Generation. + 0 + 0 + write-only + + + + + STATUS + Status register. + 0x004 + read-write + 0x00000000 + 0x20 + + + SEEDERROR + Seed Error during Isolated Key Generation. + 0 + 0 + read-only + + + ENTROPYERROR + Entropy Error during Isolated Key Generation. + 1 + 1 + read-only + + + OKAY + Isolated Key Generation is okay. + 2 + 2 + read-only + + + CTRDRBGBUSY + CTR_DRBG health test is busy (only when g_hw_health_test = true). + 4 + 4 + read-only + + + CATASTROPHICERROR + Catastrophic error during CTR_DRBG health test (only when g_hw_health_test = true). + 5 + 5 + read-only + + + SYMKEYSTORED + Symmetric Keys are stored. + 6 + 6 + read-only + + + PRIVKEYSTORED + Private Keys are stored. + 7 + 7 + read-only + + + + + INITDATA + InitData register. + 0x008 + read-write + 0x00000000 + 0x20 + + + INITDATA + Writing a 1 initialise Nonce and Personalisation_String registers counters, i.e. start writing from the 32 LSB. + 0 + 0 + write-only + + + + + NONCE + Nonce register. + 0x00C + read-write + 0x00000000 + 0x20 + + + NONCE + Nonce (write/read value 32-bit by 32-bit). + 0 + 31 + + + + + PERSONALISATIONSTRING + Personalisation String register. + 0x010 + read-write + 0x00000000 + 0x20 + + + PERSONALISATIONSTRING + Personalisation String (write/read value 32-bit by 32-bit). + 0 + 31 + + + + + RESEEDINTERVALLSB + Reseed Interval LSB register. + 0x014 + read-write + 0x80000000 + 0x20 + + + RESEEDINTERVALLSB + Reseed Interval LSB. + 0 + 31 + + + + + RESEEDINTERVALMSB + Reseed Interval MSB register. + 0x018 + read-write + 0x00000000 + 0x20 + + + RESEEDINTERVALMSB + Reseed Interval MSB. + 0 + 15 + + + + + PKECONTROL + PKE Control register. + 0x01C + read-write + 0x00000000 + 0x20 + + + PKESTART + Start the PKE operation or trigger for Secure mode exit. + 0 + 0 + write-only + + + CLEARIRQ + Clear the IRQ output. + 1 + 1 + write-only + + + + + PKECOMMAND + PKE Command register. + 0x020 + read-write + 0x00000000 + 0x20 + + + SECUREMODE + Secure mode. + 0 + 0 + + + DEACTIVATED + Unspecified + 0x0 + + + ACTIVATED + Unspecified + 0x1 + + + + + SELECTEDKEY + Select Generated Private Key for PKE operation. + 4 + 7 + + + OPSEL + Select PKE operation with Isolated Key + 8 + 9 + + + PUBKEY + Public Key Generation + 0x0 + + + ECDSA + ECDSA Signature + 0x1 + + + PTMUL + Point Multiplication + 0x2 + + + + + + + PKESTATUS + PKE Status register. + 0x024 + read-write + 0x00000000 + 0x20 + + + ERROR + Error because either Private Keys are not stored or the operation is not defined. + 0 + 0 + read-only + + + STARTERROR + Error because a new operation is started while the previous one is still busy. + 1 + 1 + read-only + + + IKGPKBUSY + Busy, set when the operation starts and cleared when the operation is finished. + 16 + 16 + read-only + + + IRQSTATUS + IRQ, set when the operation is finished and cleared when the CPU writes the bit 1 of PKE_Control Register or a new operation is started. + 17 + 17 + read-only + + + ERASEBUSY + The PKE Data RAM is being erased. + 18 + 18 + read-only + + + + + SOFTRST + SoftRst register. + 0x028 + read-write + 0x00000000 + 0x20 + + + SOFTRST + Software reset: + 0 + 0 + + + NORMAL + Normal mode. + 0x0 + + + KEY + The Isolated Key Generation logic and the keys are reset. + 0x1 + + + + + + + HWCONFIG + HwConfig register. + 0x02C + read-write + 0xCC4C8312 + 0x20 + + + NBSYMKEYS + Number of Symmetric Keys generated. + 0 + 3 + read-only + + + NBPRIVKEYS + Number of Private Keys generated. + 4 + 7 + read-only + + + IKGCM + Countermeasures for IKG operations are implemented when 1. + 8 + 8 + read-only + + + HWHEALTHTEST + CTR_DRBG health test is implemented when 1. + 9 + 9 + read-only + + + CURVE + ECC curve for IKG (input). + 10 + 11 + read-only + + + P256 + P256. + 0x0 + + + P384 + P384. + 0x1 + + + P521 + P521. + 0x2 + + + + + DF + Derivation function is implemented in the CTR_DRBG when 1. + 12 + 12 + read-only + + + KEYSIZE + AES Key Size support for the AES Core embedded in the CTR_DRBG. + 13 + 15 + read-only + + + AES128 + supports AES128 + 0x1 + + + AES192 + supports AES192 + 0x2 + + + AES256 + supports AES256 + 0x4 + + + + + ENTROPYINPUTLENGTH + Value of g_entropy_input_length/32. + 16 + 19 + read-only + + + NONCELENGTH + Value of g_nonce_length/32. + 20 + 23 + read-only + + + PERSONALIZATIONSTRINGLENGTH + Value of g_personalization_string_length/32. + 24 + 27 + read-only + + + ADDITIONALINPUTLENGTH + Value of g_additional_input_length/32. + 28 + 31 + read-only + + + + + + + + TPIU_NS + Trace Port Interface Unit + 0xE0040000 + TPIU + + + + 0 + 0x1000 + registers + + TPIU + 0x20 + + + SUPPORTEDPORTSIZES + Each bit location is a single port size that is supported on the device. + 0x000 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates whether the TPIU supports port size of 1-bit. + 0 + 0 + + + NotSupported + Port size 1 is not supported. + 0x0 + + + Supported + Port size 1 is supported. + 0x1 + + + + + PORT_SIZE_2 + Indicates whether the TPIU supports port size of 2-bit. + 1 + 1 + + + NotSupported + Port size 2 is not supported. + 0x0 + + + Supported + Port size 2 is supported. + 0x1 + + + + + PORT_SIZE_3 + Indicates whether the TPIU supports port size of 3-bit. + 2 + 2 + + + NotSupported + Port size 3 is not supported. + 0x0 + + + Supported + Port size 3 is supported. + 0x1 + + + + + PORT_SIZE_4 + Indicates whether the TPIU supports port size of 4-bit. + 3 + 3 + + + NotSupported + Port size 4 is not supported. + 0x0 + + + Supported + Port size 4 is supported. + 0x1 + + + + + PORT_SIZE_5 + Indicates whether the TPIU supports port size of 5-bit. + 4 + 4 + + + NotSupported + Port size 5 is not supported. + 0x0 + + + Supported + Port size 5 is supported. + 0x1 + + + + + PORT_SIZE_6 + Indicates whether the TPIU supports port size of 6-bit. + 5 + 5 + + + NotSupported + Port size 6 is not supported. + 0x0 + + + Supported + Port size 6 is supported. + 0x1 + + + + + PORT_SIZE_7 + Indicates whether the TPIU supports port size of 7-bit. + 6 + 6 + + + NotSupported + Port size 7 is not supported. + 0x0 + + + Supported + Port size 7 is supported. + 0x1 + + + + + PORT_SIZE_8 + Indicates whether the TPIU supports port size of 8-bit. + 7 + 7 + + + NotSupported + Port size 8 is not supported. + 0x0 + + + Supported + Port size 8 is supported. + 0x1 + + + + + PORT_SIZE_9 + Indicates whether the TPIU supports port size of 9-bit. + 8 + 8 + + + NotSupported + Port size 9 is not supported. + 0x0 + + + Supported + Port size 9 is supported. + 0x1 + + + + + PORT_SIZE_10 + Indicates whether the TPIU supports port size of 10-bit. + 9 + 9 + + + NotSupported + Port size 10 is not supported. + 0x0 + + + Supported + Port size 10 is supported. + 0x1 + + + + + PORT_SIZE_11 + Indicates whether the TPIU supports port size of 11-bit. + 10 + 10 + + + NotSupported + Port size 11 is not supported. + 0x0 + + + Supported + Port size 11 is supported. + 0x1 + + + + + PORT_SIZE_12 + Indicates whether the TPIU supports port size of 12-bit. + 11 + 11 + + + NotSupported + Port size 12 is not supported. + 0x0 + + + Supported + Port size 12 is supported. + 0x1 + + + + + PORT_SIZE_13 + Indicates whether the TPIU supports port size of 13-bit. + 12 + 12 + + + NotSupported + Port size 13 is not supported. + 0x0 + + + Supported + Port size 13 is supported. + 0x1 + + + + + PORT_SIZE_14 + Indicates whether the TPIU supports port size of 14-bit. + 13 + 13 + + + NotSupported + Port size 14 is not supported. + 0x0 + + + Supported + Port size 14 is supported. + 0x1 + + + + + PORT_SIZE_15 + Indicates whether the TPIU supports port size of 15-bit. + 14 + 14 + + + NotSupported + Port size 15 is not supported. + 0x0 + + + Supported + Port size 15 is supported. + 0x1 + + + + + PORT_SIZE_16 + Indicates whether the TPIU supports port size of 16-bit. + 15 + 15 + + + NotSupported + Port size 16 is not supported. + 0x0 + + + Supported + Port size 16 is supported. + 0x1 + + + + + PORT_SIZE_17 + Indicates whether the TPIU supports port size of 17-bit. + 16 + 16 + + + NotSupported + Port size 17 is not supported. + 0x0 + + + Supported + Port size 17 is supported. + 0x1 + + + + + PORT_SIZE_18 + Indicates whether the TPIU supports port size of 18-bit. + 17 + 17 + + + NotSupported + Port size 18 is not supported. + 0x0 + + + Supported + Port size 18 is supported. + 0x1 + + + + + PORT_SIZE_19 + Indicates whether the TPIU supports port size of 19-bit. + 18 + 18 + + + NotSupported + Port size 19 is not supported. + 0x0 + + + Supported + Port size 19 is supported. + 0x1 + + + + + PORT_SIZE_20 + Indicates whether the TPIU supports port size of 20-bit. + 19 + 19 + + + NotSupported + Port size 20 is not supported. + 0x0 + + + Supported + Port size 20 is supported. + 0x1 + + + + + PORT_SIZE_21 + Indicates whether the TPIU supports port size of 21-bit. + 20 + 20 + + + NotSupported + Port size 21 is not supported. + 0x0 + + + Supported + Port size 21 is supported. + 0x1 + + + + + PORT_SIZE_22 + Indicates whether the TPIU supports port size of 22-bit. + 21 + 21 + + + NotSupported + Port size 22 is not supported. + 0x0 + + + Supported + Port size 22 is supported. + 0x1 + + + + + PORT_SIZE_23 + Indicates whether the TPIU supports port size of 23-bit. + 22 + 22 + + + NotSupported + Port size 23 is not supported. + 0x0 + + + Supported + Port size 23 is supported. + 0x1 + + + + + PORT_SIZE_24 + Indicates whether the TPIU supports port size of 24-bit. + 23 + 23 + + + NotSupported + Port size 24 is not supported. + 0x0 + + + Supported + Port size 24 is supported. + 0x1 + + + + + PORT_SIZE_25 + Indicates whether the TPIU supports port size of 25-bit. + 24 + 24 + + + NotSupported + Port size 25 is not supported. + 0x0 + + + Supported + Port size 25 is supported. + 0x1 + + + + + PORT_SIZE_26 + Indicates whether the TPIU supports port size of 26-bit. + 25 + 25 + + + NotSupported + Port size 26 is not supported. + 0x0 + + + Supported + Port size 26 is supported. + 0x1 + + + + + PORT_SIZE_27 + Indicates whether the TPIU supports port size of 27-bit. + 26 + 26 + + + NotSupported + Port size 27 is not supported. + 0x0 + + + Supported + Port size 27 is supported. + 0x1 + + + + + PORT_SIZE_28 + Indicates whether the TPIU supports port size of 28-bit. + 27 + 27 + + + NotSupported + Port size 28 is not supported. + 0x0 + + + Supported + Port size 28 is supported. + 0x1 + + + + + PORT_SIZE_29 + Indicates whether the TPIU supports port size of 29-bit. + 28 + 28 + + + NotSupported + Port size 29 is not supported. + 0x0 + + + Supported + Port size 29 is supported. + 0x1 + + + + + PORT_SIZE_30 + Indicates whether the TPIU supports port size of 30-bit. + 29 + 29 + + + NotSupported + Port size 30 is not supported. + 0x0 + + + Supported + Port size 30 is supported. + 0x1 + + + + + PORT_SIZE_31 + Indicates whether the TPIU supports port size of 31-bit. + 30 + 30 + + + NotSupported + Port size 31 is not supported. + 0x0 + + + Supported + Port size 31 is supported. + 0x1 + + + + + PORT_SIZE_32 + Indicates whether the TPIU supports port size of 32-bit. + 31 + 31 + + + NotSupported + Port size 32 is not supported. + 0x0 + + + Supported + Port size 32 is supported. + 0x1 + + + + + + + CURRENTPORTSIZE + Each bit location is a single port size. One bit can be set, and indicates the current port size. + 0x004 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates which port size is currently selected. + 0 + 0 + + + NotSelected + Port size 1 is not selected. + 0x0 + + + Selected + Port size 1 is selected. + 0x1 + + + + + PORT_SIZE_2 + Indicates which port size is currently selected. + 1 + 1 + + + NotSelected + Port size 2 is not selected. + 0x0 + + + Selected + Port size 2 is selected. + 0x1 + + + + + PORT_SIZE_3 + Indicates which port size is currently selected. + 2 + 2 + + + NotSelected + Port size 3 is not selected. + 0x0 + + + Selected + Port size 3 is selected. + 0x1 + + + + + PORT_SIZE_4 + Indicates which port size is currently selected. + 3 + 3 + + + NotSelected + Port size 4 is not selected. + 0x0 + + + Selected + Port size 4 is selected. + 0x1 + + + + + PORT_SIZE_5 + Indicates which port size is currently selected. + 4 + 4 + + + NotSelected + Port size 5 is not selected. + 0x0 + + + Selected + Port size 5 is selected. + 0x1 + + + + + PORT_SIZE_6 + Indicates which port size is currently selected. + 5 + 5 + + + NotSelected + Port size 6 is not selected. + 0x0 + + + Selected + Port size 6 is selected. + 0x1 + + + + + PORT_SIZE_7 + Indicates which port size is currently selected. + 6 + 6 + + + NotSelected + Port size 7 is not selected. + 0x0 + + + Selected + Port size 7 is selected. + 0x1 + + + + + PORT_SIZE_8 + Indicates which port size is currently selected. + 7 + 7 + + + NotSelected + Port size 8 is not selected. + 0x0 + + + Selected + Port size 8 is selected. + 0x1 + + + + + PORT_SIZE_9 + Indicates which port size is currently selected. + 8 + 8 + + + NotSelected + Port size 9 is not selected. + 0x0 + + + Selected + Port size 9 is selected. + 0x1 + + + + + PORT_SIZE_10 + Indicates which port size is currently selected. + 9 + 9 + + + NotSelected + Port size 10 is not selected. + 0x0 + + + Selected + Port size 10 is selected. + 0x1 + + + + + PORT_SIZE_11 + Indicates which port size is currently selected. + 10 + 10 + + + NotSelected + Port size 11 is not selected. + 0x0 + + + Selected + Port size 11 is selected. + 0x1 + + + + + PORT_SIZE_12 + Indicates which port size is currently selected. + 11 + 11 + + + NotSelected + Port size 12 is not selected. + 0x0 + + + Selected + Port size 12 is selected. + 0x1 + + + + + PORT_SIZE_13 + Indicates which port size is currently selected. + 12 + 12 + + + NotSelected + Port size 13 is not selected. + 0x0 + + + Selected + Port size 13 is selected. + 0x1 + + + + + PORT_SIZE_14 + Indicates which port size is currently selected. + 13 + 13 + + + NotSelected + Port size 14 is not selected. + 0x0 + + + Selected + Port size 14 is selected. + 0x1 + + + + + PORT_SIZE_15 + Indicates which port size is currently selected. + 14 + 14 + + + NotSelected + Port size 15 is not selected. + 0x0 + + + Selected + Port size 15 is selected. + 0x1 + + + + + PORT_SIZE_16 + Indicates which port size is currently selected. + 15 + 15 + + + NotSelected + Port size 16 is not selected. + 0x0 + + + Selected + Port size 16 is selected. + 0x1 + + + + + PORT_SIZE_17 + Indicates which port size is currently selected. + 16 + 16 + + + NotSelected + Port size 17 is not selected. + 0x0 + + + Selected + Port size 17 is selected. + 0x1 + + + + + PORT_SIZE_18 + Indicates which port size is currently selected. + 17 + 17 + + + NotSelected + Port size 18 is not selected. + 0x0 + + + Selected + Port size 18 is selected. + 0x1 + + + + + PORT_SIZE_19 + Indicates which port size is currently selected. + 18 + 18 + + + NotSelected + Port size 19 is not selected. + 0x0 + + + Selected + Port size 19 is selected. + 0x1 + + + + + PORT_SIZE_20 + Indicates which port size is currently selected. + 19 + 19 + + + NotSelected + Port size 20 is not selected. + 0x0 + + + Selected + Port size 20 is selected. + 0x1 + + + + + PORT_SIZE_21 + Indicates which port size is currently selected. + 20 + 20 + + + NotSelected + Port size 21 is not selected. + 0x0 + + + Selected + Port size 21 is selected. + 0x1 + + + + + PORT_SIZE_22 + Indicates which port size is currently selected. + 21 + 21 + + + NotSelected + Port size 22 is not selected. + 0x0 + + + Selected + Port size 22 is selected. + 0x1 + + + + + PORT_SIZE_23 + Indicates which port size is currently selected. + 22 + 22 + + + NotSelected + Port size 23 is not selected. + 0x0 + + + Selected + Port size 23 is selected. + 0x1 + + + + + PORT_SIZE_24 + Indicates which port size is currently selected. + 23 + 23 + + + NotSelected + Port size 24 is not selected. + 0x0 + + + Selected + Port size 24 is selected. + 0x1 + + + + + PORT_SIZE_25 + Indicates which port size is currently selected. + 24 + 24 + + + NotSelected + Port size 25 is not selected. + 0x0 + + + Selected + Port size 25 is selected. + 0x1 + + + + + PORT_SIZE_26 + Indicates which port size is currently selected. + 25 + 25 + + + NotSelected + Port size 26 is not selected. + 0x0 + + + Selected + Port size 26 is selected. + 0x1 + + + + + PORT_SIZE_27 + Indicates which port size is currently selected. + 26 + 26 + + + NotSelected + Port size 27 is not selected. + 0x0 + + + Selected + Port size 27 is selected. + 0x1 + + + + + PORT_SIZE_28 + Indicates which port size is currently selected. + 27 + 27 + + + NotSelected + Port size 28 is not selected. + 0x0 + + + Selected + Port size 28 is selected. + 0x1 + + + + + PORT_SIZE_29 + Indicates which port size is currently selected. + 28 + 28 + + + NotSelected + Port size 29 is not selected. + 0x0 + + + Selected + Port size 29 is selected. + 0x1 + + + + + PORT_SIZE_30 + Indicates which port size is currently selected. + 29 + 29 + + + NotSelected + Port size 30 is not selected. + 0x0 + + + Selected + Port size 30 is selected. + 0x1 + + + + + PORT_SIZE_31 + Indicates which port size is currently selected. + 30 + 30 + + + NotSelected + Port size 31 is not selected. + 0x0 + + + Selected + Port size 31 is selected. + 0x1 + + + + + PORT_SIZE_32 + Indicates which port size is currently selected. + 31 + 31 + + + NotSelected + Port size 32 is not selected. + 0x0 + + + Selected + Port size 32 is selected. + 0x1 + + + + + + + SUPPORTEDTRIGGERMODES + The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. + 0x100 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Indicates whether multiplying the trigger counter by 2^(0+1) is supported. + 0 + 0 + + + NotSelected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x1 + + + + + MULT_1 + Indicates whether multiplying the trigger counter by 2^(1+1) is supported. + 1 + 1 + + + NotSelected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x1 + + + + + MULT_2 + Indicates whether multiplying the trigger counter by 2^(2+1) is supported. + 2 + 2 + + + NotSelected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x1 + + + + + MULT_3 + Indicates whether multiplying the trigger counter by 2^(3+1) is supported. + 3 + 3 + + + NotSelected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x1 + + + + + MULT_4 + Indicates whether multiplying the trigger counter by 2^(4+1) is supported. + 4 + 4 + + + NotSelected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x1 + + + + + TCOUNT8 + Indicates whether an 8-bit wide counter register is implemented. + 8 + 8 + + + NotImplemented + An 8-bit wide counter register is implemented. + 0x0 + + + Implemented + An 8-bit wide counter register is implemented. + 0x1 + + + + + TRIGGERED + A trigger has occurred and the counter has reached 0. + 16 + 16 + + + NotOccured + Trigger has not occurred. + 0x0 + + + Occured + Trigger has occurred. + 0x1 + + + + + TRGRUN + A trigger has occurred but the counter is not at 0. + 17 + 17 + + + NotOccured + Either a trigger has not occurred or the counter is at 0. + 0x0 + + + Occured + A trigger has occurred but the counter is not at 0. + 0x1 + + + + + + + TRIGGERCOUNTERVALUE + The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. + 0x104 + read-write + 0x00000000 + 0x20 + + + TrigCount + 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. + 0 + 7 + + + + + TRIGGERMULTIPLIER + The Trigger_multiplier register contains the selectors for the trigger counter multiplier. + 0x108 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Multiply the Trigger Counter by 2^n. + 0 + 0 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_1 + Multiply the Trigger Counter by 2^n. + 1 + 1 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_2 + Multiply the Trigger Counter by 2^n. + 2 + 2 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_3 + Multiply the Trigger Counter by 2^n. + 3 + 3 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_4 + Multiply the Trigger Counter by 2^n. + 4 + 4 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + + + SUPPPORTEDTESTPATTERNMODES + The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. + 0x200 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + + + CURRENTTESTPATTERNMODES + Current_test_pattern_mode indicates the current test pattern or mode selected. + 0x204 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + + + TPRCR + The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. + 0x208 + read-write + 0x00000000 + 0x20 + + + PATTCOUNT + 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. + 0 + 7 + + + + + FFSR + The FFSR register indicates the current status of the formatter and flush features available in the TPIU. + 0x300 + read-write + 0x00000000 + 0x20 + + + FLINPROG + Flush in progress. + 0 + 0 + + + NotInProgress + A flush is not in progress. + 0x0 + + + InProgress + A flush is in progress. + 0x1 + + + + + FTSTOPPED + The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. + 1 + 1 + + + Running + Formatter has not stopped. + 0x0 + + + Stopped + Formatter has stopped. + 0x1 + + + + + TCPRESENT + Indicates whether the TRACECTL pin is available for use. + 2 + 2 + + + NotPresent + TRACECTL pin is not present. + 0x0 + + + Present + TRACECTL pin is present. + 0x1 + + + + + + + FFCR + The FFCR register controls the generation of stop, trigger, and flush events. + 0x304 + read-write + 0x00000000 + 0x20 + + + ENFTC + Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. + 0 + 0 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + ENFCONT + Is embedded in trigger packets and indicates that no cycle is using sync packets. + 1 + 1 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONFLIN + Enables the use of the flushin connection. + 4 + 4 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONTRIG + Initiates a manual flush of data in the system when a trigger event occurs. + 5 + 5 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANR + Generates a flush. This bit is set to 0 when this flush is serviced. + 6 + 6 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANW + Generates a flush. This bit is set to 1 when this flush is serviced. + 7 + 7 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGIN + Indicates a trigger when trigin is asserted. + 8 + 8 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGEVT + Indicates a trigger on a trigger event. + 9 + 9 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGFL + Indicates a trigger when flush completion on afreadys is returned. + 10 + 10 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPFL + Forces the FIFO to drain off any part-completed packets. + 12 + 12 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPTRIG + Stops the formatter after a trigger event is observed. Reset to disabled or 0. + 13 + 13 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + + + FSCR + The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. + 0x308 + read-write + 0x00000000 + 0x20 + + + CYCCOUNT + 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. + 0 + 11 + + + + + EXTCTLINPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. + 0x400 + read-write + 0x00000000 + 0x20 + + + EXTCTLIN_0 + EXTCTL inputs. + 0 + 0 + + + Low + Input EXTCTL0 is low. + 0x0 + + + High + Input EXTCTL0 is high. + 0x1 + + + + + EXTCTLIN_1 + EXTCTL inputs. + 1 + 1 + + + Low + Input EXTCTL1 is low. + 0x0 + + + High + Input EXTCTL1 is high. + 0x1 + + + + + EXTCTLIN_2 + EXTCTL inputs. + 2 + 2 + + + Low + Input EXTCTL2 is low. + 0x0 + + + High + Input EXTCTL2 is high. + 0x1 + + + + + EXTCTLIN_3 + EXTCTL inputs. + 3 + 3 + + + Low + Input EXTCTL3 is low. + 0x0 + + + High + Input EXTCTL3 is high. + 0x1 + + + + + EXTCTLIN_4 + EXTCTL inputs. + 4 + 4 + + + Low + Input EXTCTL4 is low. + 0x0 + + + High + Input EXTCTL4 is high. + 0x1 + + + + + EXTCTLIN_5 + EXTCTL inputs. + 5 + 5 + + + Low + Input EXTCTL5 is low. + 0x0 + + + High + Input EXTCTL5 is high. + 0x1 + + + + + EXTCTLIN_6 + EXTCTL inputs. + 6 + 6 + + + Low + Input EXTCTL6 is low. + 0x0 + + + High + Input EXTCTL6 is high. + 0x1 + + + + + EXTCTLIN_7 + EXTCTL inputs. + 7 + 7 + + + Low + Input EXTCTL7 is low. + 0x0 + + + High + Input EXTCTL7 is high. + 0x1 + + + + + + + EXTCTLOUTPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. + 0x404 + read-write + 0x00000000 + 0x20 + + + EXTCTLOUT_0 + EXTCTL outputs. + 0 + 0 + + + Low + Output EXTCTL0 is low. + 0x0 + + + High + Output EXTCTL0 is high. + 0x1 + + + + + EXTCTLOUT_1 + EXTCTL outputs. + 1 + 1 + + + Low + Output EXTCTL1 is low. + 0x0 + + + High + Output EXTCTL1 is high. + 0x1 + + + + + EXTCTLOUT_2 + EXTCTL outputs. + 2 + 2 + + + Low + Output EXTCTL2 is low. + 0x0 + + + High + Output EXTCTL2 is high. + 0x1 + + + + + EXTCTLOUT_3 + EXTCTL outputs. + 3 + 3 + + + Low + Output EXTCTL3 is low. + 0x0 + + + High + Output EXTCTL3 is high. + 0x1 + + + + + EXTCTLOUT_4 + EXTCTL outputs. + 4 + 4 + + + Low + Output EXTCTL4 is low. + 0x0 + + + High + Output EXTCTL4 is high. + 0x1 + + + + + EXTCTLOUT_5 + EXTCTL outputs. + 5 + 5 + + + Low + Output EXTCTL5 is low. + 0x0 + + + High + Output EXTCTL5 is high. + 0x1 + + + + + EXTCTLOUT_6 + EXTCTL outputs. + 6 + 6 + + + Low + Output EXTCTL6 is low. + 0x0 + + + High + Output EXTCTL6 is high. + 0x1 + + + + + EXTCTLOUT_7 + EXTCTL outputs. + 7 + 7 + + + Low + Output EXTCTL7 is low. + 0x0 + + + High + Output EXTCTL7 is high. + 0x1 + + + + + + + ITTRFLINACK + The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + TRIGINACK + Sets the value of triginack. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHINACK + Sets the value of flushinack. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITTRFLIN + The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. + 0xEE8 + read-write + 0x00000000 + 0x20 + + + TRIGIN + Reads the value of trigin. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHIN + Reads the value of flushin. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBDATA0 + The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + Enables control of the atreadys and afvalids outputs of the TPIU. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + Sets the value of afvalid. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + Sets the value of atready. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATID + Reads the value of atids. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. + To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + Reads the value of atvalids. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + Reads the value of afreadys. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + Reads the value of atbytess. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + MUXNUM + Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. + Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. + 0 + 4 + + + CLKRELAT + Indicates the relationship between atclk and traceclkin. + 5 + 5 + + + Synchronous + atclk and traceclkin are synchronous. + 0x0 + + + ASynchronous + atclk and traceclkin are asynchronous. + 0x1 + + + + + FIFOSIZE + FIFO size in powers of 2. + 6 + 8 + + + Entries4 + FIFO size of 4 entries, that is, 16 bytes. + 0x2 + + + + + TCLKDATA + Indicates whether trace clock plus data is supported. + 9 + 9 + + + Supported + Trace clock and data is supported. + 0x0 + + + NotSupported + Trace clock and data is not supported. + 0x1 + + + + + SWOMAN + Indicates whether Serial Wire Output, Manchester encoded format, is supported. + 10 + 10 + + + NotSupported + Serial Wire Output, Manchester encoded format, is not supported. + 0x0 + + + Supported + Serial Wire Output, Manchester encoded format, is supported. + 0x1 + + + + + SWOUARTNRZ + Indicates whether Serial Wire Output, UART or NRZ, is supported. + 11 + 11 + + + NotSupported + Serial Wire Output, UART or NRZ, is not supported. + 0x0 + + + Supported + Serial Wire Output, UART or NRZ, is supported. + 0x1 + + + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace sink. + 0x1 + + + + + SUB + The sub-type of the component + 4 + 7 + + + TracePort + Indicates that this component is a trace port component. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + ETM_NS + Embedded Trace Macrocell + 0xE0041000 + ETM + + + + 0 + 0x1000 + registers + + ETM + 0x20 + + + TRCPRGCTLR + Enables the trace unit. + 0x004 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCPROCSELR + Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero. + 0x008 + read-write + 0x00000000 + 0x20 + + + PROCSEL + PE select bits that select the PE to trace. + 0 + 4 + + + + + TRCSTATR + Idle status bit + 0x00C + read-write + 0x00000000 + 0x20 + + + IDLE + Trace unit enable bit + 0 + 0 + + + NotIdle + The trace unit is not idle. + 0x0 + + + Idle + The trace unit is idle. + 0x1 + + + + + PMSTABLE + Programmers' model stable bit + 1 + 1 + + + NotStable + The programmers' model is not stable. + 0x0 + + + Stable + The programmers' model is stable. + 0x1 + + + + + + + TRCCONFIGR + Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x010 + read-write + 0x00000000 + 0x20 + + + LOADASP0INST + Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. + 1 + 1 + + + No + Do not trace load instructions as P0 instructions. + 0x0 + + + Yes + Trace load instructions as P0 instructions. + 0x1 + + + + + STOREASP0INST + Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. + 2 + 2 + + + No + Do not trace store instructions as P0 instructions. + 0x0 + + + Yes + Trace store instructions as P0 instructions. + 0x1 + + + + + BB + Branch broadcast mode bit. + 3 + 3 + + + Disabled + Branch broadcast mode is disabled. + 0x0 + + + Enabled + Branch broadcast mode is enabled. + 0x1 + + + + + CCI + Cycle counting instruction trace bit. + 4 + 4 + + + Disabled + Cycle counting in the instruction trace is disabled. + 0x0 + + + Enabled + Cycle counting in the instruction trace is enabled. + 0x1 + + + + + CID + Context ID tracing bit. + 6 + 6 + + + Disabled + Context ID tracing is disabled. + 0x0 + + + Enabled + Context ID tracing is enabled. + 0x1 + + + + + VMID + Virtual context identifier tracing bit. + 7 + 7 + + + Disabled + Virtual context identifier tracing is disabled. + 0x0 + + + Enabled + Virtual context identifier tracing is enabled. + 0x1 + + + + + COND + Conditional instruction tracing bit. + 8 + 10 + + + Disabled + Conditional instruction tracing is disabled. + 0x0 + + + LoadOnly + Conditional load instructions are traced. + 0x1 + + + StoreOnly + Conditional store instructions are traced. + 0x2 + + + LoadAndStore + Conditional load and store instructions are traced. + 0x3 + + + All + All conditional instructions are traced. + 0x7 + + + + + TS + Global timestamp tracing bit. + 11 + 11 + + + Disabled + Global timestamp tracing is disabled. + 0x0 + + + Enabled + Global timestamp tracing is enabled. + 0x1 + + + + + RS + Return stack enable bit. + 12 + 12 + + + Disabled + Return stack is disabled. + 0x0 + + + Enabled + Return stack is enabled. + 0x1 + + + + + QE + Q element enable field. + 13 + 14 + + + Disabled + Q elements are disabled. + 0x0 + + + OnlyWithoutInstCounts + Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. + 0x1 + + + Enabled + Q elements with and without instruction counts are enabled. + 0x3 + + + + + VMIDOPT + Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. + 15 + 15 + + + VTTBR_EL2 + VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context +identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always +zero. If the trace unit supports a Virtual context identifier larger than 8 bits and +if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits +[15:8] of the trace unit Virtual context identifier are always zero. + 0x0 + + + CONTEXTIDR_EL2 + CONTEXTIDR_EL2 is used. + 0x1 + + + + + DA + Data address tracing bit. + 16 + 16 + + + Disabled + Data address tracing is disabled. + 0x0 + + + Enabled + Data address tracing is enabled. + 0x1 + + + + + DV + Data value tracing bit. + 17 + 17 + + + Disabled + Data value tracing is disabled. + 0x0 + + + Enabled + Data value tracing is enabled. + 0x1 + + + + + + + TRCEVENTCTL0R + Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. + 0x20 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate trace elements. + 0 + 7 + + + + + TRCEVENTCTL1R + Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x24 + read-write + 0x00000000 + 0x20 + + + INSTEN_0 + Instruction event enable field. + 0 + 0 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 0, in the instruction trace stream. + 0x1 + + + + + INSTEN_1 + Instruction event enable field. + 1 + 1 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 1, in the instruction trace stream. + 0x1 + + + + + INSTEN_2 + Instruction event enable field. + 2 + 2 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 2, in the instruction trace stream. + 0x1 + + + + + INSTEN_3 + Instruction event enable field. + 3 + 3 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 3, in the instruction trace stream. + 0x1 + + + + + DATAEN + Data event enable bit. + 4 + 4 + + + Disabled + The trace unit does not generate an Event element if event 0 occurs. + 0x0 + + + Enabled + The trace unit generates an Event element in the data trace stream if event 0 occurs. + 0x1 + + + + + ATB + AMBA Trace Bus (ATB) trigger enable bit. + 11 + 11 + + + Disabled + ATB trigger is disabled. + 0x0 + + + Enabled + ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event. + 0x1 + + + + + LPOVERRIDE + Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. + 12 + 12 + + + Disabled + Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state. + 0x0 + + + Enabled + Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation. + 0x1 + + + + + + + TRCSTALLCTLR + Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. + 0x2C + read-write + 0x00000000 + 0x20 + + + LEVEL + Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct. + 0 + 3 + + + Min + Zero invasion. This setting has a greater risk of a FIFO overflow + 0x0 + + + Max + Maximum invasion occurs but there is less risk of a FIFO overflow. + 0xF + + + + + ISTALL + Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL. + 8 + 8 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + DSTALL + Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL. + 9 + 9 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + INSTPRIORITY + Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL. + 10 + 10 + + + Disabled + The trace unit must not prioritize instruction trace. + 0x0 + + + Enabled + The trace unit can prioritize instruction trace. A trace unit might prioritize +instruction trace by preventing output of data trace, or other means which ensure +that the instruction trace has a higher priority than the data trace. + 0x1 + + + + + DATADISCARDLOAD + Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL. + 11 + 11 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data loads. + 0x1 + + + + + DATADISCARDSTORE + Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL. + 12 + 12 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data stores. + 0x1 + + + + + NOOVERFLOW + Trace overflow prevention bit. + 13 + 13 + + + Disabled + Trace overflow prevention is disabled. + 0x0 + + + Enabled + Trace overflow prevention is enabled. This might cause a significant performance impact. + 0x1 + + + + + + + TRCTSCTLR + Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. + 0x30 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate time stamps. + 0 + 7 + + + + + TRCSYNCPR + Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed. + 0x34 + read-write + 0x00000000 + 0x20 + + + PERIOD + Controls how many bytes of trace, the sum of instruction and data, that a trace unit can +generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD + 0 + 4 + + + Disabled + Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request. + 0x00 + + + + + + + TRCCCCTLR + Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1. + 0x38 + read-write + 0x00000000 + 0x20 + + + THRESHOLD + Sets the threshold value for instruction trace cycle counting. + 0 + 11 + + + + + TRCBBCTLR + Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. + 0x3C + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[0] controls the selection of address range comparator pair 0. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_1 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[1] controls the selection of address range comparator pair 1. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_2 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[2] controls the selection of address range comparator pair 2. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_3 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[3] controls the selection of address range comparator pair 3. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_4 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[4] controls the selection of address range comparator pair 4. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_5 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[5] controls the selection of address range comparator pair 5. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_6 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[6] controls the selection of address range comparator pair 6. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_7 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[7] controls the selection of address range comparator pair 7. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + + + TRCTRACEIDR + Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x40 + read-write + 0x00000000 + 0x20 + + + TRACEID + Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. + 0 + 6 + + + + + TRCQCTLR + Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. + 0x44 + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Specifies the address range comparators to be used for controlling Q elements. + 0 + 0 + + + Disabled + Address range comparator 0 is disabled. + 0x0 + + + Enabled + Address range comparator 0 is selected for use. + 0x1 + + + + + RANGE_1 + Specifies the address range comparators to be used for controlling Q elements. + 1 + 1 + + + Disabled + Address range comparator 1 is disabled. + 0x0 + + + Enabled + Address range comparator 1 is selected for use. + 0x1 + + + + + RANGE_2 + Specifies the address range comparators to be used for controlling Q elements. + 2 + 2 + + + Disabled + Address range comparator 2 is disabled. + 0x0 + + + Enabled + Address range comparator 2 is selected for use. + 0x1 + + + + + RANGE_3 + Specifies the address range comparators to be used for controlling Q elements. + 3 + 3 + + + Disabled + Address range comparator 3 is disabled. + 0x0 + + + Enabled + Address range comparator 3 is selected for use. + 0x1 + + + + + RANGE_4 + Specifies the address range comparators to be used for controlling Q elements. + 4 + 4 + + + Disabled + Address range comparator 4 is disabled. + 0x0 + + + Enabled + Address range comparator 4 is selected for use. + 0x1 + + + + + RANGE_5 + Specifies the address range comparators to be used for controlling Q elements. + 5 + 5 + + + Disabled + Address range comparator 5 is disabled. + 0x0 + + + Enabled + Address range comparator 5 is selected for use. + 0x1 + + + + + RANGE_6 + Specifies the address range comparators to be used for controlling Q elements. + 6 + 6 + + + Disabled + Address range comparator 6 is disabled. + 0x0 + + + Enabled + Address range comparator 6 is selected for use. + 0x1 + + + + + RANGE_7 + Specifies the address range comparators to be used for controlling Q elements. + 7 + 7 + + + Disabled + Address range comparator 7 is disabled. + 0x0 + + + Enabled + Address range comparator 7 is selected for use. + 0x1 + + + + + MODE + Selects whether the address range comparators selected by the RANGE field indicate +address ranges where the trace unit is permitted to generate Q elements or address ranges +where the trace unit is not permitted to generate Q elements: + 8 + 8 + + + Exclude + Exclude mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit cannot generate Q elements. If no +ranges are selected, Q elements are permitted across the entire memory map. + 0x0 + + + Include + Include mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit can generate Q elements. If all the +implemented bits in RANGE are set to 0 then Q elements are disabled. + 0x1 + + + + + + + TRCVICTLR + Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic. + 0x080 + read-write + 0x00000000 + 0x20 + + + EVENT_SEL + Select which resource number should be filtered. + 0 + 4 + + + Disabled + This event is not filtered. + 0x00 + + + Enabled + This event is filtered. + 0x01 + + + + + SSSTATUS + When TRCIDR4.NUMACPAIRS &gt; 0 or TRCIDR4.NUMPC &gt; 0, this bit returns the status of the start/stop logic. + 9 + 9 + + + Stopped + The start/stop logic is in the stopped state. + 0x0 + + + Started + The start/stop logic is in the started state. + 0x1 + + + + + TRCRESET + Controls whether a trace unit must trace a Reset exception. + 10 + 10 + + + Disabled + The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. + 0x0 + + + Enabled + The trace unit always traces a Reset exception. + 0x1 + + + + + TRCERR + When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. + 11 + 11 + + + Disabled + The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. + 0x0 + + + Enabled + The trace unit always traces a System error exception, regardless of the value of ViewInst. + 0x1 + + + + + EXLEVEL0_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 16 + 16 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 17 + 17 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 18 + 18 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 19 + 19 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 3. + 0x0 + + + + + EXLEVEL0_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 20 + 20 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 21 + 21 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 22 + 22 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 23 + 23 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 3. + 0x0 + + + + + + + TRCVIIECTLR + ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x084 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst exclude control. + 0x1 + + + + + + + TRCVISSCTLR + Use this to set, or read, the single address comparators that control the ViewInst start/stop +logic. The start/stop logic is active for an instruction which causes a start and remains active +up to and including an instruction which causes a stop, and then the start/stop logic becomes +inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x088 + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 16 + 16 + + + Disabled + The single address comparator 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 17 + 17 + + + Disabled + The single address comparator 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 18 + 18 + + + Disabled + The single address comparator 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 19 + 19 + + + Disabled + The single address comparator 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 20 + 20 + + + Disabled + The single address comparator 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 21 + 21 + + + Disabled + The single address comparator 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 22 + 22 + + + Disabled + The single address comparator 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 23 + 23 + + + Disabled + The single address comparator 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVIPCSSCTLR + Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x08C + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 0 + 0 + + + Disabled + The single PE comparator input 0, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 1 + 1 + + + Disabled + The single PE comparator input 1, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 2 + 2 + + + Disabled + The single PE comparator input 2, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 3 + 3 + + + Disabled + The single PE comparator input 3, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 4 + 4 + + + Disabled + The single PE comparator input 4, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 5 + 5 + + + Disabled + The single PE comparator input 5, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 6 + 6 + + + Disabled + The single PE comparator input 6, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 7 + 7 + + + Disabled + The single PE comparator input 7, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 16 + 16 + + + Disabled + The single PE comparator input 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 17 + 17 + + + Disabled + The single PE comparator input 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 18 + 18 + + + Disabled + The single PE comparator input 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 19 + 19 + + + Disabled + The single PE comparator input 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 20 + 20 + + + Disabled + The single PE comparator input 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 21 + 21 + + + Disabled + The single PE comparator input 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 22 + 22 + + + Disabled + The single PE comparator input 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 23 + 23 + + + Disabled + The single PE comparator input 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVDCTLR + Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. + 0x0A0 + read-write + 0x00000000 + 0x20 + + + EVENT_0 + Event unit enable bit. + 0 + 0 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_1 + Event unit enable bit. + 1 + 1 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_2 + Event unit enable bit. + 2 + 2 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_3 + Event unit enable bit. + 3 + 3 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_4 + Event unit enable bit. + 4 + 4 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_5 + Event unit enable bit. + 5 + 5 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_6 + Event unit enable bit. + 6 + 6 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_7 + Event unit enable bit. + 7 + 7 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + SPREL + Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). + 8 + 9 + + + Enabled + The trace unit does not affect the tracing of SP-relative transfers. + 0x0 + + + DataOnly + The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element. + 0x2 + + + Disabled + The trace unit does not trace the address or value portions of SP-relative transfers. + 0x3 + + + + + PCREL + Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). + 10 + 10 + + + Enabled + The trace unit does not affect the tracing of PC-relative transfers. + 0x0 + + + Disabled + The trace unit does not trace the address or value portions of PC-relative transfers. + 0x1 + + + + + TBI + Controls which information a trace unit populates in bits[63:56] of the data address. + 11 + 11 + + + SignExtend + The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value. + 0x0 + + + Copy + The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. + 0x1 + + + + + TRCEXDATA + Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs. + 12 + 12 + + + Disabled + Exception and exception return data transfers are not traced. + 0x0 + + + Enabled + Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced. + 0x1 + + + + + + + TRCVDSACCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A4 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Selects which single address comparators are in use with ViewData include control. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 0, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Selects which single address comparators are in use with ViewData include control. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 1, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Selects which single address comparators are in use with ViewData include control. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 2, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Selects which single address comparators are in use with ViewData include control. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 3, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Selects which single address comparators are in use with ViewData include control. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 4, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Selects which single address comparators are in use with ViewData include control. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 5, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Selects which single address comparators are in use with ViewData include control. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 6, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Selects which single address comparators are in use with ViewData include control. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 7, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Selects which single address comparators are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The single address comparator 0, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 0, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Selects which single address comparators are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The single address comparator 1, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 1, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Selects which single address comparators are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The single address comparator 2, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 2, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Selects which single address comparators are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The single address comparator 3, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 3, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Selects which single address comparators are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The single address comparator 4, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 4, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Selects which single address comparators are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The single address comparator 5, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 5, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Selects which single address comparators are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The single address comparator 6, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 6, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Selects which single address comparators are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The single address comparator 7, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 7, s selected for ViewData exclude control. + 0x1 + + + + + + + TRCVDARCCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A8 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 0 + 0 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 1 + 1 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 2 + 2 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 3 + 3 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 4 + 4 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 5 + 5 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 6 + 6 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 7 + 7 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, s selected for ViewData exclude control. + 0x1 + + + + + + + 0x3 + 0x4 + TRCSEQEVR[%s] + Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x100 + read-write + 0x00000000 + 0x20 + + + F_0 + Forward field. + 0 + 0 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_1 + Forward field. + 1 + 1 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_2 + Forward field. + 2 + 2 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_3 + Forward field. + 3 + 3 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_4 + Forward field. + 4 + 4 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_5 + Forward field. + 5 + 5 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_6 + Forward field. + 6 + 6 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_7 + Forward field. + 7 + 7 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + B_0 + Backward field. + 8 + 8 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_1 + Backward field. + 9 + 9 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_2 + Backward field. + 10 + 10 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_3 + Backward field. + 11 + 11 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_4 + Backward field. + 12 + 12 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_5 + Backward field. + 13 + 13 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_6 + Backward field. + 14 + 14 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_7 + Backward field. + 15 + 15 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + + + TRCSEQRSTEVR + Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should reset the sequencer. + 0 + 7 + + + + + TRCSEQSTR + Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x11C + read-write + 0x00000000 + 0x20 + + + STATE + Sets or returns the state of the sequencer. + 0 + 1 + + + State0 + The sequencer is in state 0. + 0x0 + + + State1 + The sequencer is in state 1. + 0x1 + + + State2 + The sequencer is in state 2. + 0x2 + + + State3 + The sequencer is in state 3. + 0x3 + + + + + + + TRCEXTINSELR + Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x120 + read-write + 0x00000000 + 0x20 + + + SEL_0 + Each field in this collection selects an external input as a resource for the trace unit. + 0 + 7 + + + SEL_1 + Each field in this collection selects an external input as a resource for the trace unit. + 8 + 15 + + + SEL_2 + Each field in this collection selects an external input as a resource for the trace unit. + 16 + 23 + + + SEL_3 + Each field in this collection selects an external input as a resource for the trace unit. + 24 + 31 + + + + + 0x4 + 0x4 + TRCCNTRLDVR[%s] + Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x140 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n. + 0 + 15 + + + + + 0x4 + 0x4 + TRCCNTCTLR[%s] + Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x150 + read-write + 0x00000000 + 0x20 + + + CNTEVENT + Selects an event, that when it occurs causes counter n to decrement. + 0 + 7 + + + RLDEVENT + Selects an event, that when it occurs causes a reload event for counter n. + 8 + 15 + + + RLDSELF + Controls whether a reload event occurs for counter n, when counter n reaches zero. + 16 + 16 + + + Disabled + The counter is in Normal mode. + 0x0 + + + Enabled + The counter is in Self-reload mode. + 0x1 + + + + + CNTCHAIN + For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. + 17 + 17 + + + Disabled + Counter n does not decrement when a reload event for counter n-1 occurs. + 0x0 + + + Enabled + Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. + 0x1 + + + + + + + 0x4 + 0x4 + TRCCNTVR[%s] + Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle. + 0x160 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the count value of counter n. + 0 + 15 + + + + + 0x1E + 0x4 + TRCRSCTLR[%s] + Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE +behavior of the resource selector occurs, so the resource selector might fire +unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + 0x200 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCSSCCR0 + Controls the single-shot comparator. + 0x280 + read-write + 0x00000000 + 0x20 + + + RST + Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected + 24 + 24 + + + Disabled + Multiple matches can not be detected. + 0x0 + + + Enabled + Multiple matches can occur. + 0x1 + + + + + + + TRCSSCSR0 + Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. + 0x2A0 + read-write + 0x00000000 + 0x20 + + + INST + Instruction address comparator support + 0 + 0 + + + False + Single-shot instruction address comparisons not supported. + 0x0 + + + True + Single-shot instruction address comparisons supported. + 0x1 + + + + + DA + Data address comparator support + 1 + 1 + + + False + Data address comparisons not supported. + 0x0 + + + True + Data address comparisons supported. + 0x1 + + + + + DV + Data value comparator support + 2 + 2 + + + False + Data value comparisons not supported. + 0x0 + + + True + Data value comparisons supported. + 0x1 + + + + + PC + Process counter value comparator support + 3 + 3 + + + False + Process counter value comparisons not supported. + 0x0 + + + True + Process counter value comparisons supported. + 0x1 + + + + + STATUS + Single-shot status. This indicates whether any of the selected comparators have matched. + 31 + 31 + + + NoMatch + Match has not occurred. + 0x0 + + + Match + Match has occurred at least once. + 0x1 + + + + + + + TRCSSPCICR0 + Selects the processor comparator inputs for Single-shot control. + 0x2C0 + read-write + 0x00000000 + 0x20 + + + PC_0 + Selects processor comparator 0 inputs for Single-shot control + 0 + 0 + + + Disabled + Processor comparator 0 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 0 is selected for Single-shot control. + 0x1 + + + + + PC_1 + Selects processor comparator 1 inputs for Single-shot control + 1 + 1 + + + Disabled + Processor comparator 1 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 1 is selected for Single-shot control. + 0x1 + + + + + PC_2 + Selects processor comparator 2 inputs for Single-shot control + 2 + 2 + + + Disabled + Processor comparator 2 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 2 is selected for Single-shot control. + 0x1 + + + + + PC_3 + Selects processor comparator 3 inputs for Single-shot control + 3 + 3 + + + Disabled + Processor comparator 3 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 3 is selected for Single-shot control. + 0x1 + + + + + + + TRCPDCR + Controls the single-shot comparator. + 0x310 + read-write + 0x00000000 + 0x20 + + + PU + Power up request, to request that power to ETM and access to the trace registers is maintained. + 24 + 24 + + + Disabled + Power not requested. + 0x0 + + + Enabled + Power requested. + 0x1 + + + + + + + TRCPDSR + Indicates the power down status of the ETM. + 0x314 + read-write + 0x00000000 + 0x20 + + + POWER + Indicates ETM is powered up + 0 + 0 + + + NotPoweredUp + ETM is not powered up. All registers are not accessible. + 0x0 + + + PoweredUp + ETM is powered up. All registers are accessible. + 0x1 + + + + + STICKYPD + Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR + 1 + 1 + + + NotPoweredDown + Trace register power has not been removed since the TRCPDSR was last read. + 0x0 + + + PoweredDown + Trace register power has been removed since the TRCPDSR was last read. + 0x1 + + + + + + + TRCITATBIDR + Sets the state of output pins. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + ID_0 + Drives the ATIDMI[0] output pin. + 0 + 0 + + + ID_1 + Drives the ATIDMI[1] output pin. + 1 + 1 + + + ID_2 + Drives the ATIDMI[2] output pin. + 2 + 2 + + + ID_3 + Drives the ATIDMI[3] output pin. + 3 + 3 + + + ID_4 + Drives the ATIDMI[4] output pin. + 4 + 4 + + + ID_5 + Drives the ATIDMI[5] output pin. + 5 + 5 + + + ID_6 + Drives the ATIDMI[6] output pin. + 6 + 6 + + + + + TRCITIATBINR + Reads the state of the input pins. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALID + Returns the value of the ATVALIDMI input pin. + 0 + 0 + + + AFREADY + Returns the value of the AFREADYMI input pin. + 1 + 1 + + + + + TRCITIATBOUTR + Sets the state of the output pins. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALID + Drives the ATVALIDMI output pin. + 0 + 0 + + + AFREADY + Drives the AFREADYMI output pin. + 1 + 1 + + + + + TRCITCTRL + Enables topology detection or integration testing, by putting ETM-M33 into integration mode. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration mode enable + 0 + 0 + + + Disabled + ETM is not in integration mode. + 0x0 + + + Enabled + ETM is in integration mode. + 0x1 + + + + + + + TRCCLAIMSET + Sets bits in the claim tag and determines the number of claim tag bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + SET_0 + Claim tag set register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Claim + Set claim tag 0. + 0x1 + + + + + SET_1 + Claim tag set register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Claim + Set claim tag 1. + 0x1 + + + + + SET_2 + Claim tag set register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Claim + Set claim tag 2. + 0x1 + + + + + SET_3 + Claim tag set register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Claim + Set claim tag 3. + 0x1 + + + + + + + TRCCLAIMCLR + Clears bits in the claim tag and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + CLR_0 + Claim tag clear register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Clear + Clear claim tag 0. + 0x1 + + + + + CLR_1 + Claim tag clear register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Clear + Clear claim tag 1. + 0x1 + + + + + CLR_2 + Claim tag clear register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Clear + Clear claim tag 2. + 0x1 + + + + + CLR_3 + Claim tag clear register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Clear + Clear claim tag 3. + 0x1 + + + + + + + TRCAUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + TRCDEVARCH + The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component + 0xFBC + read-only + 0x00000000 + 0x20 + + + ARCHID + Architecture ID + 0 + 15 + + + ETMv42 + Component is an ETMv4 component + 0x4A13 + + + + + REVISION + Architecture revision + 16 + 19 + + + v2 + Component is part of architecture 4.2 + 0x2 + + + + + PRESENT + This register is implemented + 20 + 20 + + + Absent + The register is not implemented. + 0x0 + + + Present + The register is implemented. + 0x1 + + + + + ARCHITECT + Defines the architect of the component + 21 + 31 + + + Arm + This peripheral was architected by Arm. + 0x23B + + + + + + + TRCDEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + ProcessorTrace + Peripheral is a processor trace source. + 0x1 + + + + + + + 0x8 + 0x4 + TRCPIDR[%s] + Description collection: Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + 0x4 + 0x4 + TRCCIDR[%s] + Description collection: Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + + + CPUC_S + CPU control + 0xE0080000 + CPUC + + + + 0 + 0x1000 + registers + + CPUC + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + FPUIOC + Enable or disable interrupt for event FPUIOC + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FPUDZC + Enable or disable interrupt for event FPUDZC + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FPUOFC + Enable or disable interrupt for event FPUOFC + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FPUUFC + Enable or disable interrupt for event FPUUFC + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FPUIXC + Enable or disable interrupt for event FPUIXC + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FPUIDC + Enable or disable interrupt for event FPUIDC + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + FPUIOC + Write '1' to enable interrupt for event FPUIOC + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FPUDZC + Write '1' to enable interrupt for event FPUDZC + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FPUOFC + Write '1' to enable interrupt for event FPUOFC + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FPUUFC + Write '1' to enable interrupt for event FPUUFC + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FPUIXC + Write '1' to enable interrupt for event FPUIXC + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FPUIDC + Write '1' to enable interrupt for event FPUIDC + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + FPUIOC + Write '1' to disable interrupt for event FPUIOC + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FPUDZC + Write '1' to disable interrupt for event FPUDZC + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FPUOFC + Write '1' to disable interrupt for event FPUOFC + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FPUUFC + Write '1' to disable interrupt for event FPUUFC + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FPUIXC + Write '1' to disable interrupt for event FPUIXC + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FPUIDC + Write '1' to disable interrupt for event FPUIDC + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + LOCK + Register to lock the certain parts of the CPU from being modified. + 0x500 + read-write + 0x00000000 + 0x20 + + + LOCKVTORAIRCRS + Locks both the Vector table Offset Register (VTOR) and + Application Interrupt and Reset Control Register (AIRCR) for secure mode. + 0 + 0 + + + NotLocked + Both VTOR and AIRCR can be changed. + 0x0 + + + Locked + Prevents changes to both VTOR and AIRCR. + 0x1 + + + + + LOCKVTORNS + Locks the Vector table Offset Register (VTOR) for non-secure mode. + 1 + 1 + + + NotLocked + VTOR can be changed. + 0x0 + + + Locked + Prevents changes to VTOR. + 0x1 + + + + + LOCKMPUS + Locks the Memory Protection Unit (MPU) for secure mode. + 2 + 2 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKMPUNS + Locks the Memory Protection Unit (MPU) for non secure mode. + 3 + 3 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKSAU + Locks the Security Attribution Unit (SAU) + 4 + 4 + + + NotLocked + SAU registers can be changed. + 0x0 + + + Locked + Prevents changes to SAU registers. + 0x1 + + + + + + + CPUID + The identifier for the CPU in this subsystem. + 0x504 + read-only + 0x00000000 + 0x20 + + + CPUID + The CPU identifier. + 0 + 31 + + + + + + + ICACHE_S + Cache + 0xE0082000 + CACHE + + + + 0 + 0x1000 + registers + + CACHE + 0x20 + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_INVALIDATELINE + Invalidate the line. + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_INVALIDATELINE + Invalidate the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_ERASE + Erase the cache. + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_ERASE + Erase the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STATUS + Status of the cache activities. + 0x400 + read-only + 0x00000000 + 0x20 + + + READY + Ready status. + 0 + 0 + + + Ready + Activity is done and ready for the next activity. + 0x0 + + + Busy + Activity is in progress. + 0x1 + + + + + + + ENABLE + Enable cache. + 0x404 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable cache + 0 + 0 + + + Disabled + Disable cache + 0x0 + + + Enabled + Enable cache + 0x1 + + + + + + + MODE + Cache mode. + 0x408 + read-write + 0x00000000 + 0x20 + + + MODE + Cache mode + 0 + 0 + + + Cache + Cache mode + 0x0 + + + Ram + RAM mode + 0x1 + + + + + RAMSIZE + RAM size + 4 + 5 + + + All + All RAM is used for cache memory + 0x0 + + + Half + Half of the RAM is used for cache memory + 0x1 + + + Quarter + Quarter of the RAM is used for cache memory + 0x2 + + + None + None of the RAM is used for cache memory + 0x3 + + + + + + + LINEADDR + Memory address covered by the line to be maintained. + 0x410 + read-write + 0x00000000 + 0x20 + + + ADDR + Address. + 0 + 31 + + + + + PROFILING + Unspecified + CACHE_PROFILING + read-write + 0x414 + + ENABLE + Enable the profiling counters. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable the profiling counters + 0 + 0 + + + Disable + Disable profiling + 0x0 + + + Enable + Enable profiling + 0x1 + + + + + + + CLEAR + Clear the profiling counters. + 0x004 + write-only + 0x00000000 + 0x20 + + + CLEAR + Clearing the profiling counters + 0 + 0 + + + Clear + Clear the profiling counters + 0x1 + + + + + + + HIT + The cache hit counter for cache region. + 0x008 + read-only + 0x00000000 + 0x20 + + + HITS + Number of cache hits + 0 + 31 + + + + + MISS + The cache miss counter for cache region. + 0x00C + read-only + 0x00000000 + 0x20 + + + MISSES + Number of cache misses + 0 + 31 + + + + + LMISS + The cache line miss counter for cache region. + 0x010 + read-only + 0x00000000 + 0x20 + + + LMISSES + Number of cache line misses + 0 + 31 + + + + + READS + Number of reads for cache region. + 0x014 + read-only + 0x00000000 + 0x20 + + + READS + Number of reads for cache region. + 0 + 31 + + + + + WRITES + Number of writes for cache region. + 0x018 + read-only + 0x00000000 + 0x20 + + + WRITES + Number of writes for cache region. + 0 + 31 + + + + + + DEBUGLOCK + Lock debug mode. + 0x430 + read-writeonce + 0x00000000 + 0x20 + + + DEBUGLOCK + Lock debug mode + 0 + 0 + + + Unlocked + Debug mode unlocked + 0x0 + + + Locked + Debug mode locked. Ignores any other value written. + 0x1 + + + + + + + WRITELOCK + Lock cache updates. + 0x434 + read-write + 0x00000000 + 0x20 + + + WRITELOCK + Lock cache updates + 0 + 0 + + + Unlocked + Cache updates unlocked + 0x0 + + + Locked + Cache updates locked + 0x1 + + + + + + + + + SWI00_S + Software interrupt 0 + 0x5001C000 + SWI + + + + 0 + 0x1000 + registers + + + SWI00 + 28 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + SWI01_S + Software interrupt 1 + 0x5001D000 + + + + SWI01 + 29 + + + + SWI02_S + Software interrupt 2 + 0x5001E000 + + + + SWI02 + 30 + + + + SWI03_S + Software interrupt 3 + 0x5001F000 + + + + SWI03 + 31 + + + + GLOBAL_SPU00_S + System protection unit 0 + 0x50040000 + SPU + + + + 0 + 0x1000 + registers + + + SPU00 + 64 + + SPU + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + PERIPHACCERR + Read pending status of interrupt for event PERIPHACCERR + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + PERIPHACCERR + Unspecified + SPU_PERIPHACCERR + read-write + 0x404 + + ADDRESS + Address of the transaction that caused first error. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Address + 0 + 15 + + + + + + 64 + 0x004 + PERIPH[%s] + Unspecified + SPU_PERIPH + read-write + 0x500 + + PERM + Description cluster: Get and set the applicable access permissions for the peripheral slave index n + 0x000 + read-write + 0x8000000A + 0x20 + + + SECUREMAPPING + Read capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0x0 + + + Secure + This peripheral is always accessible as a secure peripheral + 0x1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPH[n].PERM register + 0x2 + + + Split + This peripheral implements the split security mechanism. + 0x3 + + + + + DMA + Read the peripheral DMA capabilities + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0x0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 0x1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 0x2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + LOCK + Register lock + 8 + 8 + oneToSet + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can not be changed until the next reset + 0x1 + + + + + PRESENT + Indicates if a peripheral is present with peripheral slave index n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0x0 + + + IsPresent + Peripheral is present + 0x1 + + + + + + + + FEATURE + Unspecified + SPU_FEATURE + read-write + 0x600 + + DPPIC + Unspecified + SPU_FEATURE_DPPIC + read-write + 0x080 + + 0x18 + 0x4 + CH[%s] + Description collection: Configuration of features for channel n of DPPIC + 0x000 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + 0x8 + 0x4 + CHG[%s] + Description collection: Configuration of features for channel group n of DPPIC + 0x060 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + + 2 + 0x040 + GPIOTE[%s] + Unspecified + SPU_FEATURE_GPIOTE + read-write + 0x100 + + 0x8 + 0x4 + CH[%s] + Description collection: Configuration of features for channel o of GPIOTE[n] + 0x000 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + 0x8 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt o of GPIOTE[n] + 0x020 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + + 3 + 0x080 + GPIO[%s] + Unspecified + GPIO + read-write + 0x200 + + 0x20 + 0x4 + PIN[%s] + Description collection: Configuration of features for GPIO[n] PIN[o] + 0x000 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + + CRACEN + Unspecified + CRACEN + GPIO[%s] + read-write + 0x200 + + SEED + Configuration for CRACEN SEED + 0x180 + read-write + 0x00020010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + + GRTC + Unspecified + SPU_FEATURE_GRTC + read-write + 0x700 + + 0x18 + 0x4 + CC[%s] + Description collection: Configuration of features for CC n of GRTC + 0x000 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + PWMCONFIG + Configuration of feature for PWMCONFIG of GRTC + 0x074 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + CLK + Configuration of features for CLKOUT/CLKCFG of GRTC + 0x078 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + SYSCOUNTER + Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC + 0x07C + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + 0x10 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt n of GRTC + 0x080 + read-write + 0x00100010 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + + + + + + + GLOBAL_MPC00_S + Memory Privilege Controller + 0x50041000 + MPC + + + + 0 + 0x1000 + registers + + + MPC00 + 65 + + MPC + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Enable or disable interrupt for event MEMACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to enable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to disable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MEMACCERR + Memory Access Error status registers + MPC_MEMACCERR + read-write + 0x400 + + ADDRESS + Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is active. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Target address for erroneous access + 0 + 31 + + + + + INFO + Access information for the transaction that triggered a memory access error. Register content won't be changed as long as MEMACCERR event is active. + 0x004 + read-only + 0x00000000 + 0x20 + + + OWNERID + Owner identifier of the erroneous access + 0 + 3 + + + MASTERPORT + Master port where erroneous access is detected + 4 + 8 + + + READ + Read bit of bus access + 12 + 12 + + + Set + Read access bit was set + 0x1 + + + NotSet + Read access bit was not set + 0x0 + + + + + WRITE + Write bit of bus access + 13 + 13 + + + Set + Write access bit was set + 0x1 + + + NotSet + Write access bit was not set + 0x0 + + + + + EXECUTE + Execute bit of bus access + 14 + 14 + + + Set + Execute access bit was set + 0x1 + + + NotSet + Execute access bit was not set + 0x0 + + + + + SECURE + Secure bit of bus access + 15 + 15 + + + Set + Secure access bit was set + 0x1 + + + NotSet + Secure access bit was not set + 0x0 + + + + + ERRORSOURCE + Source of memory access error + 16 + 16 + + + MPC + Error was triggered by MPC module + 0x1 + + + Slave + Error was triggered by an AXI slave + 0x0 + + + + + + + + GLOBALSLAVE + Global slave master port connection information + MPC_GLOBALSLAVE + read-write + 0x410 + + MASTERPORT + Global slave connection information for master port + 0x000 + read-write + 0x00000000 + 0x20 + + + CONNECTION_0 + Global slave connection information for master port + 0 + 0 + + + Disabled + Master port 0 connection to global slave is disabled + 0x0 + + + Enabled + Master port 0 connection to global slave is enabled + 0x1 + + + + + CONNECTION_1 + Global slave connection information for master port + 1 + 1 + + + Disabled + Master port 1 connection to global slave is disabled + 0x0 + + + Enabled + Master port 1 connection to global slave is enabled + 0x1 + + + + + CONNECTION_2 + Global slave connection information for master port + 2 + 2 + + + Disabled + Master port 2 connection to global slave is disabled + 0x0 + + + Enabled + Master port 2 connection to global slave is enabled + 0x1 + + + + + CONNECTION_3 + Global slave connection information for master port + 3 + 3 + + + Disabled + Master port 3 connection to global slave is disabled + 0x0 + + + Enabled + Master port 3 connection to global slave is enabled + 0x1 + + + + + CONNECTION_4 + Global slave connection information for master port + 4 + 4 + + + Disabled + Master port 4 connection to global slave is disabled + 0x0 + + + Enabled + Master port 4 connection to global slave is enabled + 0x1 + + + + + CONNECTION_5 + Global slave connection information for master port + 5 + 5 + + + Disabled + Master port 5 connection to global slave is disabled + 0x0 + + + Enabled + Master port 5 connection to global slave is enabled + 0x1 + + + + + CONNECTION_6 + Global slave connection information for master port + 6 + 6 + + + Disabled + Master port 6 connection to global slave is disabled + 0x0 + + + Enabled + Master port 6 connection to global slave is enabled + 0x1 + + + + + CONNECTION_7 + Global slave connection information for master port + 7 + 7 + + + Disabled + Master port 7 connection to global slave is disabled + 0x0 + + + Enabled + Master port 7 connection to global slave is enabled + 0x1 + + + + + CONNECTION_8 + Global slave connection information for master port + 8 + 8 + + + Disabled + Master port 8 connection to global slave is disabled + 0x0 + + + Enabled + Master port 8 connection to global slave is enabled + 0x1 + + + + + CONNECTION_9 + Global slave connection information for master port + 9 + 9 + + + Disabled + Master port 9 connection to global slave is disabled + 0x0 + + + Enabled + Master port 9 connection to global slave is enabled + 0x1 + + + + + CONNECTION_10 + Global slave connection information for master port + 10 + 10 + + + Disabled + Master port 10 connection to global slave is disabled + 0x0 + + + Enabled + Master port 10 connection to global slave is enabled + 0x1 + + + + + CONNECTION_11 + Global slave connection information for master port + 11 + 11 + + + Disabled + Master port 11 connection to global slave is disabled + 0x0 + + + Enabled + Master port 11 connection to global slave is enabled + 0x1 + + + + + CONNECTION_12 + Global slave connection information for master port + 12 + 12 + + + Disabled + Master port 12 connection to global slave is disabled + 0x0 + + + Enabled + Master port 12 connection to global slave is enabled + 0x1 + + + + + CONNECTION_13 + Global slave connection information for master port + 13 + 13 + + + Disabled + Master port 13 connection to global slave is disabled + 0x0 + + + Enabled + Master port 13 connection to global slave is enabled + 0x1 + + + + + CONNECTION_14 + Global slave connection information for master port + 14 + 14 + + + Disabled + Master port 14 connection to global slave is disabled + 0x0 + + + Enabled + Master port 14 connection to global slave is enabled + 0x1 + + + + + + + LOCK + Lock global slave registers + 0x004 + read-write + 0x00000000 + 0x20 + + + LOCK + Enable lock + 0 + 0 + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + + + + 8 + 0x010 + REGION[%s] + Memory region to slave decoding table + MPC_REGION + read-write + 0x600 + + CONFIG + Description cluster: Slave region n Configuration register + 0x000 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Locks the region n setting + 8 + 8 + read-writeonce + + + Unlocked + Region n settings can be updated + 0x0 + + + Locked + Region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Region n enable + 9 + 9 + + + Disabled + Region n is not used + 0x0 + + + Enabled + Region n is used + 0x1 + + + + + READ + Read access + 12 + 12 + + + NotAllowed + Read access to region n is not allowed + 0x0 + + + Allowed + Read access to region n is allowed + 0x1 + + + + + WRITE + Write access + 13 + 13 + + + NotAllowed + Write access to region n is not allowed + 0x0 + + + Allowed + Write access to region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 14 + 14 + + + NotAllowed + Software execution from region n is not allowed + 0x0 + + + Allowed + Software execution from region n is allowed + 0x1 + + + + + SECATTR + Memory security mapping + 15 + 15 + + + Secure + Memory is mapped in secure memory address space + 0x1 + + + NonSecure + Memory is mapped in non-secure memory address space + 0x0 + + + + + OWNERID + Region owner identifier. + 16 + 19 + + + + + STARTADDR + Description cluster: Region n start address + 0x004 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for memory region n + 0 + 31 + + + + + ADDRMASK + Description cluster: Select which bits of the incoming address are compared against the STARTADDR + 0x008 + read-write + 0x00000000 + 0x20 + + + ADDRMASK + Address mask for memory region n + 0 + 31 + + + + + MASTERPORT + Description cluster: Region n local master enable + 0x00C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable region n for master port 0 + 0 + 0 + + + Disable + Region n is disabled for master port 0 + 0x0 + + + Enable + Region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable region n for master port 1 + 1 + 1 + + + Disable + Region n is disabled for master port 1 + 0x0 + + + Enable + Region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable region n for master port 2 + 2 + 2 + + + Disable + Region n is disabled for master port 2 + 0x0 + + + Enable + Region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable region n for master port 3 + 3 + 3 + + + Disable + Region n is disabled for master port 3 + 0x0 + + + Enable + Region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable region n for master port 4 + 4 + 4 + + + Disable + Region n is disabled for master port 4 + 0x0 + + + Enable + Region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable region n for master port 5 + 5 + 5 + + + Disable + Region n is disabled for master port 5 + 0x0 + + + Enable + Region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable region n for master port 6 + 6 + 6 + + + Disable + Region n is disabled for master port 6 + 0x0 + + + Enable + Region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable region n for master port 7 + 7 + 7 + + + Disable + Region n is disabled for master port 7 + 0x0 + + + Enable + Region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable region n for master port 8 + 8 + 8 + + + Disable + Region n is disabled for master port 8 + 0x0 + + + Enable + Region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable region n for master port 9 + 9 + 9 + + + Disable + Region n is disabled for master port 9 + 0x0 + + + Enable + Region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable region n for master port 10 + 10 + 10 + + + Disable + Region n is disabled for master port 10 + 0x0 + + + Enable + Region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable region n for master port 11 + 11 + 11 + + + Disable + Region n is disabled for master port 11 + 0x0 + + + Enable + Region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable region n for master port 12 + 12 + 12 + + + Disable + Region n is disabled for master port 12 + 0x0 + + + Enable + Region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable region n for master port 13 + 13 + 13 + + + Disable + Region n is disabled for master port 13 + 0x0 + + + Enable + Region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable region n for master port 14 + 14 + 14 + + + Disable + Region n is disabled for master port 14 + 0x0 + + + Enable + Region n is enabled for master port 14 + 0x1 + + + + + + + + 7 + 0x020 + OVERRIDE[%s] + Special privilege tables + MPC_OVERRIDE + read-write + 0x800 + + CONFIG + Description cluster: Override region n Configuration register + 0x0 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for override region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Lock Override region n + 8 + 8 + read-writeonce + + + Unlocked + Override region n settings can be updated + 0x0 + + + Locked + Override region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Enable Override region n + 9 + 9 + + + Disabled + Override region n is not used + 0x0 + + + Enabled + Override region n is used + 0x1 + + + + + SECUREMASK + Secure mask enable for Override region n + 12 + 12 + read-only + + + Disabled + Mask is disabled for override region n + 0x0 + + + Enabled + Mask is enabled for override region n + 0x1 + + + + + + + STARTADDR + Description cluster: Override region n Start Address + 0x4 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for override region n + 0 + 31 + + + + + ENDADDR + Description cluster: Override region n End Address + 0x8 + read-write + 0x00000000 + 0x20 + + + ENDADDR + End address for override region n + 0 + 31 + + + + + PERM + Description cluster: Permission settings for override region n + 0x10 + read-write + 0x00000000 + 0x20 + + + READ + Read access + 0 + 0 + + + NotAllowed + Read access to override region n is not allowed + 0x0 + + + Allowed + Read access to override region n is allowed + 0x1 + + + + + WRITE + Write access + 1 + 1 + + + NotAllowed + Write access to override region n is not allowed + 0x0 + + + Allowed + Write access to override region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 2 + 2 + + + NotAllowed + Software execution from override region n is not allowed + 0x0 + + + Allowed + Software execution from override region n is allowed + 0x1 + + + + + SECATTR + Security mapping + 3 + 3 + + + Secure + Override region n is mapped in secure memory address space + 0x1 + + + NonSecure + Override region n is mapped in non-secure memory address space + 0x0 + + + + + + + PERMMASK + Description cluster: Masks permission setting fields from register OVERRIDE.PERM + 0x14 + read-write + 0x00000000 + 0x20 + + + READ + Read mask + 0 + 0 + + + Masked + Permission setting READ in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting READ in OVERRIDE register will be applied + 0x1 + + + + + WRITE + Write mask + 1 + 1 + + + Masked + Permission setting WRITE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting WRITE in OVERRIDE register will be applied + 0x1 + + + + + EXECUTE + Execute mask + 2 + 2 + + + Masked + Permission setting EXECUTE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting EXECUTE in OVERRIDE register will be applied + 0x1 + + + + + SECATTR + Security mapping mask + 3 + 3 + + + Masked + Permission setting SECATTR in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting SECATTR in OVERRIDE register will be applied + 0x1 + + + + + + + OWNER + Description cluster: Owner for override region + 0x18 + read-write + 0x00000000 + 0x20 + + + OWNERID + owner identifier for override region n + 0 + 3 + + + + + MASTERPORT + Description cluster: Override region n local master enable + 0x1C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable override + 0 + 0 + + + Disable + Override region n is disabled for master port 0 + 0x0 + + + Enable + Override region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable override + 1 + 1 + + + Disable + Override region n is disabled for master port 1 + 0x0 + + + Enable + Override region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable override + 2 + 2 + + + Disable + Override region n is disabled for master port 2 + 0x0 + + + Enable + Override region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable override + 3 + 3 + + + Disable + Override region n is disabled for master port 3 + 0x0 + + + Enable + Override region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable override + 4 + 4 + + + Disable + Override region n is disabled for master port 4 + 0x0 + + + Enable + Override region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable override + 5 + 5 + + + Disable + Override region n is disabled for master port 5 + 0x0 + + + Enable + Override region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable override + 6 + 6 + + + Disable + Override region n is disabled for master port 6 + 0x0 + + + Enable + Override region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable override + 7 + 7 + + + Disable + Override region n is disabled for master port 7 + 0x0 + + + Enable + Override region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable override + 8 + 8 + + + Disable + Override region n is disabled for master port 8 + 0x0 + + + Enable + Override region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable override + 9 + 9 + + + Disable + Override region n is disabled for master port 9 + 0x0 + + + Enable + Override region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable override + 10 + 10 + + + Disable + Override region n is disabled for master port 10 + 0x0 + + + Enable + Override region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable override + 11 + 11 + + + Disable + Override region n is disabled for master port 11 + 0x0 + + + Enable + Override region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable override + 12 + 12 + + + Disable + Override region n is disabled for master port 12 + 0x0 + + + Enable + Override region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable override + 13 + 13 + + + Disable + Override region n is disabled for master port 13 + 0x0 + + + Enable + Override region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable override + 14 + 14 + + + Disable + Override region n is disabled for master port 14 + 0x0 + + + Enable + Override region n is enabled for master port 14 + 0x1 + + + + + + + + + + GLOBAL_DPPIC00_NS + Distributed programmable peripheral interconnect controller 0 + 0x40042000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 6 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + 0x20 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + GLOBAL_DPPIC00_S + Distributed programmable peripheral interconnect controller 1 + 0x50042000 + + + + + + GLOBAL_PPIB00_NS + PPIB APB registers 0 + 0x40043000 + PPIB + + + + 0 + 0x1000 + registers + + PPIB + 0x20 + + + 0x20 + 0x4 + TASKS_SEND[%s] + Description collection: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + OVERFLOW + Unspecified + PPIB_OVERFLOW + read-write + 0x400 + + SEND + The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + The status for tasks overflow at SUBSCRIBE_SEND[0]. + 0 + 0 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_1 + The status for tasks overflow at SUBSCRIBE_SEND[1]. + 1 + 1 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_2 + The status for tasks overflow at SUBSCRIBE_SEND[2]. + 2 + 2 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_3 + The status for tasks overflow at SUBSCRIBE_SEND[3]. + 3 + 3 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_4 + The status for tasks overflow at SUBSCRIBE_SEND[4]. + 4 + 4 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_5 + The status for tasks overflow at SUBSCRIBE_SEND[5]. + 5 + 5 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_6 + The status for tasks overflow at SUBSCRIBE_SEND[6]. + 6 + 6 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_7 + The status for tasks overflow at SUBSCRIBE_SEND[7]. + 7 + 7 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_8 + The status for tasks overflow at SUBSCRIBE_SEND[8]. + 8 + 8 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_9 + The status for tasks overflow at SUBSCRIBE_SEND[9]. + 9 + 9 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_10 + The status for tasks overflow at SUBSCRIBE_SEND[10]. + 10 + 10 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_11 + The status for tasks overflow at SUBSCRIBE_SEND[11]. + 11 + 11 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_12 + The status for tasks overflow at SUBSCRIBE_SEND[12]. + 12 + 12 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_13 + The status for tasks overflow at SUBSCRIBE_SEND[13]. + 13 + 13 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_14 + The status for tasks overflow at SUBSCRIBE_SEND[14]. + 14 + 14 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_15 + The status for tasks overflow at SUBSCRIBE_SEND[15]. + 15 + 15 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_16 + The status for tasks overflow at SUBSCRIBE_SEND[16]. + 16 + 16 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_17 + The status for tasks overflow at SUBSCRIBE_SEND[17]. + 17 + 17 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_18 + The status for tasks overflow at SUBSCRIBE_SEND[18]. + 18 + 18 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_19 + The status for tasks overflow at SUBSCRIBE_SEND[19]. + 19 + 19 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_20 + The status for tasks overflow at SUBSCRIBE_SEND[20]. + 20 + 20 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_21 + The status for tasks overflow at SUBSCRIBE_SEND[21]. + 21 + 21 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_22 + The status for tasks overflow at SUBSCRIBE_SEND[22]. + 22 + 22 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_23 + The status for tasks overflow at SUBSCRIBE_SEND[23]. + 23 + 23 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_24 + The status for tasks overflow at SUBSCRIBE_SEND[24]. + 24 + 24 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_25 + The status for tasks overflow at SUBSCRIBE_SEND[25]. + 25 + 25 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_26 + The status for tasks overflow at SUBSCRIBE_SEND[26]. + 26 + 26 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_27 + The status for tasks overflow at SUBSCRIBE_SEND[27]. + 27 + 27 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_28 + The status for tasks overflow at SUBSCRIBE_SEND[28]. + 28 + 28 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_29 + The status for tasks overflow at SUBSCRIBE_SEND[29]. + 29 + 29 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_30 + The status for tasks overflow at SUBSCRIBE_SEND[30]. + 30 + 30 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_31 + The status for tasks overflow at SUBSCRIBE_SEND[31]. + 31 + 31 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + + + + + + GLOBAL_PPIB00_S + PPIB APB registers 1 + 0x50043000 + + + + + GLOBAL_PPIB01_NS + PPIB APB registers 2 + 0x40044000 + + + + + GLOBAL_PPIB01_S + PPIB APB registers 3 + 0x50044000 + + + + + GLOBAL_KMU_S + Key management unit + 0x50045000 + KMU + + + + 0 + 0x1000 + registers + + KMU + 0x20 + + + TASKS_PROVISION + Provision key slot + 0x0000 + write-only + 0x00000000 + 0x20 + + + TASKS_PROVISION + Provision key slot + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PUSH + Push key slot + 0x0004 + write-only + 0x00000000 + 0x20 + + + TASKS_PUSH + Push key slot + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_REVOKE + Revoke key slot + 0x0008 + write-only + 0x00000000 + 0x20 + + + TASKS_REVOKE + Revoke key slot + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READMETADATA + Read key slot metedata into METADATA register + 0x000C + write-only + 0x00000000 + 0x20 + + + TASKS_READMETADATA + Read key slot metedata into METADATA register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PUSHBLOCK + Block the PUSH operation of key slot, preventing the key slot being PUSH until next reset + 0x0010 + write-only + 0x00000000 + 0x20 + + + TASKS_PUSHBLOCK + Block the PUSH operation of key slot, preventing the key slot being PUSH until next reset + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_PROVISIONED + Key slot successfully provisioned + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_PROVISIONED + Key slot successfully provisioned + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PUSHED + Key slot successfully pushed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_PUSHED + Key slot successfully pushed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REVOKED + Key slot has been revoked and can no longer be used + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_REVOKED + Key slot has been revoked and can no longer be used + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error during PROVISION, PUSH, or REVOKE operations + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error during PROVISION, PUSH, or REVOKE operations + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_METADATAREAD + Key slot metedata has been read into METADATA register + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_METADATAREAD + Key slot metedata has been read into METADATA register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PUSHBLOCKED + The PUSHBLOCK operation was succesful + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_PUSHBLOCKED + The PUSHBLOCK operation was succesful + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + STATUS + KMU status register + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + KMU status + 0 + 0 + + + Ready + KMU is ready for new operation + 0x0 + + + Busy + KMU is busy, an operation is in progress + 0x1 + + + + + + + KEYSLOT + Select key slot to operate on + 0x500 + read-write + 0x00000000 + 0x20 + + + ID + Select key slot ID to provision, read, or push when TASKS_PROVISION, TASKS_PUSH, + TASKS_READMETADATA, or TASKS_REVOKE, is triggered. + 0 + 7 + + + + + SRC + Source address for provisioning + 0x504 + read-write + 0x00000000 + 0x20 + + + SRC + Source address for TASKS_PROVISION. + 0 + 31 + + + + + METADATA + Key slot metadata as read by TASKS_READMETADATA. + 0x508 + read-write + 0x00000000 + 0x20 + + + METADATA + Read metadata. + 0 + 31 + + + + + + + GLOBAL_AAR00_NS + Accelerated Address Resolver 0 + 0x40046000 + AAR + + + + 0 + 0x1000 + registers + + + AAR00_CCM00 + 70 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Address resolution procedure complete or ended due to an error + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Address resolution procedure complete or ended due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Operation aborted because of a STOP task or due to an error + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Operation aborted because of a STOP task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESOLVED + Publish configuration for event RESOLVED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESOLVED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NOTRESOLVED + Publish configuration for event NOTRESOLVED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NOTRESOLVED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSTATUS + Error status + 0x404 + read-only + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status when the ERROR event is generated + 0 + 2 + + + NoError + No errors have occurred + 0x0 + + + PrematureInptrEnd + End of INPTR job list before data structure was read. + 0x1 + + + PrematureOutptrEnd + End of OUTPTR job list before data structure was read. + 0x2 + + + DmaError + Bus error during DMA access. + 0x4 + + + + + + + ENABLE + Enable AAR + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x3 + + + + + + + MAXRESOLVED + Maximum number of IRKs to resolve + 0x508 + read-write + 0x00000001 + 0x20 + + + MAXRESOLVED + The maximum number of IRKs to resolve + 0 + 11 + + + + + IN + IN EasyDMA channel + AAR_IN + read-write + 0x530 + + PTR + Input pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Points to a job list containing AAR data structure + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + AAR_OUT + read-write + 0x538 + + PTR + Output pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x004 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes written to memory after triggering the START task. + 0 + 7 + + + + + + + + GLOBAL_CCM00_NS + AES CCM Mode Encryption 0 + 0x40046000 + GLOBAL_AAR00_NS + CCM + + + + 0 + 0x1000 + registers + + + AAR00_CCM00 + 70 + + CCM + 0x20 + + + TASKS_START + Start encryption/decryption. This operation will stop by itself when completed. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RATEOVERRIDE + Subscribe configuration for task RATEOVERRIDE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RATEOVERRIDE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Encrypt/decrypt complete or ended because of an error + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Encrypt/decrypt complete or ended because of an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + CCM error event + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MACSTATUS + MAC check result + 0x400 + read-only + 0x00000000 + 0x20 + + + MACSTATUS + The result of the MAC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MAC check failed + 0x0 + + + CheckPassed + MAC check passed + 0x1 + + + + + + + ERRORSTATUS + Error status + 0x404 + read-only + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status when the ERROR event is generated + 0 + 2 + + + NoError + No errors have occurred + 0x0 + + + PrematureInptrEnd + End of INPTR job list before CCM data structure was read. + 0x1 + + + PrematureOutptrEnd + End of OUTPTR job list before CCM data structure was read. + 0x2 + + + EncryptionTooSlow + Encryption of the unencrypted CCM data structure did not complete in time. + 0x3 + + + DmaError + Bus error during DMA access. + 0x4 + + + + + + + ENABLE + Enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + 0x20 + + + MODE + The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. + 0 + 1 + + + Encryption + AES CCM packet encryption mode + 0x0 + + + Decryption + Deprecated enumerator - This mode will run CCM decryption in the speed of the DATARATE field. + 0x1 + + + FastDecryption + AES CCM decryption mode. + 0x2 + + + + + PROTOCOL + Protocol and packet format selection + 8 + 9 + + + Ble + Bluetooth Low Energy packet format + 0x0 + + + Ieee802154 + 802.15.4 packet format + 0x1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 18 + + + 125Kbit + 125 Kbps + 0x0 + + + 250Kbit + 250 Kbps + 0x1 + + + 500Kbit + 500 Kbps + 0x2 + + + 1Mbit + 1 Mbps + 0x3 + + + 2Mbit + 2 Mbps + 0x4 + + + 4Mbit + 4 Mbps + 0x5 + + + + + MACLEN + CCM MAC length (bytes) + 24 + 26 + + + M0 + M = 0 This is a special case for CCM* where encryption is required but not authentication + 0x0 + + + M4 + M = 4 + 0x1 + + + M6 + M = 6 + 0x2 + + + M8 + M = 8 + 0x3 + + + M10 + M = 10 + 0x4 + + + M12 + M = 12 + 0x5 + + + M14 + M = 14 + 0x6 + + + M16 + M = 16 + 0x7 + + + + + + + KEY + Unspecified + CCM_KEY + read-write + 0x510 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 128-bit AES key + 0x000 + write-only + 0x00000000 + 0x20 + + + VALUE + AES 128-bit key value, bits (32*(i+1))-1 : (32*i) + 0 + 31 + + + + + + NONCE + Unspecified + CCM_NONCE + read-write + 0x520 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 13-byte NONCE vector Only the lower 13 bytes are used + 0x000 + read-write + 0x00000000 + 0x20 + + + VALUE + NONCE value, bits (32*(n+1))-1 : (32*n) + 0 + 31 + + + + + + IN + IN EasyDMA channel + CCM_IN + read-write + 0x530 + + PTR + Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job list containing encrypted CCM data structure in Decryption mode + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Input pointer + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + CCM_OUT + read-write + 0x538 + + PTR + Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job list containing decrypted CCM data structure in Decryption mode + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + + RATEOVERRIDE + Data rate override setting. + 0x544 + read-write + 0x00000002 + 0x20 + + + RATEOVERRIDE + Data rate override setting. + 0 + 2 + + + 125Kbit + 125 Kbps + 0x0 + + + 500Kbit + 500 Kbps + 0x2 + + + 1Mbit + 1 Mbps + 0x3 + + + 2Mbit + 2 Mbps + 0x4 + + + 4Mbit + 4 Mbps + 0x5 + + + + + + + ADATAMASK + CCM adata mask. + 0x548 + read-write + 0x000000E3 + 0x20 + + + ADATAMASK + CCM adata mask. + 0 + 7 + + + + + + + GLOBAL_AAR00_S + Accelerated Address Resolver 1 + 0x50046000 + + + + AAR00_CCM00 + 70 + + + + GLOBAL_CCM00_S + AES CCM Mode Encryption 1 + 0x50046000 + GLOBAL_AAR00_S + + + + AAR00_CCM00 + 70 + + + + GLOBAL_ECB00_NS + AES ECB Mode Encryption 0 + 0x40047000 + ECB + + + + 0 + 0x1000 + registers + + + ECB00 + 71 + + ECB + 0x20 + + + TASKS_START + Start ECB block encrypt + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Abort a possible executing ECB operation + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + ECB block encrypt complete + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + ECB block encrypt aborted because of a STOP task or due to an error + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + ECB block encrypt aborted because of a STOP task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSTATUS + Error status + 0x400 + read-only + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status when the ERROR event is generated + 0 + 2 + + + NoError + No errors have occurred + 0x0 + + + PrematureInptrEnd + End of INPTR job list before data structure was read. + 0x1 + + + PrematureOutptrEnd + End of OUTPTR job list before data structure was read. + 0x2 + + + EncryptionTooSlow + Deprecated enumerator - Encryption aborted due to higher priority peripheral requesting or using the AES module. + 0x3 + + + Aborted + Encryption aborted due to higher priority peripheral requesting or using the AES module. + 0x3 + + + DmaError + Bus error during DMA access. + 0x4 + + + + + + + KEY + Unspecified + ECB_KEY + read-write + 0x510 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 128-bit AES key + 0x000 + write-only + 0x00000000 + 0x20 + + + VALUE + AES 128-bit key value, bits (32*(n+1))-1 : (32*n) + 0 + 31 + + + + + + IN + IN EasyDMA channel + ECB_IN + read-write + 0x530 + + PTR + Input pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Points to a job list containing unencrypted ECB data structure + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + ECB_OUT + read-write + 0x538 + + PTR + Output pointer Points to a job list containing encrypted ECB data structure + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + + + + GLOBAL_ECB00_S + AES ECB Mode Encryption 1 + 0x50047000 + + + + ECB00 + 71 + + + + GLOBAL_CRACEN_S + CRACEN + 0x50048000 + CRACEN + + + + 0 + 0x1000 + registers + + + CRACEN + 72 + + CRACEN + 0x20 + + + EVENTS_CRYPTOMASTER + Event indicating that interrupt triggered at Cryptomaster + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CRYPTOMASTER + Event indicating that interrupt triggered at Cryptomaster + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RNG + Event indicating that interrupt triggered at RNG + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RNG + Event indicating that interrupt triggered at RNG + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PKEIKG + Event indicating that interrupt triggered at PKE or IKG + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PKEIKG + Event indicating that interrupt triggered at PKE or IKG + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CRYPTOMASTER + Enable or disable interrupt for event CRYPTOMASTER + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RNG + Enable or disable interrupt for event RNG + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PKEIKG + Enable or disable interrupt for event PKEIKG + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CRYPTOMASTER + Write '1' to enable interrupt for event CRYPTOMASTER + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RNG + Write '1' to enable interrupt for event RNG + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PKEIKG + Write '1' to enable interrupt for event PKEIKG + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CRYPTOMASTER + Write '1' to disable interrupt for event CRYPTOMASTER + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RNG + Write '1' to disable interrupt for event RNG + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PKEIKG + Write '1' to disable interrupt for event PKEIKG + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CRYPTOMASTER + Read pending status of interrupt for event CRYPTOMASTER + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RNG + Read pending status of interrupt for event RNG + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PKEIKG + Read pending status of interrupt for event PKEIKG + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable CRACEN peripheral modules. + 0x400 + read-write + 0x00000000 + 0x20 + + + CRYPTOMASTER + Enable cryptomaster + 0 + 0 + + + Disabled + Cryptomaster disabled. + 0x0 + + + Enabled + Cryptomaster enabled. + 0x1 + + + + + RNG + Enable RNG + 1 + 1 + + + Disabled + RNG disabled. + 0x0 + + + Enabled + RNG enabled. + 0x1 + + + + + PKEIKG + Enable PKE and IKG + 2 + 2 + + + Disabled + PKE and IKG disabled. + 0x0 + + + Enabled + PKE and IKG enabled. + 0x1 + + + + + + + SEEDVALID + Marks the SEED register as valid + 0x404 + read-write + 0x00000000 + 0x20 + + + VALID + Marks the SEED as valid + 0 + 0 + + + Disabled + Valid disabled. + 0x0 + + + Enabled + Valid enabled. + 0x1 + + + + + + + 0xC + 0x4 + SEED[%s] + Description collection: Seed word [n] for symmetric and asymmetric key generation. This register is only writable from KMU. + 0x410 + write-only + 0x00000000 + 0x20 + + + VAL + Seed value + 0 + 31 + + + + + SEEDLOCK + Lock the access to the SEED register. + 0x440 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable the lock + 0 + 0 + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + + + PROTECTEDRAMLOCK + Lock the access to the protected RAM. + 0x444 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable the lock + 0 + 0 + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + + + + + GLOBAL_SPIM00_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x4004A000 + SPIM + + + + 0 + 0x1000 + registers + + + SERIAL00 + 74 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIM_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STARTED + SPI transaction has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + SPI transaction has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PRESCALER + The prescaler is used to set the SPI frequency. + 0x52C + read-write + 0x00000040 + 0x20 + + + DIVISOR + Core clock to SCK divisor + 0 + 6 + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x5AC + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of SPIM core clock cycles. + 0 + 7 + + + + + + DCXCNT + DCX configuration + 0x5B4 + read-write + 0x00000000 + 0x20 + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + CSNPOL + Polarity of CSN output + 0x5B8 + read-write + 0x00000000 + 0x20 + + + CSNPOL_0 + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0x0 + + + HIGH + Active high (idle state low) + 0x1 + + + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DCX + Pin select for DCX signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIM_DMA + read-write + 0x700 + + RX + Unspecified + SPIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIS00_NS + SPI Slave 0 + 0x4004A000 + GLOBAL_SPIM00_NS + SPIS + + + + 0 + 0x1000 + registers + + + SERIAL00 + 74 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIS_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIS_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIS_DMA + read-write + 0x700 + + RX + Unspecified + SPIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE00_NS + UART with EasyDMA 0 + 0x4004A000 + GLOBAL_SPIM00_NS + UARTE + + + + 0 + 0x1000 + registers + + + SERIAL00 + 74 + + UARTE + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + UARTE_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + UARTE_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + UARTE_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x124 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + UARTE_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + UARTE_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + UARTE_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0x174 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + UARTE_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + UARTE_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + UARTE_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + PUBLISH_FRAMETIMEOUT + Publish configuration for event FRAMETIMEOUT + 0x1F4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMETIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + DMA_RX_END_DMA_RX_START + Shortcut between event DMA.RX.END and task DMA.RX.START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_END_DMA_RX_STOP + Shortcut between event DMA.RX.END and task DMA.RX.STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_TX_END_DMA_TX_STOP + Shortcut between event DMA.TX.END and task DMA.TX.STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMETIMEOUT_DMA_RX_STOP + Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP + 29 + 29 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMETIMEOUT + Enable or disable interrupt for event FRAMETIMEOUT + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to enable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to disable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency + 0x0075C000 + + + Baud31250 + 31250 baud when UARTE has 16 MHz peripheral clock frequency + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency + 0x03B00000 + + + Baud250000 + 250000 baud when UARTE has 16 MHz peripheral clock frequency + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency + 0x0F000000 + + + Baud1M + 1 megabaud when UARTE has 16 MHz peripheral clock frequency + 0x10000000 + + + + + + + CONFIG + Configuration of parity, hardware flow control, framesize, and packet timeout. + 0x56C + read-write + 0x00001000 + 0x20 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0x0 + + + Odd + Odd parity + 0x1 + + + + + FRAMESIZE + Set the data frame size + 9 + 12 + + + 9bit + 9 bit data frame size. 9th bit is treated as address bit. + 0x9 + + + 8bit + 8 bit data frame size. + 0x8 + + + 7bit + 7 bit data frame size. + 0x7 + + + 6bit + 6 bit data frame size. + 0x6 + + + 5bit + 5 bit data frame size. + 0x5 + + + 4bit + 4 bit data frame size. + 0x4 + + + + + ENDIAN + Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. + 13 + 13 + + + MSB + Data is trimmed from MSB end. + 0x0 + + + LSB + Data is trimmed from LSB end. + 0x1 + + + + + FRAMETIMEOUT + Enable packet timeout. + 14 + 14 + + + DISABLED + Packet timeout is disabled. + 0x0 + + + ENABLED + Packet timeout is enabled. + 0x1 + + + + + + + ADDRESS + Set the address of the UARTE for RX when used in 9 bit data frame mode. + 0x574 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Set address + 0 + 7 + + + + + FRAMETIMEOUT + Set the number of UARTE bits to count before triggering packet timeout. + 0x578 + read-write + 0x00000010 + 0x20 + + + COUNTERTOP + Number of UARTE bits before timeout. + 0 + 9 + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x604 + + TXD + Pin select for TXD signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RTS + Pin select for RTS signal + 0x0C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + UARTE_DMA + read-write + 0x700 + + RX + Unspecified + UARTE_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + UARTE_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + UARTE_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM00_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x5004A000 + + + + SERIAL00 + 74 + + + + GLOBAL_SPIS00_S + SPI Slave 1 + 0x5004A000 + GLOBAL_SPIM00_S + + + + SERIAL00 + 74 + + + + GLOBAL_UARTE00_S + UART with EasyDMA 1 + 0x5004A000 + GLOBAL_SPIM00_S + + + + SERIAL00 + 74 + + + + GLOBAL_GLITCHDET_S + Voltage glitch detectors + 0x5004B000 + GLITCHDET + + + + 0 + 0x1000 + registers + + GLITCHDET + 0x20 + + + CONFIG + Configuration for glitch detector + 0x5A0 + read-write + 0x00000001 + 0x20 + + + ENABLE + Enable glitch detector + 0 + 0 + + + Disable + Disable glitch detector + 0x0 + + + Enable + Enable glitch detector + 0x1 + + + + + MODE + Glitch detector mode + 4 + 4 + + + HighPassFilter + High pass filter mode + 0x0 + + + CapDiv + Cap divider mode + 0x1 + + + + + + + + + GLOBAL_RRAMC_S + RRAM controller GLITCH detector + 0x5004B000 + GLOBAL_GLITCHDET_S + RRAMC + + + + 0 + 0x1000 + registers + + + RRAMC + 75 + + RRAMC + 0x20 + + + TASKS_WAKEUP + Wakeup the RRAM from low power mode + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_WAKEUP + Wakeup the RRAM from low power mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COMMITWRITEBUF + Commits the data stored in internal write-buffer to RRAM + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COMMITWRITEBUF + Commits the data stored in internal write-buffer to RRAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_WAKEUP + Subscribe configuration for task WAKEUP + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task WAKEUP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COMMITWRITEBUF + Subscribe configuration for task COMMITWRITEBUF + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COMMITWRITEBUF will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_WOKENUP + RRAMC is woken up from low power mode + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_WOKENUP + RRAMC is woken up from low power mode + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READY + RRAMC is ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + RRAMC is ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READYNEXT + Ready to accept a new write operation + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_READYNEXT + Ready to accept a new write operation + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCESSERROR + RRAM access error + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCESSERROR + RRAM access error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ECCERROR + Uncorrectable ECC error detected + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_ECCERROR + Uncorrectable ECC error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_WOKENUP + Publish configuration for event WOKENUP + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WOKENUP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + WOKENUP + Enable or disable interrupt for event WOKENUP + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY + Enable or disable interrupt for event READY + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READYNEXT + Enable or disable interrupt for event READYNEXT + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ACCESSERROR + Enable or disable interrupt for event ACCESSERROR + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ECCERROR + Enable or disable interrupt for event ECCERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + WOKENUP + Write '1' to enable interrupt for event WOKENUP + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY + Write '1' to enable interrupt for event READY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READYNEXT + Write '1' to enable interrupt for event READYNEXT + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCESSERROR + Write '1' to enable interrupt for event ACCESSERROR + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ECCERROR + Write '1' to enable interrupt for event ECCERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + WOKENUP + Write '1' to disable interrupt for event WOKENUP + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY + Write '1' to disable interrupt for event READY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READYNEXT + Write '1' to disable interrupt for event READYNEXT + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCESSERROR + Write '1' to disable interrupt for event ACCESSERROR + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ECCERROR + Write '1' to disable interrupt for event ECCERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + WOKENUP + Read pending status of interrupt for event WOKENUP + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY + Read pending status of interrupt for event READY + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READYNEXT + Read pending status of interrupt for event READYNEXT + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + ACCESSERROR + Read pending status of interrupt for event ACCESSERROR + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + ECCERROR + Read pending status of interrupt for event ECCERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + READY + RRAMC ready status + 0x400 + read-only + 0x00000000 + 0x20 + + + READY + RRAMC is ready or busy + 0 + 0 + + + Busy + RRAMC is busy + 0x0 + + + Ready + The current RRAMC operation is completed and RRAMC is ready + 0x1 + + + + + + + READYNEXT + Ready next flag + 0x404 + read-only + 0x00000000 + 0x20 + + + READYNEXT + RRAMC can accept a new write operation + 0 + 0 + + + Busy + RRAMC cannot accept any write operation now + 0x0 + + + Ready + RRAMC is ready to accept a new write operation + 0x1 + + + + + + + ACCESSERRORADDR + Address of the first access error + 0x408 + read-only + 0x00FFFFFF + 0x20 + + + ADDRESS + Access error address + 0 + 31 + + + + + BUFSTATUS + Unspecified + RRAMC_BUFSTATUS + read-write + 0x410 + + WRITEBUFEMPTY + Internal write-buffer is empty + 0x08 + read-only + 0x00000000 + 0x20 + + + EMPTY + 0 + 0 + + + NotEmpty + The internal write-buffer has data that needs committing + 0x0 + + + Empty + The internal write-buffer is empty and has no content that needs to be committed + 0x1 + + + + + + + + ECC + Unspecified + RRAMC_ECC + read-write + 0x420 + + ERRORADDR + Address of the first ECC error that could not be corrected + 0x000 + read-only + 0x00FFFFFF + 0x20 + + + ADDRESS + ECC error address + 0 + 31 + + + + + + CONFIG + Configuration register + 0x500 + read-write + 0x00000000 + 0x20 + + + WEN + Write enable + 0 + 0 + + + Disabled + Write is disabled + 0x0 + + + Enabled + Write is enabled + 0x1 + + + + + WRITEBUFSIZE + write-buffer size in number of 128-bit words + 8 + 13 + + + Unbuffered + Disable buffering + 0x00 + + + + + + + READYNEXTTIMEOUT + Configuration for ready next timeout counter, in units of AXI clock frequency + 0x50C + read-write + 0x00000080 + 0x20 + + + VALUE + Preload value for waiting for a next write + 0 + 11 + + + EN + Enable ready next timeout + 31 + 31 + + + Disable + Disable ready next timeout + 0x0 + + + Enable + Enable ready next timeout + 0x1 + + + + + + + POWER + Unspecified + RRAMC_POWER + read-write + 0x510 + + CONFIG + Power configuration + 0x000 + read-write + 0x00000100 + 0x20 + + + ACCESSTIMEOUT + Access timeout, in 31.25 ns units, used for going into standby power mode or remain active on wake up + 0 + 15 + + + POF + Power on failure warning handling configuration + 16 + 16 + + + Wait + Wait until the current RRAM write finishes + 0x0 + + + Abort + Abort the current RRAM write + 0x1 + + + + + + + LOWPOWERCONFIG + Low power mode configuration + 0x008 + read-write + 0x00000000 + 0x20 + + + MODE + RRAM low power mode + 0 + 1 + + + PowerDown + The RRAM goes into power down mode + 0x0 + + + Standby + The RRAM automatically goes into standby mode while the RRAM is not being accessed + 0x1 + + + NAP + The RRAM goes into NAP mode + 0x2 + + + PowerOff + The RRAM is powered Off + 0x3 + + + + + + + + ERASE + Unspecified + RRAMC_ERASE + read-write + 0x540 + + ERASEALL + Register for erasing whole RRAM main block, that includes the SICR and the UICR + 0x000 + read-write + 0x00000000 + 0x20 + + + ERASE + Erase whole RRAM main block + 0 + 0 + + + NoOperation + No operation + 0x0 + + + Erase + Start erase of chip + 0x1 + + + + + + + + 5 + 0x008 + REGION[%s] + Unspecified + RRAMC_REGION + read-write + 0x550 + + ADDRESS + Description cluster: Region address + 0x000 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address of the region [n] + 0 + 31 + + + + + CONFIG + Description cluster: Region configuration + 0x004 + read-write + 0x00000000 + 0x20 + + + READ + Read access + 0 + 0 + + + NotAllowed + Read access to override region [n] is not allowed + 0x0 + + + Allowed + Read access to override region [n] is allowed + 0x1 + + + + + WRITE + Write access + 1 + 1 + + + NotAllowed + Write access to override region [n] is not allowed + 0x0 + + + Allowed + Write access to override region [n] is allowed + 0x1 + + + + + EXECUTE + Execute access + 2 + 2 + + + NotAllowed + Execute access to override region [n] is not allowed + 0x0 + + + Allowed + Execute access to override region [n] is allowed + 0x1 + + + + + SECURE + Secure access + 3 + 3 + + + NonSecure + Both Secure and non-Secure access to override region [n] is allowed + 0x0 + + + Secure + Only secure access to override region [n] is allowed + 0x1 + + + + + OWNER + Owner ID + 4 + 7 + + + NotEnforced + Owner ID protection is not enforced + 0x0 + + + + + WRITEONCE + Write-once + 12 + 12 + + + Disabled + Write-once disabled + 0x0 + + + Enabled + Write-once enabled + 0x1 + + + + + LOCK + Enable lock + 13 + 13 + oneToSet + + + Disabled + Lock disabled for region [n] + 0x0 + + + Enabled + Lock enabled for region [n] + 0x1 + + + + + SIZE + Size in KBytes of region [n] + 16 + 20 + + + + + + + + GLOBAL_VPR00_NS + VPR peripheral registers 0 + 0x4004C000 + VPR + + + + 0 + 0x1000 + registers + + + VPR00 + 76 + + VPR + 0x20 + + + 0x7 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TASKS_TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + EN + Subscription enable bit + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x7 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: VPR event [n] register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + VPR event [n] register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event EVENTS_TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + EN + Publication enable bit + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + DEBUGIF + Unspecified + VPR_DEBUGIF + read-write + 0x400 + + DATA0 + Abstract Data 0. Read/write data for argument 0 + 0x10 + read-write + 0x00000000 + 0x20 + + + DATA0 + Abstract Data 0 + 0 + 31 + + + + + DATA1 + Abstract Data 1. Read/write data for argument 1 + 0x14 + read-write + 0x00000000 + 0x20 + + + DATA1 + Abstract Data 1 + 0 + 31 + + + + + DMCONTROL + Debug Module Control + 0x40 + read-write + 0x00000000 + 0x20 + + + DMACTIVE + Reset signal for the debug module. + 0 + 0 + + + Disabled + Reset the debug module itself + 0x0 + + + Enabled + Normal operation + 0x1 + + + + + NDMRESET + Reset signal output from the debug module to the system. + 1 + 1 + + + Inactive + Reset inactive + 0x0 + + + Active + Reset active + 0x1 + + + + + CLRRESETHALTREQ + Clear the halt on reset request. + 2 + 2 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the halt on reset request + 0x1 + + + + + SETRESETHALTREQ + Set the halt on reset request. + 3 + 3 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Sets the halt on reset request + 0x1 + + + + + HARTSELHI + The high 10 bits of hartsel. + 6 + 15 + write-only + + + HARTSELLO + The low 10 bits of hartsel. + 16 + 25 + write-only + + + HASEL + Definition of currently selected harts. + 26 + 26 + write-only + + + Single + Single hart selected. + 0x0 + + + Multiple + Multiple harts selected + 0x1 + + + + + ACKHAVERESET + Clear the havereset. + 28 + 28 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the havereset for selected harts. + 0x1 + + + + + HARTRESET + Reset harts. + 29 + 29 + + + Deasserted + Reset de-asserted. + 0x0 + + + Asserted + Reset asserted. + 0x1 + + + + + RESUMEREQ + Resume currently selected harts. + 30 + 30 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Resumed + Currently selected harts resumed. + 0x1 + + + + + HALTREQ + Halt currently selected harts. + 31 + 31 + write-only + + + Clear + Clears halt request bit for all currently selected harts. + 0x0 + + + Halt + Currently selected harts halted. + 0x1 + + + + + + + DMSTATUS + Debug Module Status + 0x44 + read-only + 0x00400082 + 0x20 + + + VERSION + Version of the debug module. + 0 + 3 + + + NotPresent + Debug module not present. + 0x0 + + + V011 + There is a Debug Module and it conforms to version 0.11 of this specifcation. + 0x1 + + + V013 + There is a Debug Module and it conforms to version 0.13 of this specifcation. + 0x2 + + + NonConform + There is a Debug Module but it does not conform to any available version of the spec. + 0xF + + + + + CONFSTRPTRVALID + Configuration string. + 4 + 4 + + + NotRelevant + The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. + 0x0 + + + Address + The confstrptr0..confstrptr3 holds the address of the configuration string. + 0x1 + + + + + HASRESETHALTREQ + Halt-on-reset support status. + 5 + 5 + + + No + Halt-on-reset is supported. + 0x0 + + + Yes + Halt-on-reset is not supported. + 0x1 + + + + + AUTHBUSY + Authentication busy status. + 6 + 6 + + + No + The authentication module is ready. + 0x0 + + + Yes + The authentication module is busy. + 0x1 + + + + + AUTHENTICATED + Authentication status. + 7 + 7 + + + No + Authentication required before using the debug module. + 0x0 + + + Yes + Authentication passed. + 0x1 + + + + + ANYHALTED + Any currently selected harts halted status. + 8 + 8 + + + No + None of the currently selected harts halted. + 0x0 + + + Yes + Any of the currently selected harts halted. + 0x1 + + + + + ALLHALTED + All currently selected harts halted status. + 9 + 9 + + + No + Not all of the currently selected harts halted. + 0x0 + + + Yes + All of the currently selected harts halted. + 0x1 + + + + + ANYRUNNING + Any currently selected harts running status. + 10 + 10 + + + No + None of the currently selected harts running. + 0x0 + + + Yes + Any of the currently selected harts running. + 0x1 + + + + + ALLRUNNING + All currently selected harts running status. + 11 + 11 + + + No + Not all of the currently selected harts running. + 0x0 + + + Yes + All of the currently selected harts running. + 0x1 + + + + + ANYUNAVAIL + Any currently selected harts unavailable status. + 12 + 12 + + + No + None of the currently selected harts unavailable. + 0x0 + + + Yes + Any of the currently selected harts unavailable. + 0x1 + + + + + ALLUNAVAIL + All currently selected harts unavailable status. + 13 + 13 + + + No + Not all of the currently selected harts unavailable. + 0x0 + + + Yes + All of the currently selected harts unavailable. + 0x1 + + + + + ANYNONEXISTENT + Any currently selected harts nonexistent status. + 14 + 14 + + + No + None of the currently selected harts nonexistent. + 0x0 + + + Yes + Any of the currently selected harts nonexistent. + 0x1 + + + + + ALLNONEXISTENT + All currently selected harts nonexistent status. + 15 + 15 + + + No + Not all of the currently selected harts nonexistent. + 0x0 + + + Yes + All of the currently selected harts nonexistent. + 0x1 + + + + + ANYRESUMEACK + Any currently selected harts acknowledged last resume request. + 16 + 16 + + + No + None of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + Any of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ALLRESUMEACK + All currently selected harts acknowledged last resume + 17 + 17 + + + No + Not all of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + All of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ANYHAVERESET + Any currently selected harts have been reset and reset is not acknowledged. + 18 + 18 + + + No + None of the currently selected harts have been reset and reset is not acknowledget. + 0x0 + + + Yes + Any of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + ALLHAVERESET + All currently selected harts have been reset and reset is not acknowledge + 19 + 19 + + + No + Not all of the currently selected harts have been reset and reset is not acknowledge. + 0x0 + + + Yes + All of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + IMPEBREAK + Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. + 22 + 22 + + + No + No implicit ebreak instruction. + 0x0 + + + Yes + Implicit ebreak instruction. + 0x1 + + + + + + + HARTINFO + Hart Information + 0x48 + read-write + 0x00000000 + 0x20 + + + DATAADDR + Data Address + 0 + 11 + read-only + + + DATASIZE + Data Size + 12 + 15 + read-only + + + DATAACCESS + Data Access + 16 + 16 + read-only + + + No + The data registers are shadowed in the hart + by CSRs. Each CSR is DXLEN bits in size, and + corresponds to a single argument. + 0x0 + + + Yes + The data registers are shadowed in the hart's + memory map. Each register takes up 4 bytes in + the memory map. + 0x1 + + + + + NSCRATCH + Number of dscratch registers + 20 + 23 + read-only + + + + + HALTSUM1 + Halt Summary 1 + 0x4C + read-write + 0x00000000 + 0x20 + + + HALTSUM1 + Halt Summary 1 + 0 + 31 + read-only + + + + + HAWINDOWSEL + Hart Array Window Select + 0x50 + read-write + 0x00000000 + 0x20 + + + HAWINDOWSEL + The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. + 0 + 14 + read-only + + + + + HAWINDOW + Hart Array Window + 0x54 + read-write + 0x00000000 + 0x20 + + + MASKDATA + Mask data. + 0 + 31 + + + + + ABSTRACTCS + Abstract Control and Status + 0x58 + read-write + 0x01000002 + 0x20 + + + DATACOUNT + Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. + 0 + 3 + read-only + + + CMDERR + Command error when the abstract command fails. + 8 + 10 + + + NoError + No error. + 0x0 + + + Busy + An abstract command was executing while command, + abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read + or written. This status is only written if cmderr contains 0 + 0x1 + + + NotSupported + The requested command is notsupported, + regardless of whether the hart is running or not. + 0x2 + + + Exception + An exception occurred while executing the + command (e.g. while executing theProgram Buffer). + 0x3 + + + HaltResume + The abstract command couldn't execute + because the hart wasn't in the required state (running/halted). or unavailable. + 0x4 + + + Bus + The abstract command failed due to abus + error (e.g. alignment, access size, or timeout). + 0x5 + + + Other + The command failed for another reason. + 0x7 + + + + + BUSY + Abstract command execution status. + 12 + 12 + read-only + + + NotBusy + Not busy. + 0x0 + + + Busy + An abstract command is currently being executed. + This bit is set as soon as command is written, and is not cleared until that command has completed. + 0x1 + + + + + PROGBUFSIZE + Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. + 24 + 28 + read-only + + + + + ABSTRACTCMD + Abstract command + 0x5C + write-only + 0x00000000 + 0x20 + + + CONTROL + This Field is interpreted in a command specific manner, described for each abstract command. + 0 + 23 + + + CMDTYPE + The type determines the overall functionality of this abstract command. + 24 + 31 + + + REGACCESS + Register Access Command + 0x00 + + + QUICKACCESS + Quick Access Command + 0x01 + + + MEMACCESS + Memory Access Command + 0x02 + + + + + + + ABSTRACTAUTO + Abstract Command Autoexec + 0x60 + read-write + 0x00000000 + 0x20 + + + AUTOEXECDATA + When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. + 0 + 11 + read-only + + + AUTOEXECPROGBUF + When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. + 16 + 31 + read-only + + + + + 0x4 + 0x4 + CONFSTRPTR[%s] + Description collection: Configuration String Pointer [n] + 0x64 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + NEXTDM + Next Debug Module + 0x74 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + 0x10 + 0x4 + PROGBUF[%s] + Description collection: Program Buffer [n] + 0x80 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + AUTHDATA + Authentication Data + 0xC0 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + HALTSUM2 + Halt Summary 2 + 0xD0 + read-write + 0x00000000 + 0x20 + + + HALTSUM2 + Halt Summary 2 + 0 + 31 + read-only + + + + + HALTSUM3 + Halt Summary 3 + 0xD4 + read-write + 0x00000000 + 0x20 + + + HALTSUM3 + Halt Summary 3 + 0 + 31 + read-only + + + + + SBADDRESS3 + System Bus Addres 127:96 + 0xDC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 127:96 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBCS + System Bus Access Control and Status + 0xE0 + read-write + 0x20000000 + 0x20 + + + SBACCESS8 + 0 + 0 + read-only + + + sbaccess8 + 8-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS16 + 1 + 1 + read-only + + + sbaccess16 + 16-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS32 + 2 + 2 + read-only + + + sbaccess32 + 32-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS64 + 3 + 3 + read-only + + + sbaccess64 + 64-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS128 + 4 + 4 + read-only + + + sbaccess128 + 128-bit system bus accesses are supported. + 0x1 + + + + + SBASIZE + Width of system bus addresses in bits. (0 indicates there is no bus access support.) + 5 + 11 + read-only + + + SBERROR + 12 + 14 + read-only + + + Normal + There was no bus error. + 0x0 + + + Timeout + There was a timeout. + 0x1 + + + Address + A bad address was accessed. + 0x2 + + + Alignment + There was an alignment error. + 0x3 + + + Size + An access of unsupported size was requested. + 0x4 + + + Other + Other. + 0x7 + + + + + SBREADONDATA + 15 + 15 + read-only + + + sbreadondata + Every read from sbdata0 automatically + triggers a system bus read at the (possibly autoincremented) address. + 0x1 + + + + + SBAUTOINCREMENT + 16 + 16 + read-only + + + sbautoincrement + sbaddress is incremented by the access + size (in bytes) selected in sbaccess after every system bus access. + 0x1 + + + + + SBACCESS + 17 + 19 + read-only + + + size8 + 8-bit. + 0x0 + + + size16 + 16-bit. + 0x1 + + + size32 + 32-bit. + 0x2 + + + size64 + 64-bit. + 0x3 + + + size128 + 128-bit. + 0x4 + + + + + SBREADONADDR + 20 + 20 + read-only + + + sbreadonaddr + Every write to sbaddress0 automatically + triggers a system bus read at the new address. + 0x1 + + + + + SBBUSY + 21 + 21 + read-only + + + notbusy + System bus master is not busy. + 0x0 + + + busy + System bus master is busy. + 0x1 + + + + + SBBUSYERROR + 22 + 22 + read-only + + + noerror + No error. + 0x0 + + + error + Debugger access attempted while one in progress. + 0x1 + + + + + SBVERSION + 29 + 31 + read-only + + + version0 + The System Bus interface conforms to mainline + drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. + 0x0 + + + version1 + The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. + Other values are reserved for future versions. + 0x1 + + + + + + + SBADDRESS0 + System Bus Addres 31:0 + 0xE4 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 31:0 of the physical address in + sbaddress. + 0 + 31 + read-only + + + + + SBADDRESS1 + System Bus Addres 63:32 + 0xE8 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 63:32 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBADDRESS2 + System Bus Addres 95:64 + 0xEC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 95:64 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBDATA0 + System Bus Data 31:0 + 0xF0 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 31:0 of sbdata + 0 + 31 + read-only + + + + + SBDATA1 + System Bus Data 63:32 + 0xF4 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 63:32 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA2 + System Bus Data 95:64 + 0xF8 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 95:64 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA3 + System Bus Data 127:96 + 0xFC + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 127:96 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + HALTSUM0 + Halt summary 0 + 0x100 + read-write + 0x00000000 + 0x20 + + + HALTSUM0 + Halt summary 0 + 0 + 31 + read-only + + + + + + CPURUN + State of the CPU after a core reset + 0x800 + read-write + 0x00000000 + 0x20 + + + EN + Controls CPU running state after a core reset. + 0 + 0 + + + Stopped + CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. + 0x0 + + + Running + CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. + 0x1 + + + + + + + INITPC + Initial value of the PC at CPU start. + 0x808 + read-write + 0x00000000 + 0x20 + + + INITPC + Initial value of the PC at CPU start. + 0 + 31 + + + + + + + GLOBAL_VPR00_S + VPR peripheral registers 1 + 0x5004C000 + + + + VPR00 + 76 + + + + GLOBAL_P2_NS + GPIO Port 0 + 0x40050400 + GPIO + + + + + 0 + 0x200 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x000 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x004 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x00C + read-only + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x010 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x014 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x018 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + 0x20 + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x024 + read-write + 0x00000000 + 0x20 + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Pin n configuration of GPIO pin + 0x080 + read-write + 0x00000002 + 0x20 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE0 + Drive configuration for '0' + 8 + 9 + + + S0 + Standard '0' + 0x0 + + + H0 + High drive '0' + 0x1 + + + D0 + Disconnect '0'(normally used for wired-or connections) + 0x2 + + + E0 + Extra high drive '0' + 0x3 + + + + + DRIVE1 + Drive configuration for '1' + 10 + 11 + + + S1 + Standard '1' + 0x0 + + + H1 + High drive '1' + 0x1 + + + D1 + Disconnect '1'(normally used for wired-or connections) + 0x2 + + + E1 + Extra high drive '1' + 0x3 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + CTRLSEL + Select which module has direct control over this pin + 28 + 30 + + + GPIO + GPIO or peripherals with PSEL registers + 0x0 + + + VPR + VPR processor + 0x1 + + + GRTC + GRTC peripheral + 0x4 + + + + + + + + + GLOBAL_P2_S + GPIO Port 1 + 0x50050400 + + + + + + GLOBAL_CTRLAP_NS + Control access port 0 + 0x40052000 + CTRLAPPERI + + + + 0 + 0x1000 + registers + + + CTRLAP + 82 + + CTRLAPPERI + 0x20 + + + EVENTS_RXREADY + RXSTATUS is changed to DataPending. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXREADY + RXSTATUS is changed to DataPending. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDONE + TXSTATUS is changed to NoDataPending. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDONE + TXSTATUS is changed to NoDataPending. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXREADY + Enable or disable interrupt for event RXREADY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDONE + Enable or disable interrupt for event TXDONE + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDONE + Write '1' to enable interrupt for event TXDONE + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDONE + Write '1' to disable interrupt for event TXDONE + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RXREADY + Read pending status of interrupt for event RXREADY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TXDONE + Read pending status of interrupt for event TXDONE + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + MAILBOX + Unspecified + CTRLAPPERI_MAILBOX + read-write + 0x400 + + RXDATA + Data sent from the debugger to the CPU. + 0x000 + read-only + 0x00000000 + 0x20 + + + RXDATA + Data received from debugger. + 0 + 31 + + + + + RXSTATUS + Status to indicate if data sent from the debugger to the CPU has been read. + 0x004 + read-only + 0x00000000 + 0x20 + + + RXSTATUS + Status of data in register RXDATA. + 0 + 0 + + + NoDataPending + No data is pending in register RXDATA. + 0x0 + + + DataPending + Data is pending in register RXDATA. + 0x1 + + + + + + + TXDATA + Data sent from the CPU to the debugger. + 0x80 + read-write + 0x00000000 + 0x20 + + + TXDATA + Data sent to debugger. + 0 + 31 + + + + + TXSTATUS + Status to indicate if data sent from the CPU to the debugger has been read. + 0x84 + read-only + 0x00000000 + 0x20 + + + TXSTATUS + Status of data in register TXDATA. + 0 + 0 + + + NoDataPending + No data is pending in register TXDATA. + 0x0 + + + DataPending + Data is pending in register TXDATA. + 0x1 + + + + + + + + ERASEPROTECT + Unspecified + CTRLAPPERI_ERASEPROTECT + read-write + 0x500 + + LOCK + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. + 0x000 + read-writeonce + 0x00000000 + 0x20 + + + LOCK + Lock ERASEPROTECT.DISABLE register from being written until next reset. + 0 + 0 + + + Unlocked + Register ERASEPROTECT.DISABLE is writeable. + 0x0 + + + Locked + Register ERASEPROTECT.DISABLE is read-only. + 0x1 + + + + + + + DISABLE + This register disables the ERASEPROTECT register and performs an ERASEALL operation. + 0x004 + writeonce + 0x00000000 + 0x20 + + + KEY + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + 0 + 31 + + + + + + RESET + System reset request. + 0x520 + write-only + 0x00000000 + 0x20 + + + RESET + Reset request + 0 + 2 + + + NoReset + No reset is generated + 0x0 + + + SoftReset + Perform a device soft reset + 0x1 + + + HardReset + Perform a device hard reset + 0x2 + + + PinReset + Perform a device pin reset + 0x4 + + + + + + + + + GLOBAL_CTRLAP_S + Control access port 1 + 0x50052000 + + + + CTRLAP + 82 + + + + GLOBAL_TAD_NS + Trace and debug control 0 + 0x40053000 + TAD + + + + 0 + 0x1000 + registers + + TAD + 0x20 + + + SYSPWRUPREQ + System power-up request + 0x400 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + DBGPWRUPREQ + Debug power-up request + 0x404 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + ENABLE + Enable debug domain and aquire selected GPIOs + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + DISABLED + Disable debug domain and release selected GPIOs + 0x0 + + + ENABLED + Enable debug domain and aquire selected GPIOs + 0x1 + + + + + + + TRACEPORTSPEED + Trace port speed + 0x518 + read-write + 0x00000000 + 0x20 + + + TRACEPORTSPEED + Trace port speed is divided from CPU clock. The TRACECLK pin output will be divided again by two from the trace port clock. + 0 + 1 + + + DIV1 + Trace port speed equals CPU clock + 0x0 + + + DIV2 + Trace port speed equals CPU clock divided by 2 + 0x1 + + + DIV4 + Trace port speed equals CPU clock divided by 4 + 0x2 + + + DIV32 + Trace port speed equals CPU clock divided by 32 + 0x3 + + + + + + + TINSTANCE + SW-DP Target instance + 0x520 + read-write + 0x00000000 + 0x20 + + + TINSTANCE + TINSTANCE bits are used in the SW-DP DLPIDR.TINSTANCE field. + 0 + 3 + + + + + + + GLOBAL_TAD_S + Trace and debug control 1 + 0x50053000 + + + + + GLOBAL_TIMER00_NS + Timer/Counter 0 + 0x40055000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER00 + 85 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + 0x20 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + 0x20 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + 0x20 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + 0x00000000 + 0x20 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + + + GLOBAL_TIMER00_S + Timer/Counter 1 + 0x50055000 + + + + TIMER00 + 85 + + + + GLOBAL_SPU10_S + System protection unit 1 + 0x50080000 + + + + SPU10 + 128 + + + + GLOBAL_DPPIC10_NS + Distributed programmable peripheral interconnect controller 2 + 0x40082000 + + + + + + GLOBAL_DPPIC10_S + Distributed programmable peripheral interconnect controller 3 + 0x50082000 + + + + + + GLOBAL_PPIB10_NS + PPIB APB registers 4 + 0x40083000 + + + + + GLOBAL_PPIB10_S + PPIB APB registers 5 + 0x50083000 + + + + + GLOBAL_PPIB11_NS + PPIB APB registers 6 + 0x40084000 + + + + + GLOBAL_PPIB11_S + PPIB APB registers 7 + 0x50084000 + + + + + GLOBAL_TIMER10_NS + Timer/Counter 2 + 0x40085000 + + + + TIMER10 + 133 + + + + GLOBAL_TIMER10_S + Timer/Counter 3 + 0x50085000 + + + + TIMER10 + 133 + + + + GLOBAL_RTC10_NS + Real-time counter 0 + 0x40086000 + RTC + + + + 0 + 0x1000 + registers + + + RTC10 + 134 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 23 + + + + + + + GLOBAL_RTC10_S + Real-time counter 1 + 0x50086000 + + + + RTC10 + 134 + + + + GLOBAL_EGU10_NS + Event generator unit 0 + 0x40087000 + EGU + + + + 0 + 0x1000 + registers + + + EGU10 + 135 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + + + GLOBAL_EGU10_S + Event generator unit 1 + 0x50087000 + + + + EGU10 + 135 + + + + GLOBAL_RADIO_NS + 2.4 GHz radio 0 + 0x4008A000 + RADIO + + + + 0 + 0x2000 + registers + + + RADIO_0 + 138 + + + RADIO_1 + 139 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x028 + write-only + 0x00000000 + 0x20 + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x02C + write-only + 0x00000000 + 0x20 + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SOFTRESET + Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. + 0x0A4 + write-only + 0x00000000 + 0x20 + + + TASKS_SOFTRESET + Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_TXEN + Subscribe configuration for task TXEN + 0x100 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RXEN + Subscribe configuration for task RXEN + 0x104 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x108 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x10C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x110 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RSSISTART + Subscribe configuration for task RSSISTART + 0x114 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RSSISTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_BCSTART + Subscribe configuration for task BCSTART + 0x118 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task BCSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_BCSTOP + Subscribe configuration for task BCSTOP + 0x11C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task BCSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_EDSTART + Subscribe configuration for task EDSTART + 0x120 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task EDSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_EDSTOP + Subscribe configuration for task EDSTOP + 0x124 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task EDSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CCASTART + Subscribe configuration for task CCASTART + 0x128 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CCASTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CCASTOP + Subscribe configuration for task CCASTOP + 0x12C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CCASTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SOFTRESET + Subscribe configuration for task SOFTRESET + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SOFTRESET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x200 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x204 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x208 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x20C + read-write + 0x00000000 + 0x20 + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x210 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x214 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + Memory access for packet data has been completed + 0x218 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Memory access for packet data has been completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PHYEND + The last bit is sent on air or last bit is received + 0x21C + read-write + 0x00000000 + 0x20 + + + EVENTS_PHYEND + The last bit is sent on air or last bit is received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x220 + read-write + 0x00000000 + 0x20 + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x224 + read-write + 0x00000000 + 0x20 + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x228 + read-write + 0x00000000 + 0x20 + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x22C + read-write + 0x00000000 + 0x20 + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x230 + read-write + 0x00000000 + 0x20 + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x238 + read-write + 0x00000000 + 0x20 + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register) + 0x23C + read-write + 0x00000000 + 0x20 + + + EVENTS_EDEND + Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x240 + read-write + 0x00000000 + 0x20 + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x244 + read-write + 0x00000000 + 0x20 + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x248 + read-write + 0x00000000 + 0x20 + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x24C + read-write + 0x00000000 + 0x20 + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit + 0x250 + read-write + 0x00000000 + 0x20 + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x254 + read-write + 0x00000000 + 0x20 + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYNC + Initial sync detected + 0x258 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYNC + Initial sync detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CTEPRESENT + CTEInfo byte is received + 0x25C + read-write + 0x00000000 + 0x20 + + + EVENTS_CTEPRESENT + CTEInfo byte is received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x300 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXREADY + Publish configuration for event TXREADY + 0x304 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXREADY + Publish configuration for event RXREADY + 0x308 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ADDRESS + Publish configuration for event ADDRESS + 0x30C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ADDRESS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x310 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PAYLOAD + Publish configuration for event PAYLOAD + 0x314 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PAYLOAD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x318 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PHYEND + Publish configuration for event PHYEND + 0x31C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PHYEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DISABLED + Publish configuration for event DISABLED + 0x320 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DISABLED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DEVMATCH + Publish configuration for event DEVMATCH + 0x324 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DEVMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DEVMISS + Publish configuration for event DEVMISS + 0x328 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DEVMISS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CRCOK + Publish configuration for event CRCOK + 0x32C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CRCOK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CRCERROR + Publish configuration for event CRCERROR + 0x330 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CRCERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_BCMATCH + Publish configuration for event BCMATCH + 0x338 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BCMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_EDEND + Publish configuration for event EDEND + 0x33C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event EDEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_EDSTOPPED + Publish configuration for event EDSTOPPED + 0x340 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event EDSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCAIDLE + Publish configuration for event CCAIDLE + 0x344 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCAIDLE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCABUSY + Publish configuration for event CCABUSY + 0x348 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCABUSY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCASTOPPED + Publish configuration for event CCASTOPPED + 0x34C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCASTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RATEBOOST + Publish configuration for event RATEBOOST + 0x350 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RATEBOOST will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_MHRMATCH + Publish configuration for event MHRMATCH + 0x354 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MHRMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SYNC + Publish configuration for event SYNC + 0x358 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SYNC will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CTEPRESENT + Publish configuration for event CTEPRESENT + 0x35C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTEPRESENT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x400 + read-write + 0x00000000 + 0x20 + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 11 + 11 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 15 + 15 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET00 + Enable interrupt + 0x488 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR00 + Disable interrupt + 0x490 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x4A8 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x4B0 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Data rate and modulation + 0x500 + read-write + 0x00000000 + 0x20 + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbps Nordic proprietary radio mode + 0x0 + + + Nrf_2Mbit + 2 Mbps Nordic proprietary radio mode + 0x1 + + + Ble_1Mbit + 1 Mbps BLE + 0x3 + + + Ble_2Mbit + 2 Mbps BLE + 0x4 + + + Ble_LR125Kbit + Long range 125 kbps TX, 125 kbps and 500 kbps RX + 0x5 + + + Ble_LR500Kbit + Long range 500 kbps TX, 125 kbps and 500 kbps RX + 0x6 + + + Nrf_4Mbit_0BT6 + 4 Mbps Nordic proprietary radio mode (BT=0.6/h=0.5) + 0x9 + + + Nrf_4Mbit_0BT4 + 4 Mbps Nordic proprietary radio mode (BT=0.4/h=0.5) + 0xA + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbps + 0xF + + + + + + + STATE + Current radio state + 0x520 + read-only + 0x00000000 + 0x20 + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the DISABLED state + 0x0 + + + RxRu + RADIO is in the RXRU state + 0x1 + + + RxIdle + RADIO is in the RXIDLE state + 0x2 + + + Rx + RADIO is in the RX state + 0x3 + + + RxDisable + RADIO is in the RXDISABLE state + 0x4 + + + TxRu + RADIO is in the TXRU state + 0x9 + + + TxIdle + RADIO is in the TXIDLE state + 0xA + + + Tx + RADIO is in the TX state + 0xB + + + TxDisable + RADIO is in the TXDISABLE state + 0xC + + + + + + + EDCTRL + IEEE 802.15.4 energy detect control + 0x530 + read-write + 0x20000000 + 0x20 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x534 + read-only + 0x00000000 + 0x20 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x538 + read-write + 0x052D0000 + 0x20 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0x0 + + + CarrierMode + Carrier seen + 0x1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 0x2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 0x3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 0x4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + DATAWHITE + Data whitening configuration + 0x540 + read-write + 0x00890040 + 0x20 + + + IV + Whitening initial value + 0 + 8 + + + POLY + Whitening polynomial + 16 + 25 + + + + + TIMING + Timing + 0x704 + read-write + 0x00000001 + 0x20 + + + RU + Ramp-up time + 0 + 0 + + + Legacy + Legacy ramp-up time + 0x0 + + + Fast + Fast ramp-up (default) + 0x1 + + + + + + + FREQUENCY + Frequency + 0x708 + read-write + 0x00000002 + 0x20 + + + FREQUENCY + Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). + 0 + 6 + + + MAP + Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1: Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). + 8 + 8 + + + + + TXPOWER + Output power + 0x710 + read-write + 0x00000013 + 0x20 + + + TXPOWER + RADIO output power + 0 + 10 + + + Pos8dBm + +8 dBm + 0x03F + + + Pos7dBm + +7 dBm + 0x039 + + + Pos6dBm + +6 dBm + 0x033 + + + Pos5dBm + +5 dBm + 0x02D + + + Pos4dBm + +4 dBm + 0x028 + + + Pos3dBm + +3 dBm + 0x023 + + + Pos2dBm + +2 dBm + 0x01F + + + Pos1dBm + +1 dBm + 0x01B + + + 0dBm + 0 dBm + 0x018 + + + Neg1dBm + -1 dBm + 0x015 + + + Neg2dBm + -2 dBm + 0x013 + + + Neg3dBm + -3 dBm + 0x011 + + + Neg4dBm + -4 dBm + 0x00F + + + Neg5dBm + -5 dBm + 0x00D + + + Neg6dBm + -6 dBm + 0x00B + + + Neg7dBm + -7 dBm + 0x00A + + + Neg8dBm + -8 dBm + 0x009 + + + Neg9dBm + -9 dBm + 0x008 + + + Neg10dBm + -10 dBm + 0x007 + + + Neg12dBm + -12 dBm + 0x006 + + + Neg14dBm + -14 dBm + 0x005 + + + Neg16dBm + -16 dBm + 0x004 + + + Neg18dBm + -18 dBm + 0x003 + + + Neg20dBm + -20 dBm + 0x002 + + + Neg22dBm + -22 dBm + 0x002 + + + Neg28dBm + -28 dBm + 0x001 + + + Neg40dBm + -40 dBm + 0x130 + + + Neg46dBm + -46 dBm + 0x110 + + + + + + + TIFS + Interframe spacing in us + 0x714 + read-write + 0x00000000 + 0x20 + + + TIFS + Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet. + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x718 + read-only + 0x0000007F + 0x20 + + + RSSISAMPLE + RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm. + 0 + 6 + + + + + FECONFIG + Config register + 0x908 + read-write + 0x10800005 + 0x20 + + + SCALERMODE + Mode for narrow scaling output. + 20 + 20 + + + Disabled + Classic log based scaling mode. + 0x0 + + + Enabled + LUT based scaling mode. + 0x1 + + + + + + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0xD00 + read-write + 0x00000000 + 0x20 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0x0 + + + AoD + Direction finding mode set to AoD + 0x2 + + + AoA + Direction finding mode set to AoA + 0x3 + + + + + + + DFESTATUS + DFE status information + 0xD04 + read-only + 0x00000000 + 0x20 + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0x0 + + + Offset + Switching state Offset + 0x1 + + + Guard + Switching state Guard + 0x2 + + + Ref + Switching state Ref + 0x3 + + + Switching + Switching state Switching + 0x4 + + + Ending + Switching state Ending + 0x5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0x0 + + + Sampling + Sampling state Sampling + 0x1 + + + + + + + DFECTRL1 + Various configuration for Direction finding + 0xD10 + read-write + 0x00023282 + 0x20 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 0x1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0x0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0x0 + + + MagPhase + Complex samples as magnitude and phase + 0x1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + REPEATPATTERN + Repeat every antenna pattern N times. + 20 + 23 + + + NoRepeat + Do not repeat (1 time in total) + 0x0 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0xD14 + read-write + 0x00000000 + 0x20 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16M cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0xD28 + read-write + 0x00000000 + 0x20 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0xD2C + write-only + 0x00000000 + 0x20 + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor IRQ + 0 + 0 + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0xD30 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0xD50 + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + 0x00004000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 15 + + + + + + CRCSTATUS + CRC status + 0xE0C + read-only + 0x00000000 + 0x20 + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0x0 + + + CRCOk + Packet received with CRC ok + 0x1 + + + + + + + RXMATCH + Received address + 0xE10 + read-only + 0x00000000 + 0x20 + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0xE14 + read-only + 0x00000000 + 0x20 + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0xE18 + read-only + 0x00000000 + 0x20 + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0xE1C + read-only + 0x00000000 + 0x20 + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0x0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 0x1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125 kbps + 0x0 + + + LR500kbit + Frame is received at 500 kbps + 0x1 + + + + + + + PCNF0 + Packet configuration register 0 + 0xE20 + read-write + 0x00000000 + 0x20 + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 21 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0x0 + + + Include + Always include S1 field in RAM independent of S1LEN + 0x1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0x0 + + + 16bit + 16-bit preamble + 0x1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 0x2 + + + LongRange + Preamble - used for BLE long range + 0x3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0x0 + + + Include + LENGTH includes CRC + 0x1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0xE28 + read-write + 0x00000000 + 0x20 + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0x0 + + + Big + Most significant bit on air first + 0x1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WHITEOFFSET + If whitening is enabled S0 can be configured to be excluded from whitening + 26 + 26 + + + Include + S0 included in whitening + 0x0 + + + Exclude + S0 excluded from whitening + 0x1 + + + + + + + BASE0 + Base address 0 + 0xE2C + read-write + 0x00000000 + 0x20 + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0xE30 + read-write + 0x00000000 + 0x20 + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0xE34 + read-write + 0x00000000 + 0x20 + + + AP0 + Address prefix 0 + 0 + 7 + + + AP1 + Address prefix 1 + 8 + 15 + + + AP2 + Address prefix 2 + 16 + 23 + + + AP3 + Address prefix 3 + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0xE38 + read-write + 0x00000000 + 0x20 + + + AP4 + Address prefix 4 + 0 + 7 + + + AP5 + Address prefix 5 + 8 + 15 + + + AP6 + Address prefix 6 + 16 + 23 + + + AP7 + Address prefix 7 + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0xE3C + read-write + 0x00000000 + 0x20 + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0xE40 + read-write + 0x00000000 + 0x20 + + + ADDR0 + Enable or disable reception on logical address 0 + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR1 + Enable or disable reception on logical address 1 + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR2 + Enable or disable reception on logical address 2 + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR3 + Enable or disable reception on logical address 3 + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR4 + Enable or disable reception on logical address 4 + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR5 + Enable or disable reception on logical address 5 + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR6 + Enable or disable reception on logical address 6 + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR7 + Enable or disable reception on logical address 7 + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CRCCNF + CRC configuration + 0xE44 + read-write + 0x00000000 + 0x20 + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0x0 + + + One + CRC length is one byte and CRC calculation is enabled + 0x1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 0x2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 0x3 + + + + + SKIPADDR + Control whether CRC calculation skips the address field. Other fields can also be skipped. + 8 + 10 + + + Include + CRC calculation includes address field + 0x0 + + + Skip + CRC calculation starting at first byte after address field. + 0x1 + + + Ieee802154 + CRC calculation starting at first byte after length field (as per 802.15.4 standard). + 0x2 + + + SkipS0 + CRC calculation starting at first byte after S0 field. + 0x3 + + + SkipS1 + CRC calculation starting at first byte after S1 field. + 0x4 + + + + + + + CRCPOLY + CRC polynomial + 0xE48 + read-write + 0x00000000 + 0x20 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0xE4C + read-write + 0x00000000 + 0x20 + + + CRCINIT + CRC initial value + 0 + 23 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0xE50 + read-write + 0x00000000 + 0x20 + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0xE70 + read-write + 0x00000000 + 0x20 + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0xE90 + read-write + 0x00000000 + 0x20 + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + BCC + Bit counter compare + 0xE94 + read-write + 0x00000000 + 0x20 + + + BCC + Bit counter compare + 0 + 31 + + + + + CTESTATUS + CTEInfo parsed from received packet + 0xEA4 + read-only + 0x00000000 + 0x20 + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + MHRMATCHCONF + Search pattern configuration + 0xEB4 + read-write + 0x00000000 + 0x20 + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMASK + Pattern mask + 0xEB8 + read-write + 0x00000000 + 0x20 + + + MHRMATCHMASK + Pattern mask + 0 + 31 + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0xEBC + read-write + 0x000000A7 + 0x20 + + + SFD + IEEE 802.15.4 start of frame delimiter. Note: the least significant 4 bits of the SFD cannot all be zeros. + 0 + 7 + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0xEC0 + read-write + 0x00002800 + 0x20 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 0x1 + + + Disabled + Parsing of CTEInfo is disabled + 0x0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 0x1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0x0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 0x1 + + + No + No sampling and antenna switching when CRC is not OK + 0x0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 0x0 + + + 31 + 31 in 8us unit + 0x1 + + + 63 + 63 in 8us unit + 0x2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 10 + 12 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 13 + 15 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + PACKETPTR + Packet pointer + 0xED0 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + CSTONES + Unspecified + RADIO_CSTONES + read-write + 0x1000 + + MODE + Selects the mode(s) that are activated on the start signal + 0x000 + read-write + 0x00000003 + 0x20 + + + TPM + Enable or disable TPM + 0 + 0 + + + Disabled + TPM is disabled + 0x0 + + + Enabled + TPM is enabled + 0x1 + + + + + TFM + Enable or disable TFM + 1 + 1 + + + Disabled + TFM is disabled + 0x0 + + + Enabled + TFM is enabled + 0x1 + + + + + + + NUMSAMPLES + Number of input samples at 2MHz sample rate + 0x004 + read-write + 0x000000A0 + 0x20 + + + NUMSAMPLES + Maximum value supported is 160 + 0 + 7 + + + + + NEXTFREQUENCY + The value of FREQUENCY that will be used in the next step + 0x008 + read-write + 0x00000000 + 0x20 + + + NEXTFREQUENCY + Frequency = 2400 + FREQUENCY (MHz) + 0 + 6 + + + + + FFOIN + Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived from CnAcc (autocorrelation of the scaled input signal) value + 0x00C + read-write + 0x00000000 + 0x20 + + + FFFIN + Units 62.5 ppb. Max range +/-100 ppm plus margin. + 0 + 11 + + + + + FFOSOURCE + Source of FFO + 0x010 + read-write + 0x00000001 + 0x20 + + + FFOSOURCE + Use external or internal FFOSOURCE + 0 + 0 + + + External + Use FFOIN + 0x0 + + + Internal + Calc FFO from CnAcc + 0x1 + + + + + + + FAEPEER + FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. + 0x014 + read-write + 0x00000000 + 0x20 + + + FAEPEER + Units 31.25 ppb. + 0 + 7 + + + + + PHASESHIFT + Parameter used in TPM, provided by software + 0x018 + read-write + 0x00000000 + 0x20 + + + PHASESHIFT + Phase shift used in TPM calculation + 0 + 15 + + + + + NUMSAMPLESCOEFF + Parameter used in TPM, provided by software + 0x01C + read-write + 0x0000199A + 0x20 + + + NUMSAMPLESCOEFF + Coefficient 2**16/(numSamples/16) in Q1.15 format (Default numsamples value is 160) + 0 + 15 + + + + + PCT16 + Mean magnitude and mean phase converted to IQ + 0x020 + read-only + 0x00000000 + 0x20 + + + PCT16I + Inphase + 0 + 15 + + + PCT16Q + Quadrature + 16 + 31 + + + + + MAGPHASEMEAN + Mean magnitude and phase of the signal before it is converted to PCT16 + 0x024 + read-only + 0x00000000 + 0x20 + + + PHASE + Mean phase + 0 + 15 + + + MAG + Mean magnitude + 16 + 31 + + + + + IQRAWMEAN + Mean of IQ values + 0x028 + read-only + 0x00000000 + 0x20 + + + IQRAWMEANI + Inphase + 0 + 15 + + + IQRAWMEANQ + Quadrature + 16 + 31 + + + + + MAGSTD + Magnitude standard deviation approximation + 0x02C + read-only + 0x00000000 + 0x20 + + + MAGSTD + Magnitude standard deviation approximation + 0 + 15 + + + + + CNACC + Output of the autocorrelation of the accumulated IQ signal + 0x030 + read-only + 0x00000000 + 0x20 + + + CNACCI + 0 + 15 + + + CNACCQ + 16 + 31 + + + + + FFOEST + FFO estimate + 0x034 + read-only + 0x00000000 + 0x20 + + + FFOEST + Units 62.5 ppb. Max range +/-100 ppm plus margin. + 0 + 11 + + + + + DOWNSAMPLE + Turn on/off down sample of input IQ-signals + 0x038 + read-write + 0x00000000 + 0x20 + + + ENABLEFILTER + Turn on/off down sample of input IQ-signals + 0 + 0 + + + OFF + Disable filter + 0x0 + + + ON + Enable filter + 0x1 + + + + + RATE + Indicating if BLE1M or BLE2M is used + 1 + 1 + + + BLE1M + Radio mode BLE1M is used + 0x0 + + + BLE2m + Radio mode BLE2M is used + 0x1 + + + + + + + FINETUNENEXT + Number of full ADPLL finetune steps + 0x03C + read-only + 0x00000000 + 0x20 + + + FINETUNENEXT + Units of 488.28125 Hz + 0 + 12 + + + + + CFOPHASE + Cordic output of CnAcc + 0x040 + read-only + 0x00000000 + 0x20 + + + CFOPHASE + 0 + 15 + + + + + FREQOFFSET + Frequency offset estimate + 0x044 + read-only + 0x00000000 + 0x20 + + + FREQOFFSET + 0 + 13 + + + + + PCT11 + Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. + 0x048 + read-only + 0x00000000 + 0x20 + + + PCT11I + Inphase + 0 + 10 + + + PCT11Q + Quadrature + 11 + 21 + + + + + LFAENEXT + Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values limited to [-64,63] with units 7.6294 Hz. + 0x04C + read-only + 0x00000000 + 0x20 + + + LFAENEXT + Inphase + 0 + 6 + + + + + + RTT + Unspecified + RADIO_RTT + read-write + 0x1050 + + CONFIG + RTT Config. + 0x0000 + read-write + 0x00000000 + 0x20 + + + EN + Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode + 0 + 0 + + + Disabled + Disable RTT Block + 0x0 + + + Enabled + Enable RTT Block + 0x1 + + + + + ENFULLAA + Enabling/Disable ping over the entire access address. + 1 + 1 + + + Disabled + Disable ping over the entire access address, i.e., enable only over the first 16-bit access address + 0x0 + + + Enabled + Enable ping over the entire access address + 0x1 + + + + + ROLE + Role as a Initiator or Reflector. + 2 + 2 + + + Initiator + Initiator + 0x0 + + + Reflector + Reflector + 0x1 + + + + + NUMSEGMENTS + Number of 16bit payload segments available for ToA detection. Allowed values are 0, 2, 4, 6 and 8. + 3 + 6 + + + EFSDELAY + Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For 2MBPSBLE mode, the EFSDELAY value is 64 (2us) and for 1MBPSBLE mode, it can be 256 (8us). + 8 + 16 + + + + + SEGMENT01 + RTT segments 0 and 1 + 0x0004 + read-write + 0x00000000 + 0x20 + + + DATA + Data Bits 31 - 0 + 0 + 31 + + + + + SEGMENT23 + RTT segments 2 and 3 + 0x0008 + read-write + 0x00000000 + 0x20 + + + DATA + Data Bits 63 - 32 + 0 + 31 + + + + + SEGMENT45 + RTT segments 4 and 5 + 0x000C + read-write + 0x00000000 + 0x20 + + + DATA + Data Bits 95 - 64 + 0 + 31 + + + + + SEGMENT67 + RTT segments 6 and 7 + 0x0010 + read-write + 0x00000000 + 0x20 + + + DATA + Data Bits 127 - 96 + 0 + 31 + + + + + + + + GLOBAL_RADIO_S + 2.4 GHz radio 1 + 0x5008A000 + + + + RADIO_0 + 138 + + + RADIO_1 + 139 + + + + GLOBAL_SPU20_S + System protection unit 2 + 0x500C0000 + + + + SPU20 + 192 + + + + GLOBAL_DPPIC20_NS + Distributed programmable peripheral interconnect controller 4 + 0x400C2000 + + + + + + GLOBAL_DPPIC20_S + Distributed programmable peripheral interconnect controller 5 + 0x500C2000 + + + + + + GLOBAL_PPIB20_NS + PPIB APB registers 8 + 0x400C3000 + + + + + GLOBAL_PPIB20_S + PPIB APB registers 9 + 0x500C3000 + + + + + GLOBAL_PPIB21_NS + PPIB APB registers 10 + 0x400C4000 + + + + + GLOBAL_PPIB21_S + PPIB APB registers 11 + 0x500C4000 + + + + + GLOBAL_PPIB22_NS + PPIB APB registers 12 + 0x400C5000 + + + + + GLOBAL_PPIB22_S + PPIB APB registers 13 + 0x500C5000 + + + + + GLOBAL_SPIM20_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x400C6000 + + + + SERIAL20 + 198 + + + + GLOBAL_SPIS20_NS + SPI Slave 2 + 0x400C6000 + GLOBAL_SPIM20_NS + + + + SERIAL20 + 198 + + + + GLOBAL_TWIM20_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x400C6000 + GLOBAL_SPIM20_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL20 + 198 + + TWIM + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + TWIM_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + TWIM_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + LASTTX_DMA_RX_START + Shortcut between event LASTTX and task DMA.RX.START + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_DMA_TX_START + Shortcut between event LASTRX and task DMA.TX.START + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIM_DMA + read-write + 0x700 + + RX + Unspecified + TWIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x20000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_TWIS20_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x400C6000 + GLOBAL_SPIM20_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL20 + 198 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIS_TASKS_DMA + write-only + 0x030 + + RX + Peripheral tasks. + TWIS_TASKS_DMA_RX + write-only + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA + read-write + 0x0B0 + + RX + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA_RX + read-write + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + 0x20 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + 0x20 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIS_DMA + read-write + 0x700 + + RX + Unspecified + TWIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE20_NS + UART with EasyDMA 2 + 0x400C6000 + GLOBAL_SPIM20_NS + + + + SERIAL20 + 198 + + + + GLOBAL_SPIM20_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x500C6000 + + + + SERIAL20 + 198 + + + + GLOBAL_SPIS20_S + SPI Slave 3 + 0x500C6000 + GLOBAL_SPIM20_S + + + + SERIAL20 + 198 + + + + GLOBAL_TWIM20_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x500C6000 + GLOBAL_SPIM20_S + + + + SERIAL20 + 198 + + + + GLOBAL_TWIS20_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x500C6000 + GLOBAL_SPIM20_S + + + + SERIAL20 + 198 + + + + GLOBAL_UARTE20_S + UART with EasyDMA 3 + 0x500C6000 + GLOBAL_SPIM20_S + + + + SERIAL20 + 198 + + + + GLOBAL_SPIM21_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x400C7000 + + + + SERIAL21 + 199 + + + + GLOBAL_SPIS21_NS + SPI Slave 4 + 0x400C7000 + GLOBAL_SPIM21_NS + + + + SERIAL21 + 199 + + + + GLOBAL_TWIM21_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x400C7000 + GLOBAL_SPIM21_NS + + + + SERIAL21 + 199 + + + + GLOBAL_TWIS21_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x400C7000 + GLOBAL_SPIM21_NS + + + + SERIAL21 + 199 + + + + GLOBAL_UARTE21_NS + UART with EasyDMA 4 + 0x400C7000 + GLOBAL_SPIM21_NS + + + + SERIAL21 + 199 + + + + GLOBAL_SPIM21_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x500C7000 + + + + SERIAL21 + 199 + + + + GLOBAL_SPIS21_S + SPI Slave 5 + 0x500C7000 + GLOBAL_SPIM21_S + + + + SERIAL21 + 199 + + + + GLOBAL_TWIM21_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x500C7000 + GLOBAL_SPIM21_S + + + + SERIAL21 + 199 + + + + GLOBAL_TWIS21_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x500C7000 + GLOBAL_SPIM21_S + + + + SERIAL21 + 199 + + + + GLOBAL_UARTE21_S + UART with EasyDMA 5 + 0x500C7000 + GLOBAL_SPIM21_S + + + + SERIAL21 + 199 + + + + GLOBAL_SPIM22_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x400C8000 + + + + SERIAL22 + 200 + + + + GLOBAL_SPIS22_NS + SPI Slave 6 + 0x400C8000 + GLOBAL_SPIM22_NS + + + + SERIAL22 + 200 + + + + GLOBAL_TWIM22_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x400C8000 + GLOBAL_SPIM22_NS + + + + SERIAL22 + 200 + + + + GLOBAL_TWIS22_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x400C8000 + GLOBAL_SPIM22_NS + + + + SERIAL22 + 200 + + + + GLOBAL_UARTE22_NS + UART with EasyDMA 6 + 0x400C8000 + GLOBAL_SPIM22_NS + + + + SERIAL22 + 200 + + + + GLOBAL_SPIM22_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x500C8000 + + + + SERIAL22 + 200 + + + + GLOBAL_SPIS22_S + SPI Slave 7 + 0x500C8000 + GLOBAL_SPIM22_S + + + + SERIAL22 + 200 + + + + GLOBAL_TWIM22_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x500C8000 + GLOBAL_SPIM22_S + + + + SERIAL22 + 200 + + + + GLOBAL_TWIS22_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x500C8000 + GLOBAL_SPIM22_S + + + + SERIAL22 + 200 + + + + GLOBAL_UARTE22_S + UART with EasyDMA 7 + 0x500C8000 + GLOBAL_SPIM22_S + + + + SERIAL22 + 200 + + + + GLOBAL_EGU20_NS + Event generator unit 2 + 0x400C9000 + + + + EGU20 + 201 + + + + GLOBAL_EGU20_S + Event generator unit 3 + 0x500C9000 + + + + EGU20 + 201 + + + + GLOBAL_TIMER20_NS + Timer/Counter 4 + 0x400CA000 + + + + TIMER20 + 202 + + + + GLOBAL_TIMER20_S + Timer/Counter 5 + 0x500CA000 + + + + TIMER20 + 202 + + + + GLOBAL_TIMER21_NS + Timer/Counter 6 + 0x400CB000 + + + + TIMER21 + 203 + + + + GLOBAL_TIMER21_S + Timer/Counter 7 + 0x500CB000 + + + + TIMER21 + 203 + + + + GLOBAL_TIMER22_NS + Timer/Counter 8 + 0x400CC000 + + + + TIMER22 + 204 + + + + GLOBAL_TIMER22_S + Timer/Counter 9 + 0x500CC000 + + + + TIMER22 + 204 + + + + GLOBAL_TIMER23_NS + Timer/Counter 10 + 0x400CD000 + + + + TIMER23 + 205 + + + + GLOBAL_TIMER23_S + Timer/Counter 11 + 0x500CD000 + + + + TIMER23 + 205 + + + + GLOBAL_TIMER24_NS + Timer/Counter 12 + 0x400CE000 + + + + TIMER24 + 206 + + + + GLOBAL_TIMER24_S + Timer/Counter 13 + 0x500CE000 + + + + TIMER24 + 206 + + + + GLOBAL_MEMCONF_NS + Memory configuration 0 + 0x400CF000 + MEMCONF + + + + 0 + 0x1000 + registers + + MEMCONF + 0x20 + + + 2 + 0x010 + POWER[%s] + Unspecified + MEMCONF_POWER + read-write + 0x500 + + CONTROL + Description cluster: Control memory block power. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MEM0 + Keep the memory block MEM[0] on or off when in System ON mode. + 0 + 0 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM1 + Keep the memory block MEM[1] on or off when in System ON mode. + 1 + 1 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM2 + Keep the memory block MEM[2] on or off when in System ON mode. + 2 + 2 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM3 + Keep the memory block MEM[3] on or off when in System ON mode. + 3 + 3 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM4 + Keep the memory block MEM[4] on or off when in System ON mode. + 4 + 4 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM5 + Keep the memory block MEM[5] on or off when in System ON mode. + 5 + 5 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM6 + Keep the memory block MEM[6] on or off when in System ON mode. + 6 + 6 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM7 + Keep the memory block MEM[7] on or off when in System ON mode. + 7 + 7 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM8 + Keep the memory block MEM[8] on or off when in System ON mode. + 8 + 8 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM9 + Keep the memory block MEM[9] on or off when in System ON mode. + 9 + 9 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM10 + Keep the memory block MEM[10] on or off when in System ON mode. + 10 + 10 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM11 + Keep the memory block MEM[11] on or off when in System ON mode. + 11 + 11 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM12 + Keep the memory block MEM[12] on or off when in System ON mode. + 12 + 12 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM13 + Keep the memory block MEM[13] on or off when in System ON mode. + 13 + 13 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM14 + Keep the memory block MEM[14] on or off when in System ON mode. + 14 + 14 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM15 + Keep the memory block MEM[15] on or off when in System ON mode. + 15 + 15 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM16 + Keep the memory block MEM[16] on or off when in System ON mode. + 16 + 16 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM17 + Keep the memory block MEM[17] on or off when in System ON mode. + 17 + 17 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM18 + Keep the memory block MEM[18] on or off when in System ON mode. + 18 + 18 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM19 + Keep the memory block MEM[19] on or off when in System ON mode. + 19 + 19 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM20 + Keep the memory block MEM[20] on or off when in System ON mode. + 20 + 20 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM21 + Keep the memory block MEM[21] on or off when in System ON mode. + 21 + 21 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM22 + Keep the memory block MEM[22] on or off when in System ON mode. + 22 + 22 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM23 + Keep the memory block MEM[23] on or off when in System ON mode. + 23 + 23 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM24 + Keep the memory block MEM[24] on or off when in System ON mode. + 24 + 24 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM25 + Keep the memory block MEM[25] on or off when in System ON mode. + 25 + 25 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM26 + Keep the memory block MEM[26] on or off when in System ON mode. + 26 + 26 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM27 + Keep the memory block MEM[27] on or off when in System ON mode. + 27 + 27 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM28 + Keep the memory block MEM[28] on or off when in System ON mode. + 28 + 28 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM29 + Keep the memory block MEM[29] on or off when in System ON mode. + 29 + 29 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM30 + Keep the memory block MEM[30] on or off when in System ON mode. + 30 + 30 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM31 + Keep the memory block MEM[31] on or off when in System ON mode. + 31 + 31 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + + + RET + Description cluster: RAM retention for RAM [n]. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + MEM0 + Keep the RAM block MEM[0] retained when in System OFF mode. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the RAM block MEM[1] retained when in System OFF mode. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the RAM block MEM[2] retained when in System OFF mode. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the RAM block MEM[3] retained when in System OFF mode. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the RAM block MEM[4] retained when in System OFF mode. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the RAM block MEM[5] retained when in System OFF mode. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the RAM block MEM[6] retained when in System OFF mode. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the RAM block MEM[7] retained when in System OFF mode. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the RAM block MEM[8] retained when in System OFF mode. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the RAM block MEM[9] retained when in System OFF mode. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the RAM block MEM[10] retained when in System OFF mode. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the RAM block MEM[11] retained when in System OFF mode. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the RAM block MEM[12] retained when in System OFF mode. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the RAM block MEM[13] retained when in System OFF mode. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the RAM block MEM[14] retained when in System OFF mode. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the RAM block MEM[15] retained when in System OFF mode. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the RAM block MEM[16] retained when in System OFF mode. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the RAM block MEM[17] retained when in System OFF mode. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the RAM block MEM[18] retained when in System OFF mode. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the RAM block MEM[19] retained when in System OFF mode. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the RAM block MEM[20] retained when in System OFF mode. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the RAM block MEM[21] retained when in System OFF mode. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the RAM block MEM[22] retained when in System OFF mode. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the RAM block MEM[23] retained when in System OFF mode. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the RAM block MEM[24] retained when in System OFF mode. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the RAM block MEM[25] retained when in System OFF mode. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the RAM block MEM[26] retained when in System OFF mode. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the RAM block MEM[27] retained when in System OFF mode. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the RAM block MEM[28] retained when in System OFF mode. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the RAM block MEM[29] retained when in System OFF mode. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the RAM block MEM[30] retained when in System OFF mode. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the RAM block MEM[31] retained when in System OFF mode. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + RET2 + Description cluster: RAM retention for the second bank in the RAM block + 0x00C + read-write + 0x00000000 + 0x20 + + + MEM0 + Keep the second bank in RAM block MEM[0] retained when in System OFF mode. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the second bank in RAM block MEM[1] retained when in System OFF mode. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the second bank in RAM block MEM[2] retained when in System OFF mode. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the second bank in RAM block MEM[3] retained when in System OFF mode. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the second bank in RAM block MEM[4] retained when in System OFF mode. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the second bank in RAM block MEM[5] retained when in System OFF mode. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the second bank in RAM block MEM[6] retained when in System OFF mode. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the second bank in RAM block MEM[7] retained when in System OFF mode. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the second bank in RAM block MEM[8] retained when in System OFF mode. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the second bank in RAM block MEM[9] retained when in System OFF mode. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the second bank in RAM block MEM[10] retained when in System OFF mode. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the second bank in RAM block MEM[11] retained when in System OFF mode. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the second bank in RAM block MEM[12] retained when in System OFF mode. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the second bank in RAM block MEM[13] retained when in System OFF mode. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the second bank in RAM block MEM[14] retained when in System OFF mode. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the second bank in RAM block MEM[15] retained when in System OFF mode. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the second bank in RAM block MEM[16] retained when in System OFF mode. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the second bank in RAM block MEM[17] retained when in System OFF mode. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the second bank in RAM block MEM[18] retained when in System OFF mode. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the second bank in RAM block MEM[19] retained when in System OFF mode. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the second bank in RAM block MEM[20] retained when in System OFF mode. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the second bank in RAM block MEM[21] retained when in System OFF mode. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the second bank in RAM block MEM[22] retained when in System OFF mode. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the second bank in RAM block MEM[23] retained when in System OFF mode. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the second bank in RAM block MEM[24] retained when in System OFF mode. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the second bank in RAM block MEM[25] retained when in System OFF mode. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the second bank in RAM block MEM[26] retained when in System OFF mode. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the second bank in RAM block MEM[27] retained when in System OFF mode. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the second bank in RAM block MEM[28] retained when in System OFF mode. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the second bank in RAM block MEM[29] retained when in System OFF mode. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the second bank in RAM block MEM[30] retained when in System OFF mode. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the second bank in RAM block MEM[31] retained when in System OFF mode. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + + + + GLOBAL_MEMCONF_S + Memory configuration 1 + 0x500CF000 + + + + + GLOBAL_PDM20_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x400D0000 + PDM + + + + 0 + 0x1000 + registers + + + PDM20 + 208 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PDM_EVENTS_DMA + read-write + 0x110 + + BUSERROR + This event is generated if an error occurs during the bus transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + This event is generated if an error occurs during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PDM_PUBLISH_DMA + read-write + 0x190 + + BUSERROR + Publish configuration for event DMA.BUSERROR + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DMA.BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMABUSERROR + Enable or disable interrupt for event DMABUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMABUSERROR + Write '1' to enable interrupt for event DMABUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMABUSERROR + Write '1' to disable interrupt for event DMABUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STARTED + Read pending status of interrupt for event STARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + END + Read pending status of interrupt for event END + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMABUSERROR + Read pending status of interrupt for event DMABUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Defines the routing of the connected PDM microphone signals + 0x508 + read-write + 0x00000000 + 0x20 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled. + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate. Change PRESCALER accordingly. + 0x520 + read-write + 0x00000002 + 0x20 + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate + 0 + 2 + + + Ratio32 + Ratio of 32 + 0x0 + + + Ratio48 + Ratio of 48 + 0x1 + + + Ratio50 + Ratio of 50 + 0x2 + + + Ratio64 + Ratio of 64 + 0x3 + + + Ratio80 + Ratio of 80 + 0x4 + + + Ratio96 + Ratio of 96 + 0x5 + + + Ratio100 + Ratio of 100 + 0x6 + + + Ratio128 + Ratio of 128 + 0x7 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + 0x20 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + 0x20 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + PRESCALER + The prescaler is used to set the PDM frequency + 0x580 + read-write + 0x00000004 + 0x20 + + + DIVISOR + Core clock to PDM divisor + 0 + 31 + + + + + DMA + Unspecified + PDM_DMA + read-write + 0x700 + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x004 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_PDM20_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x500D0000 + + + + PDM20 + 208 + + + + GLOBAL_PDM21_NS + Pulse Density Modulation (Digital Microphone) Interface 2 + 0x400D1000 + + + + PDM21 + 209 + + + + GLOBAL_PDM21_S + Pulse Density Modulation (Digital Microphone) Interface 3 + 0x500D1000 + + + + PDM21 + 209 + + + + GLOBAL_PWM20_NS + Pulse width modulation unit 0 + 0x400D2000 + PWM + + + + 0 + 0x1000 + registers + + + PWM20 + 210 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + PWM_TASKS_DMA + write-only + 0x010 + + 2 + 0x008 + SEQ[%s] + Peripheral tasks. + PWM_TASKS_DMA_SEQ + write-only + 0x000 + + START + Description cluster: Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA + read-write + 0x090 + + 2 + 0x008 + SEQ[%s] + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA_SEQ + read-write + 0x000 + + START + Description cluster: Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PWM_EVENTS_DMA + read-write + 0x124 + + 2 + 0x00C + SEQ[%s] + Peripheral events. + PWM_EVENTS_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + Description cluster: An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + 0x4 + 0x4 + EVENTS_COMPAREMATCH[%s] + Description collection: This event is generated when the compare matches for the compare channel [n]. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPAREMATCH + This event is generated when the compare matches for the compare channel [n]. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RAMUNDERFLOW + Publish configuration for event RAMUNDERFLOW + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RAMUNDERFLOW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PWM_PUBLISH_DMA + read-write + 0x1A4 + + 2 + 0x00C + SEQ[%s] + Publish configuration for events + PWM_PUBLISH_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Description cluster: Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Description cluster: Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + 0x4 + 0x4 + PUBLISH_COMPAREMATCH[%s] + Description collection: Publish configuration for event COMPAREMATCH[n] + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPAREMATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + SEQEND0_STOP + Shortcut between event SEQEND[n] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[n] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RAMUNDERFLOW_STOP + Shortcut between event RAMUNDERFLOW and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ0_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ1_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RAMUNDERFLOW + Enable or disable interrupt for event RAMUNDERFLOW + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0END + Enable or disable interrupt for event DMASEQ0END + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0READY + Enable or disable interrupt for event DMASEQ0READY + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Enable or disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1END + Enable or disable interrupt for event DMASEQ1END + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1READY + Enable or disable interrupt for event DMASEQ1READY + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Enable or disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH0 + Enable or disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH1 + Enable or disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH2 + Enable or disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH3 + Enable or disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to enable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0END + Write '1' to enable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0READY + Write '1' to enable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to enable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1END + Write '1' to enable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1READY + Write '1' to enable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to enable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to enable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to enable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to enable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to enable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to disable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0END + Write '1' to disable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0READY + Write '1' to disable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1END + Write '1' to disable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1READY + Write '1' to disable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED0 + Read pending status of interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED1 + Read pending status of interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND0 + Read pending status of interrupt for event SEQEND[0] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND1 + Read pending status of interrupt for event SEQEND[1] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LOOPSDONE + Read pending status of interrupt for event LOOPSDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RAMUNDERFLOW + Read pending status of interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0END + Read pending status of interrupt for event DMASEQ0END + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0READY + Read pending status of interrupt for event DMASEQ0READY + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0BUSERROR + Read pending status of interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1END + Read pending status of interrupt for event DMASEQ1END + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1READY + Read pending status of interrupt for event DMASEQ1READY + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1BUSERROR + Read pending status of interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH0 + Read pending status of interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH1 + Read pending status of interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH2 + Read pending status of interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH3 + Read pending status of interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + IDLEOUT + Configure the output value on the PWM channel during idle + 0x518 + read-write + 0x00000000 + 0x20 + + + VAL_0 + Idle output value for PWM channel [0] + 0 + 0 + + + VAL_1 + Idle output value for PWM channel [1] + 1 + 1 + + + VAL_2 + Idle output value for PWM channel [2] + 2 + 2 + + + VAL_3 + Idle output value for PWM channel [3] + 3 + 3 + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + PWM_DMA + read-write + 0x700 + + 2 + 0x024 + SEQ[%s] + Unspecified + PWM_DMA_SEQ + read-write + 0x000 + + PTR + Description cluster: RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 15 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + CURRENTAMOUNT + Description cluster: Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 15 + + + + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_PWM20_S + Pulse width modulation unit 1 + 0x500D2000 + + + + PWM20 + 210 + + + + GLOBAL_PWM21_NS + Pulse width modulation unit 2 + 0x400D3000 + + + + PWM21 + 211 + + + + GLOBAL_PWM21_S + Pulse width modulation unit 3 + 0x500D3000 + + + + PWM21 + 211 + + + + GLOBAL_PWM22_NS + Pulse width modulation unit 4 + 0x400D4000 + + + + PWM22 + 212 + + + + GLOBAL_PWM22_S + Pulse width modulation unit 5 + 0x500D4000 + + + + PWM22 + 212 + + + + GLOBAL_SAADC_NS + Analog to Digital Converter 0 + 0x400D5000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 213 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + TRIM + Unspecified + SAADC_TRIM + read-write + 0x440 + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Linearity calibration coefficient + 0x000 + read-write + 0x00000000 + 0x20 + + + VAL + value + 0 + 15 + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x0 + read-write + 0x00000000 + 0x20 + + + PIN + GPIO pin selection. + 0 + 4 + + + PORT + GPIO port selection + 8 + 11 + + + INTERNAL + Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal + 12 + 13 + + + Avdd + Connected to the internal 0.9V analog supply rail + 0x0 + + + Dvdd + Connected to the internal 0.9V digital supply rail + 0x1 + + + Vdd + Connected to VDD + 0x2 + + + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + Internal + Selects internal inputs. + 0x2 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x4 + read-write + 0x00000000 + 0x20 + + + PIN + GPIO pin selection. + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + GAIN + Gain control + 8 + 10 + + + Gain2 + 2 + 0x0 + + + Gain1 + 1 + 0x1 + + + Gain2_3 + 2/3 + 0x2 + + + Gain2_4 + 2/4 + 0x3 + + + Gain2_5 + 2/5 + 0x4 + + + Gain2_6 + 2/6 + 0x5 + + + Gain2_7 + 2/7 + 0x6 + + + Gain2_8 + 2/8 + 0x7 + + + + + BURST + Enable burst mode + 11 + 11 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (1.024 V) + 0x0 + + + External + External reference given at PADC_EXT_REF_1V2 + 0x1 + + + + + MODE + Enable differential mode + 15 + 15 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) + 16 + 24 + + + TCONV + Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) + 28 + 30 + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + 0x20 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x628 + + PTR + Data pointer + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer bytes to transfer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of buffer bytes to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer bytes transferred since last START, updated after the END or STOPPED events + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START, updated after the END or STOPPED events. + 0 + 14 + + + + + CURRENTAMOUNT + Number of buffer bytes transferred since last START, continuously updated + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START, continuously updated. + 0 + 14 + + + + + + NOISESHAPE + Enable noise shaping + 0x654 + read-write + 0x00000000 + 0x20 + + + NOISESHAPE + Enable noise shaping + 0 + 1 + + + Disable + Disable noiseshaping. Oversampling based on accumulate and average. + 0x0 + + + Audio + Noiseshaping and decimating. Larger passband. Provides a 50kS/s cut off frequency, 8x the oversampling ratio. See design description for more information + 0x1 + + + Accuracy + Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bits. Provides a 5kS/s cut off frequency, 32x the oversampling ratio. See design description for more information + 0x2 + + + + + + + + + GLOBAL_SAADC_S + Analog to Digital Converter 1 + 0x500D5000 + + + + SAADC + 213 + + + + GLOBAL_NFCT_NS + NFC-A compatible radio NFC-A compatible radio 0 + 0x400D6000 + NFCT + + + + 0 + 0x1000 + registers + + + NFCT + 214 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DISABLE + Disable NFCT peripheral + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_DISABLE + Disable NFCT peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPTX + Stops an issued transmission of a frame + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPTX + Stops an issued transmission of a frame + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + 0x00000000 + 0x20 + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_ACTIVATE + Subscribe configuration for task ACTIVATE + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACTIVATE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SENSE + Subscribe configuration for task SENSE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SENSE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STARTTX + Subscribe configuration for task STARTTX + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STARTTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOPTX + Subscribe configuration for task STOPTX + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOPTX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_ENABLERXDATA + Subscribe configuration for task ENABLERXDATA + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLERXDATA will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_GOIDLE + Subscribe configuration for task GOIDLE + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task GOIDLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_GOSLEEP + Subscribe configuration for task GOSLEEP + 0x0A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task GOSLEEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + 0x00000000 + 0x20 + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + 0x00000000 + 0x20 + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FIELDDETECTED + Publish configuration for event FIELDDETECTED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FIELDDETECTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FIELDLOST + Publish configuration for event FIELDLOST + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FIELDLOST will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXFRAMESTART + Publish configuration for event TXFRAMESTART + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXFRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXFRAMEEND + Publish configuration for event TXFRAMEEND + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXFRAMEEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXFRAMESTART + Publish configuration for event RXFRAMESTART + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXFRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXFRAMEEND + Publish configuration for event RXFRAMEEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXFRAMEEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXERROR + Publish configuration for event RXERROR + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDRX + Publish configuration for event ENDRX + 0x1AC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ENDRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ENDTX + Publish configuration for event ENDTX + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ENDTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_AUTOCOLRESSTARTED + Publish configuration for event AUTOCOLRESSTARTED + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event AUTOCOLRESSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_COLLISION + Publish configuration for event COLLISION + 0x1C8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COLLISION will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SELECTED + Publish configuration for event SELECTED + 0x1CC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SELECTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x1D0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + 0x00000000 + oneToClear + 0x20 + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + 0x00000000 + oneToClear + 0x20 + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0x0 + + + CRCError + CRC received does not match local check + 0x1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0x0 + + + ParityError + Frame received with parity error + 0x1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0x0 + + + Overrun + Overrun error + 0x1 + + + + + + + + NFCTAGSTATE + Current operating state of NFC tag + 0x410 + read-only + 0x00000000 + 0x20 + + + NFCTAGSTATE + NfcTag state + 0 + 2 + + + Disabled + Disabled or sense + 0x0 + + + RampUp + RampUp + 0x2 + + + Idle + Idle + 0x3 + + + Receive + Receive + 0x4 + + + FrameDelay + FrameDelay + 0x5 + + + Transmit + Transmit + 0x6 + + + + + + + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 + 0x20 + + + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. + 0 + 0 + + + Idle + State is IDLE. + 0x0 + + + SleepA + State is SLEEP_A. + 0x1 + + + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + 0x00000000 + 0x20 + + + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0x0 + + + FieldPresent + Valid field detected + 0x1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0x0 + + + Locked + Locked to field + 0x1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + 0x20 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clock cycles + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + 0x20 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clock cycles + 0 + 19 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + 0x20 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0x0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 0x1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 0x2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 0x3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + 0x20 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write + 0x00000000 + 0x20 + + + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + 0x20 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0x0 + + + Parity + Parity is added to TX frames + 0x1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0x0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 0x1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0x0 + + + SoF + SoF symbol added + 0x1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0x0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 0x1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + 0x00000000 + 0x20 + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + 0x20 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0x0 + + + Parity + Parity is expected in RX frames + 0x1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0x0 + + + SoF + SoF symbol is expected in RX frames + 0x1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0x0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 0x1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + 0x00000000 + 0x20 + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + MODULATIONCTRL + Enables the modulation output to a GPIO pin which can be connected to a second external antenna. + 0x52C + read-write + 0x00000001 + 0x20 + + + MODULATIONCTRL + Configuration of modulation control. + 0 + 1 + + + Invalid + Invalid, defaults to same behaviour as for Internal + 0x0 + + + Internal + Use internal modulator only + 0x1 + + + ModToGpio + Output digital modulation signal to a GPIO pin. + 0x2 + + + InternalAndModToGpio + Use internal modulator and output digital modulation signal to a GPIO pin. + 0x3 + + + + + + + MODULATIONPSEL + Pin select for Modulation control + 0x538 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 6 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MODE + Configure EasyDMA mode + 0x550 + read-write + 0x00000001 + 0x20 + + + LPOP + Enable low-power operation, or use low-latency + 0 + 1 + + + LowLat + Low-latency operation + 0x0 + + + LowPower + Low-power operation + 0x1 + + + FullLowPower + Full Low-power operation + 0x3 + + + + + + + NFCID1 + Unspecified + NFCT_NFCID1 + read-write + 0x590 + + LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x000 + read-write + 0x00006363 + 0x20 + + + Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + Y + NFCID1 byte Y + 8 + 15 + + + X + NFCID1 byte X + 16 + 23 + + + W + NFCID1 byte W + 24 + 31 + + + + + SECONDLAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x004 + read-write + 0x00000000 + 0x20 + + + V + NFCID1 byte V + 0 + 7 + + + U + NFCID1 byte U + 8 + 15 + + + T + NFCID1 byte T + 16 + 23 + + + + + THIRDLAST + Third last NFCID1 part (10 bytes ID) + 0x008 + read-write + 0x00000000 + 0x20 + + + S + NFCID1 byte S + 0 + 7 + + + R + NFCID1 byte R + 8 + 15 + + + Q + NFCID1 byte Q + 16 + 23 + + + + + + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. + 0x59C + read-write + 0x00000002 + 0x20 + + + MODE + Enables/disables auto collision resolution + 0 + 0 + + + Enabled + Auto collision resolution enabled + 0x0 + + + Disabled + Auto collision resolution disabled + 0x1 + + + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + 0x20 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0x00 + + + SDD00001 + SDD pattern 00001 + 0x01 + + + SDD00010 + SDD pattern 00010 + 0x02 + + + SDD00100 + SDD pattern 00100 + 0x04 + + + SDD01000 + SDD pattern 01000 + 0x08 + + + SDD10000 + SDD pattern 10000 + 0x10 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0x0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 0x1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 0x2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + 0x00000000 + 0x20 + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + PADCONFIG + NFC pad configuration + 0x6D4 + read-write + 0x00000001 + 0x20 + + + ENABLE + Enable NFC pads + 0 + 0 + + + Disabled + NFC pads are used as GPIO pins + 0x0 + + + Enabled + The NFC pads are configured as NFC antenna pins + 0x1 + + + + + + + + + GLOBAL_NFCT_S + NFC-A compatible radio NFC-A compatible radio 1 + 0x500D6000 + + + + NFCT + 214 + + + + GLOBAL_TEMP_NS + Temperature Sensor 0 + 0x400D7000 + TEMP + + + + 0 + 0x1000 + registers + + + TEMP + 215 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DATARDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + 0x00000000 + int32_t + 0x20 + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x000002D6 + 0x20 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x0000032D + 0x20 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x00000384 + 0x20 + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x000003E9 + 0x20 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000046F + 0x20 + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x00000522 + 0x20 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + A6 + Slope of 7th piece wise linear function + 0x538 + read-write + 0x000005B7 + 0x20 + + + A6 + Slope of 7th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00000FD6 + 0x20 + + + B0 + y-intercept of 1st piece wise linear function + 0 + 11 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00000F76 + 0x20 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 11 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00000F8A + 0x20 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 11 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000FF8 + 0x20 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 11 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x000000CC + 0x20 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 11 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x00000207 + 0x20 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 11 + + + + + B6 + y-intercept of 7th piece wise linear function + 0x558 + read-write + 0x00000558 + 0x20 + + + B6 + y-intercept of 7th piece wise linear function + 0 + 11 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + 0x20 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000002 + 0x20 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x0000001F + 0x20 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x00000038 + 0x20 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x0000004F + 0x20 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + T5 + End point of 6th piece wise linear function + 0x574 + read-write + 0x00000066 + 0x20 + + + T5 + End point of 6th piece wise linear function + 0 + 7 + + + + + + + GLOBAL_TEMP_S + Temperature Sensor 1 + 0x500D7000 + + + + TEMP + 215 + + + + GLOBAL_P1_NS + GPIO Port 2 + 0x400D8200 + + + + + + GLOBAL_P1_S + GPIO Port 3 + 0x500D8200 + + + + + + GLOBAL_GPIOTE20_NS + GPIO Tasks and Events 0 + 0x400DA000 + GPIOTE + + + + + 0 + 0x1000 + registers + + + GPIOTE20_0 + 218 + + + GPIOTE20_1 + 219 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 1 + 0x008 + EVENTS_PORT[%s] + Peripheral events. + GPIOTE_EVENTS_PORT + read-write + 0x140 + + NONSECURE + Description cluster: Non-secure port event from owner n + 0x000 + read-write + 0x00000000 + 0x20 + + + + NONSECURE + Non-secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SECURE + Description cluster: Secure port event from owner n + 0x004 + read-write + 0x00000000 + 0x20 + + + + SECURE + Secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 1 + 0x008 + PUBLISH_PORT[%s] + Publish configuration for events + GPIOTE_PUBLISH_PORT + read-write + 0x1C0 + + NONSECURE + Description cluster: Publish configuration for event PORT[n].NONSECURE + 0x000 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].NONSECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SECURE + Description cluster: Publish configuration for event PORT[n].SECURE + 0x004 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].SECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + 0x20 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 4 + 8 + + + PORT + Port number + 9 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + GLOBAL_GPIOTE20_S + GPIO Tasks and Events 1 + 0x500DA000 + + + + + GPIOTE20_0 + 218 + + + GPIOTE20_1 + 219 + + + + GLOBAL_TAMPC_S + Tamper controller + 0x500DC000 + TAMPC + + + + 0 + 0x1000 + registers + + + TAMPC + 220 + + TAMPC + 0x20 + + + EVENTS_TAMPER + Tamper controller detected an error. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TAMPER + Tamper controller detected an error. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITEERROR + Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITEERROR + Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TAMPER + Enable or disable interrupt for event TAMPER + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITEERROR + Enable or disable interrupt for event WRITEERROR + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TAMPER + Write '1' to enable interrupt for event TAMPER + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITEERROR + Write '1' to enable interrupt for event WRITEERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TAMPER + Write '1' to disable interrupt for event TAMPER + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITEERROR + Write '1' to disable interrupt for event WRITEERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TAMPER + Read pending status of interrupt for event TAMPER + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + WRITEERROR + Read pending status of interrupt for event WRITEERROR + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + The tamper controller status. + 0x400 + read-write + 0x00000000 + oneToClear + 0x20 + + + ACTIVESHIELD + Active shield detector detected an error. + 0 + 0 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + PROTECT + Error detected for the protected signals. + 4 + 4 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + CRACENTAMP + CRACEN detected an error. + 5 + 5 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + GLITCHSLOWDOMAIN_0 + Slow domain glitch detector 0 detected an error. + 8 + 8 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + GLITCHFASTDOMAIN_0 + Fast domain glitch detector 0 detected an error. + 12 + 12 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + GLITCHFASTDOMAIN_1 + Fast domain glitch detector 1 detected an error. + 13 + 13 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + GLITCHFASTDOMAIN_2 + Fast domain glitch detector 2 detected an error. + 14 + 14 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + GLITCHFASTDOMAIN_3 + Fast domain glitch detector 3 detected an error. + 15 + 15 + + + NotDetected + Not detected. + 0x0 + + + Detected + Detected. + 0x1 + + + + + + + ACTIVESHIELD + Unspecified + TAMPC_ACTIVESHIELD + read-write + 0x404 + + CHEN + Active shield detector channel enable register. + 0x000 + read-write + 0x00000000 + 0x20 + + + CH_0 + Enable or disable active shield channel 0. + 0 + 0 + + + Disabled + Disable channel. + 0x0 + + + Enabled + Enable channel. + 0x1 + + + + + CH_1 + Enable or disable active shield channel 1. + 1 + 1 + + + Disabled + Disable channel. + 0x0 + + + Enabled + Enable channel. + 0x1 + + + + + CH_2 + Enable or disable active shield channel 2. + 2 + 2 + + + Disabled + Disable channel. + 0x0 + + + Enabled + Enable channel. + 0x1 + + + + + CH_3 + Enable or disable active shield channel 3. + 3 + 3 + + + Disabled + Disable channel. + 0x0 + + + Enabled + Enable channel. + 0x1 + + + + + + + + PROTECT + Unspecified + TAMPC_PROTECT + read-write + 0x500 + + 1 + 0x020 + DOMAIN[%s] + Unspecified + TAMPC_PROTECT_DOMAIN + read-write + 0x000 + + DBGEN + Unspecified + TAMPC_PROTECT_DOMAIN_DBGEN + read-write + 0x000 + + CTRL + Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of dbgen signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Description cluster: Status register for invasive (halting) debug enable for domain n. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + NIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_NIDEN + read-write + 0x008 + + CTRL + Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of niden signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Description cluster: Status register for non-invasive debug enable for domain n. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + SPIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPIDEN + read-write + 0x010 + + CTRL + Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of spiden signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + SPNIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPNIDEN + read-write + 0x018 + + CTRL + Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of spniden signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + + 1 + 0x010 + AP[%s] + Unspecified + TAMPC_PROTECT_AP + read-write + 0x200 + + DBGEN + Unspecified + TAMPC_PROTECT_AP_DBGEN + read-write + 0x000 + + CTRL + Description cluster: Control register to enable invasive (halting) debug in domain n's access port. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of dbgen signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Description cluster: Status register for invasive (halting) debug enable for domain n's access port. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + + ACTIVESHIELD + Enable active shield detector. + TAMPC_PROTECT_ACTIVESHIELD + read-write + 0x400 + + CTRL + Control register for active shield detector enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of active shield enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for active shield detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + CRACENTAMP + Enable tamper detector from CRACEN. + TAMPC_PROTECT_CRACENTAMP + read-write + 0x438 + + CTRL + Control register for CRACEN tamper detector enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of CRACEN tamper detector enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for CRACEN tamper detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHSLOWDOMAIN + Enable slow domain glitch detectors. + TAMPC_PROTECT_GLITCHSLOWDOMAIN + read-write + 0x440 + + CTRL + Control register for slow domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of slow domain glitch detectors enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for slow domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHFASTDOMAIN + Enable fast domain glitch detectors. + TAMPC_PROTECT_GLITCHFASTDOMAIN + read-write + 0x448 + + CTRL + Control register for fast domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of fast domain glitch detector's enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for fast domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + EXTRESETEN + Trigger a reset when tamper is detected by the external tamper detectors. + TAMPC_PROTECT_EXTRESETEN + read-write + 0x470 + + CTRL + Control register for external tamper reset enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of external tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for external tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + INTRESETEN + Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. + TAMPC_PROTECT_INTRESETEN + read-write + 0x478 + + CTRL + Control register for internal tamper reset enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of internal tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for internal tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + ERASEPROTECT + Device erase protection. + TAMPC_PROTECT_ERASEPROTECT + read-write + 0x480 + + CTRL + Control register for erase protection. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of eraseprotect signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for eraseprotect. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + + + + GLOBAL_I2S20_NS + Inter-IC Sound 0 + 0x400DD000 + I2S + + + + 0 + 0x1000 + registers + + + I2S20 + 221 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + 0x20 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + 0x20 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + 0x20 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + 0x20 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0x0 + + + 16Bit + 16 bit sample. + 0x1 + + + 24Bit + 24 bit sample. + 0x2 + + + 32Bit + 32 bit sample. + 0x3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 0x4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 0x5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 0x6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 0x7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + 0x20 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + 0x20 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + 0x20 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x20000000 + 0x20 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x20000000 + 0x20 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + 2 + 0x008 + CHANNEL[%s] + Unspecified + I2S_CHANNEL + read-write + 0x580 + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x004 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_I2S20_S + Inter-IC Sound 1 + 0x500DD000 + + + + I2S20 + 221 + + + + GLOBAL_QDEC20_NS + Quadrature Decoder 0 + 0x400E0000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC20 + 224 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SAMPLERDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event REPORTRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACCOF will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DBLRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + 0x00000000 + 0x20 + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0x0 + + + ActiveHigh + Led active on output pin high + 0x1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0x0 + + + 256us + 256 us + 0x1 + + + 512us + 512 us + 0x2 + + + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0x0 + + + 40Smpl + 40 samples/report + 0x1 + + + 80Smpl + 80 samples/report + 0x2 + + + 120Smpl + 120 samples/report + 0x3 + + + 160Smpl + 160 samples/report + 0x4 + + + 200Smpl + 200 samples/report + 0x5 + + + 240Smpl + 240 samples/report + 0x6 + + + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 7 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0x0 + + + Enabled + Debounce input filters enabled + 0x1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + GLOBAL_QDEC20_S + Quadrature Decoder 1 + 0x500E0000 + + + + QDEC20 + 224 + + + + GLOBAL_QDEC21_NS + Quadrature Decoder 2 + 0x400E1000 + + + + QDEC21 + 225 + + + + GLOBAL_QDEC21_S + Quadrature Decoder 3 + 0x500E1000 + + + + QDEC21 + 225 + + + + GLOBAL_GRTC_NS + Global Real-time counter 0 + 0x400E2000 + GRTC + + + + + 0 + 0x1000 + registers + + + GRTC_0 + 226 + + + GRTC_1 + 227 + + + GRTC_2 + 228 + + + GRTC_3 + 229 + + GRTC + 0x20 + + + 0xC + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture the counter value to CC[n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture the counter value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_START + Start the counter + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the counter + 0x064 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear the counter + 0x068 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear the counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTART + Start the PWM + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTART + Start the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTOP + Stop the PWM + 0x070 + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTOP + Stop the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0xC + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0xC + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RTCOMPARESYNC + The GRTC low frequency timer is synchronized with the SYSCOUNTER + 0x164 + read-write + 0x00000000 + 0x20 + + + EVENTS_RTCOMPARESYNC + The GRTC low frequency timer is synchronized with the SYSCOUNTER + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0x16C + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0xC + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RTCOMPARE_CLEAR + Shortcut between event RTCOMPARE and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x400 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Enable or disable event routing for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x404 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to enable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x408 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to disable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Counter mode selection + 0x510 + read-write + 0x00000000 + 0x20 + + + AUTOEN + Automatic enable to keep the SYSCOUNTER active. + 0 + 0 + + + Default + Default configuration to keep the SYSCOUNTER active. + 0x0 + + + CpuActive + In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. + 0x1 + + + + + SYSCOUNTEREN + Enable the SYSCOUNTER + 1 + 1 + + + Disabled + SYSCOUNTER disabled + 0x0 + + + Enabled + SYSCOUNTER enabled + 0x1 + + + + + + + 12 + 0x010 + CC[%s] + Unspecified + GRTC_CC + read-write + 0x520 + + CCL + Description cluster: The lower 32-bits of Capture/Compare register CC[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CCL + Capture/Compare low value in 1 us + 0 + 31 + + + + + CCH + Description cluster: The higher 32-bits of Capture/Compare register CC[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + CCH + Capture/Compare high value in 1 us + 0 + 19 + + + + + CCADD + Description cluster: Count to add to CC[n] when this register is written. + 0x008 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[n] + 0 + 30 + + + REFERENCE + Configure the Capture/Compare register + 31 + 31 + + + SYSCOUNTER + Adds SYSCOUNTER value. + 0x0 + + + CC + Adds CC value. + 0x1 + + + + + + + CCEN + Description cluster: Configure Capture/Compare register CC[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + ACTIVE + Configure the Capture/Compare register + 0 + 0 + + + Disable + Capture/Compare register CC[n] Disabled. + 0x0 + + + Enable + Capture/Compare register CC[n] enabled. + 0x1 + + + + + + + + TIMEOUT + Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER + 0x6A4 + read-write + 0x00000000 + 0x20 + + + VALUE + Number of 32Ki cycles + 0 + 15 + + + + + INTERVAL + Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. + 0x6A8 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[0] + 0 + 15 + + + + + WAKETIME + GRTC wake up time. + 0x6AC + read-write + 0x00000001 + 0x20 + + + VALUE + Number of LFCLK clock cycles to wake up before the next scheduled EVENTS_COMPARE event + 0 + 7 + + + + + PWMCONFIG + PWM configuration. + 0x710 + read-write + 0x00000000 + 0x20 + + + COMPAREVALUE + The PWM compare value + 0 + 7 + + + + + CLKOUT + Configuration of clock output + 0x714 + read-write + 0x00000000 + 0x20 + + + CLKOUT32K + Enable 32Ki clock output on pin + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + CLKOUTFAST + Enable fast clock output on pin + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + CLKCFG + Clock Configuration + 0x718 + read-write + 0x00010001 + 0x20 + + + CLKFASTDIV + Fast clock divisor value of clock output + 0 + 7 + + + CLKSEL + GRTC LFCLK clock source selection + 16 + 17 + write-only + + + LFXO + GRTC LFCLK clock source is LFXO + 0x0 + + + SystemLFCLK + GRTC LFCLK clock source is system LFCLK + 0x1 + + + LFLPRC + GRTC LFCLK clock source is LFLPRC + 0x2 + + + + + + + 4 + 0x010 + SYSCOUNTER[%s] + Unspecified + GRTC_SYSCOUNTER + read-write + 0x720 + + SYSCOUNTERL + Description cluster: The lower 32-bits of the SYSCOUNTER for index [n] + 0x000 + read-only + 0x00000000 + 0x20 + + + VALUE + The lower 32-bits of the SYSCOUNTER value. + 0 + 31 + + + + + SYSCOUNTERH + Description cluster: The higher 20-bits of the SYSCOUNTER for index [n] + 0x004 + read-only + 0x40000000 + 0x20 + + + VALUE + The higher 20-bits of the SYSCOUNTER value. + 0 + 19 + + + BUSY + SYSCOUNTER busy status + 30 + 30 + + + Ready + SYSCOUNTER is ready for read + 0x0 + + + Busy + SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this register is not valid) + 0x1 + + + + + OVERFLOW + The SYSCOUNTERL overflow indication after reading it. + 31 + 31 + + + NoOverflow + SYSCOUNTERL is not overflown + 0x0 + + + Overflow + SYSCOUNTERL overflown + 0x1 + + + + + + + ACTIVE + Description cluster: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] + 0x008 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Keep SYSCOUNTER in active state + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + + + + GLOBAL_GRTC_S + Global Real-time counter 1 + 0x500E2000 + + + + + GRTC_0 + 226 + + + GRTC_1 + 227 + + + GRTC_2 + 228 + + + GRTC_3 + 229 + + + + GLOBAL_SPU30_S + System protection unit 3 + 0x50100000 + + + + SPU30 + 256 + + + + GLOBAL_DPPIC30_NS + Distributed programmable peripheral interconnect controller 6 + 0x40102000 + + + + + + GLOBAL_DPPIC30_S + Distributed programmable peripheral interconnect controller 7 + 0x50102000 + + + + + + GLOBAL_PPIB30_NS + PPIB APB registers 14 + 0x40103000 + + + + + GLOBAL_PPIB30_S + PPIB APB registers 15 + 0x50103000 + + + + + GLOBAL_SPIM30_NS + Serial Peripheral Interface Master with EasyDMA 8 + 0x40104000 + + + + SERIAL30 + 260 + + + + GLOBAL_SPIS30_NS + SPI Slave 8 + 0x40104000 + GLOBAL_SPIM30_NS + + + + SERIAL30 + 260 + + + + GLOBAL_TWIM30_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x40104000 + GLOBAL_SPIM30_NS + + + + SERIAL30 + 260 + + + + GLOBAL_TWIS30_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x40104000 + GLOBAL_SPIM30_NS + + + + SERIAL30 + 260 + + + + GLOBAL_UARTE30_NS + UART with EasyDMA 8 + 0x40104000 + GLOBAL_SPIM30_NS + + + + SERIAL30 + 260 + + + + GLOBAL_SPIM30_S + Serial Peripheral Interface Master with EasyDMA 9 + 0x50104000 + + + + SERIAL30 + 260 + + + + GLOBAL_SPIS30_S + SPI Slave 9 + 0x50104000 + GLOBAL_SPIM30_S + + + + SERIAL30 + 260 + + + + GLOBAL_TWIM30_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x50104000 + GLOBAL_SPIM30_S + + + + SERIAL30 + 260 + + + + GLOBAL_TWIS30_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x50104000 + GLOBAL_SPIM30_S + + + + SERIAL30 + 260 + + + + GLOBAL_UARTE30_S + UART with EasyDMA 9 + 0x50104000 + GLOBAL_SPIM30_S + + + + SERIAL30 + 260 + + + + GLOBAL_RTC30_NS + Real-time counter 2 + 0x40105000 + + + + RTC30 + 261 + + + + GLOBAL_RTC30_S + Real-time counter 3 + 0x50105000 + + + + RTC30 + 261 + + + + GLOBAL_COMP_NS + Comparator 0 + 0x40106000 + COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 262 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value. This task requires that COMP has been started by the START Task. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value. This task requires that COMP has been started by the START Task. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference + 0x0 + + + VDD + VREF = VDD + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00002020 + 0x20 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0x0 + + + Normal + Normal mode + 0x1 + + + High + High-speed mode + 0x2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0x0 + + + Diff + Differential mode + 0x1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0x0 + + + Hyst40mV + Comparator hysteresis enabled + 0x1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + 0x00000000 + 0x20 + + + ISOURCE + Current source select on analog input + 0 + 1 + + + Off + Current source disabled + 0x0 + + + Ien2uA5 + Current source enabled (+/- 2.5 uA) + 0x1 + + + Ien5uA + Current source enabled (+/- 5 uA) + 0x2 + + + Ien10uA + Current source enabled (+/- 10 uA) + 0x3 + + + + + + + + + GLOBAL_LPCOMP_NS + Low-power comparator 0 + 0x40106000 + GLOBAL_COMP_NS + LPCOMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 262 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value. This task requires that LPCOMP has been started by the START task. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value. This task requires that LPCOMP has been started by the START task. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0x0 + + + Enabled + Comparator hysteresis enabled + 0x1 + + + + + + + + + GLOBAL_COMP_S + Comparator 1 + 0x50106000 + + + + COMP_LPCOMP + 262 + + + + GLOBAL_LPCOMP_S + Low-power comparator 1 + 0x50106000 + GLOBAL_COMP_S + + + + COMP_LPCOMP + 262 + + + + GLOBAL_WDT30_S + Watchdog Timer 0 + 0x50108000 + WDT + + + + 0 + 0x1000 + registers + + + WDT30 + 264 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + 0x20 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0x0 + + + Run + Keep WDT running while the CPU is sleeping + 0x1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0x0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 0x1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0x0 + + + Enable + Allow stopping WDT + 0x1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + 0x20 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + GLOBAL_WDT31_NS + Watchdog Timer 1 + 0x40109000 + + + + WDT31 + 265 + + + + GLOBAL_WDT31_S + Watchdog Timer 2 + 0x50109000 + + + + WDT31 + 265 + + + + GLOBAL_P0_NS + GPIO Port 4 + 0x4010A000 + + + + + + GLOBAL_P0_S + GPIO Port 5 + 0x5010A000 + + + + + + GLOBAL_GPIOTE30_NS + GPIO Tasks and Events 2 + 0x4010C000 + + + + + GPIOTE30_0 + 268 + + + GPIOTE30_1 + 269 + + + + GLOBAL_GPIOTE30_S + GPIO Tasks and Events 3 + 0x5010C000 + + + + + GPIOTE30_0 + 268 + + + GPIOTE30_1 + 269 + + + + GLOBAL_CLOCK_NS + Clock management 0 + 0x4010E000 + CLOCK + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 270 + + CLOCK + 0x20 + + + TASKS_XOSTART + Start crystal oscillator (HFXO) + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_XOSTART + Start crystal oscillator (HFXO) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_XOSTOP + Stop crystal oscillator (HFXO) + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_XOSTOP + Stop crystal oscillator (HFXO) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PLLSTART + Start PLL and keep it running, regardless of the automatic clock requests + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_PLLSTART + Start PLL and keep it running, regardless of the automatic clock requests + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PLLSTOP + Stop PLL + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_PLLSTOP + Stop PLL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLK.SRC + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_LFCLKSTART + Start LFCLK source as selected in LFCLK.SRC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_XOTUNE + Request tuning for HFXO + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_XOTUNE + Request tuning for HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_XOTUNEABORT + Abort tuning for HFXO + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_XOTUNEABORT + Abort tuning for HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_XOSTART + Subscribe configuration for task XOSTART + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task XOSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_XOSTOP + Subscribe configuration for task XOSTOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task XOSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PLLSTART + Subscribe configuration for task PLLSTART + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PLLSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PLLSTOP + Subscribe configuration for task PLLSTOP + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PLLSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LFCLKSTART + Subscribe configuration for task LFCLKSTART + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task LFCLKSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LFCLKSTOP + Subscribe configuration for task LFCLKSTOP + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task LFCLKSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CAL + Subscribe configuration for task CAL + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_XOTUNE + Subscribe configuration for task XOTUNE + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task XOTUNE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_XOTUNEABORT + Subscribe configuration for task XOTUNEABORT + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task XOTUNEABORT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_XOSTARTED + Crystal oscillator has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_XOSTARTED + Crystal oscillator has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PLLSTARTED + PLL started + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_PLLSTARTED + PLL started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_LFCLKSTARTED + LFCLK source started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + Calibration of LFRC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_XOTUNED + HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_XOTUNED + HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_XOTUNEERROR + HFXO quality issue detected, XOTUNE is needed + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_XOTUNEERROR + HFXO quality issue detected, XOTUNE is needed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_XOTUNEFAILED + HFXO tuning could not be completed + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_XOTUNEFAILED + HFXO tuning could not be completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_XOSTARTED + Publish configuration for event XOSTARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event XOSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PLLSTARTED + Publish configuration for event PLLSTARTED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PLLSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LFCLKSTARTED + Publish configuration for event LFCLKSTARTED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LFCLKSTARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_XOTUNED + Publish configuration for event XOTUNED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event XOTUNED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_XOTUNEERROR + Publish configuration for event XOTUNEERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event XOTUNEERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_XOTUNEFAILED + Publish configuration for event XOTUNEFAILED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event XOTUNEFAILED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + XOSTARTED + Enable or disable interrupt for event XOSTARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PLLSTARTED + Enable or disable interrupt for event PLLSTARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LFCLKSTARTED + Enable or disable interrupt for event LFCLKSTARTED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + XOTUNED + Enable or disable interrupt for event XOTUNED + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + XOTUNEERROR + Enable or disable interrupt for event XOTUNEERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + XOTUNEFAILED + Enable or disable interrupt for event XOTUNEFAILED + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + XOSTARTED + Write '1' to enable interrupt for event XOSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PLLSTARTED + Write '1' to enable interrupt for event PLLSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + XOTUNED + Write '1' to enable interrupt for event XOTUNED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + XOTUNEERROR + Write '1' to enable interrupt for event XOTUNEERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + XOTUNEFAILED + Write '1' to enable interrupt for event XOTUNEFAILED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + XOSTARTED + Write '1' to disable interrupt for event XOSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PLLSTARTED + Write '1' to disable interrupt for event PLLSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + XOTUNED + Write '1' to disable interrupt for event XOTUNED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + XOTUNEERROR + Write '1' to disable interrupt for event XOTUNEERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + XOTUNEFAILED + Write '1' to disable interrupt for event XOTUNEFAILED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + XOSTARTED + Read pending status of interrupt for event XOSTARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PLLSTARTED + Read pending status of interrupt for event PLLSTARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LFCLKSTARTED + Read pending status of interrupt for event LFCLKSTARTED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DONE + Read pending status of interrupt for event DONE + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + XOTUNED + Read pending status of interrupt for event XOTUNED + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + XOTUNEERROR + Read pending status of interrupt for event XOTUNEERROR + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + XOTUNEFAILED + Read pending status of interrupt for event XOTUNEFAILED + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + XO + Unspecified + CLOCK_XO + read-write + 0x400 + + RUN + Indicates that XOSTART task was triggered + 0x008 + read-only + 0x00000000 + 0x20 + + + STATUS + XOSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + STAT + XO status + 0x00C + read-only + 0x00000000 + 0x20 + + + STATE + XO state (Running between START task and STOPPED event) + 16 + 16 + + + NotRunning + XO is not running + 0x0 + + + Running + XO is running + 0x1 + + + + + + + + PLL + Unspecified + CLOCK_PLL + read-write + 0x420 + + RUN + Indicates that PLLSTART task was triggered + 0x008 + read-only + 0x00000000 + 0x20 + + + STATUS + PLLSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + STAT + Which PLL settings were selected when triggering START task + 0x00C + read-only + 0x00000000 + 0x20 + + + STATE + PLL state (Running between START task and STOPPED event) + 16 + 16 + + + NotRunning + PLL is not running + 0x0 + + + Running + PLL is running + 0x1 + + + + + + + + LFCLK + Unspecified + CLOCK_LFCLK + read-write + 0x440 + + SRC + Clock source for LFCLK + 0x000 + read-write + 0x00000000 + 0x20 + + + SRC + Select which LFCLK source is started by the LFCLKSTART task + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 0x0 + + + LFXO + 32.768 kHz crystal oscillator + 0x1 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 0x2 + + + + + + + RUN + Indicates that LFCLKSTART task was triggered + 0x008 + read-only + 0x00000000 + 0x20 + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + STAT + Copy of LFCLK.SRCCOPY register, set when LFCLKSTARTED event is triggered. + 0x00C + read-only + 0x00000000 + 0x20 + + + SRC + Value of LFCLK.SRCCOPY register when LFCLKSTARTED event was triggered + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 0x0 + + + LFXO + 32.768 kHz crystal oscillator + 0x1 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 0x2 + + + + + ALWAYSRUNNING + ALWAYSRUN activated + 4 + 4 + + + NotRunning + Automatic clock control enabled + 0x0 + + + Running + Oscillator is always running + 0x1 + + + + + STATE + LFCLK state (Running between START task and STOPPED event) + 16 + 16 + + + NotRunning + LFCLK not running + 0x0 + + + Running + LFCLK running + 0x1 + + + + + + + SRCCOPY + Copy of LFCLK.SRC register, set when LFCLKSTART task is triggered + 0x010 + read-write + 0x00000000 + 0x20 + + + SRC + Value of LFCLK.SRC register when LFCLKSTART task was triggered + 0 + 1 + + + LFRC + 32.768 kHz RC oscillator + 0x0 + + + LFXO + 32.768 kHz crystal oscillator + 0x1 + + + LFSYNT + 32.768 kHz synthesized from HFCLK + 0x2 + + + + + + + + + + GLOBAL_POWER_NS + Power control 0 + 0x4010E000 + GLOBAL_CLOCK_NS + POWER + + + + 0 + 0x1000 + registers + + + CLOCK_POWER + 270 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0x30 + write-only + 0x00000000 + 0x20 + + + TASKS_CONSTLAT + Enable Constant Latency mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0x34 + write-only + 0x00000000 + 0x20 + + + TASKS_LOWPWR + Enable Low-power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_CONSTLAT + Subscribe configuration for task CONSTLAT + 0xB0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CONSTLAT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_LOWPWR + Subscribe configuration for task LOWPWR + 0xB4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task LOWPWR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_POFWARN + Publish configuration for event POFWARN + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event POFWARN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SLEEPENTER + Publish configuration for event SLEEPENTER + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SLEEPENTER will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SLEEPEXIT + Publish configuration for event SLEEPEXIT + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SLEEPEXIT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + POFWARN + Enable or disable interrupt for event POFWARN + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SLEEPENTER + Enable or disable interrupt for event SLEEPENTER + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SLEEPEXIT + Enable or disable interrupt for event SLEEPEXIT + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + 0x2 + 0x4 + GPREGRET[%s] + Description collection: General purpose retention register + 0x500 + read-write + 0x00000000 + 0x20 + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + CONSTLATSTAT + Status of constant latency + 0x510 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Disable + Constant latency disabled + 0x0 + + + Enable + Constant latency enabled + 0x1 + + + + + + + + + GLOBAL_RESET_NS + Reset control 0 + 0x4010E000 + GLOBAL_CLOCK_NS + RESET + + + + 0 + 0x1000 + registers + + RESET + 0x20 + + + RESETREAS + Reset reason + 0x600 + read-write + 0x00000000 + 0x20 + + + RESETPIN + Reset from pin reset detected + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOG0 + Reset from watchdog timer 0 detected + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOG1 + Reset from watchdog timer 1 detected + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAPSOFT + Soft reset from CTRL-AP detected + 3 + 3 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAPHARD + Reset due to CTRL-AP hard reset + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAPPIN + Reset due to CTRL-AP pin reset + 5 + 5 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SREQ + Reset from soft reset detected + 6 + 6 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LOCKUP + Reset from CPU lockup detected + 7 + 7 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO + 8 + 8 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP + 9 + 9 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DIF + Reset triggered by Debug Interface + 10 + 10 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + GRTC + Reset due to wakeup from GRTC + 11 + 11 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + NFC + Reset after wakeup from System OFF mode due to NFC field being detected + 12 + 12 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECTAMPER + Reset due to illegal tampering of the device + 13 + 13 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + + + + + GLOBAL_CLOCK_S + Clock management 1 + 0x5010E000 + + + + CLOCK_POWER + 270 + + + + GLOBAL_POWER_S + Power control 1 + 0x5010E000 + GLOBAL_CLOCK_S + + + + CLOCK_POWER + 270 + + + + GLOBAL_RESET_S + Reset control 1 + 0x5010E000 + GLOBAL_CLOCK_S + + + + + GLOBAL_OSCILLATORS_NS + Oscillator control 0 + 0x40120000 + OSCILLATORS + + + + 0 + 0x1000 + registers + + OSCILLATORS + 0x20 + + + XOSC32M + 32 MHz oscillator control + OSCILLATORS_XOSC32M + read-write + 0x700 + + CONFIG + Unspecified + OSCILLATORS_XOSC32M_CONFIG + read-write + 0x14 + + INTCAP + Crystal load capacitor as seen by the crystal across its terminals, including pin capacitance but excluding PCB stray capacitance. + 0x08 + read-write + 0x00000020 + 0x20 + + + VAL + Crystal load capacitor value + 0 + 5 + + + + + + + PLL + Oscillator control + OSCILLATORS_PLL + read-write + 0x800 + + FREQ + Set speed of MCU power domain, including CPU + 0x00 + read-write + 0x00000003 + 0x20 + + + FREQ + Select CPU speed + 0 + 1 + + + CK128M + 128 MHz + 0x1 + + + CK64M + 64 MHz + 0x3 + + + + + + + CURRENTFREQ + Current speed of MCU power domain, including CPU + 0x04 + read-only + 0x00000003 + 0x20 + + + CURRENTFREQ + Active CPU speed + 0 + 1 + + + CK128M + 128 MHz + 0x1 + + + CK64M + 64 MHz + 0x3 + + + + + + + + XOSC32KI + 32.768 kHz oscillator control + OSCILLATORS_XOSC32KI + read-write + 0x900 + + INTCAP + Programmable capacitance of XL1 and XL2 + 0x004 + read-write + 0x00000017 + 0x20 + + + VAL + Crystal load capacitor as seen by the crystal across its terminals, including pin capacitance but excluding PCB stray capacitance. + 0 + 4 + + + + + + + + GLOBAL_REGULATORS_NS + Voltage regulators 0 + 0x40120000 + GLOBAL_OSCILLATORS_NS + REGULATORS + + + + 0 + 0x1000 + registers + + REGULATORS + 0x20 + + + VREGM + Register interface for the medium voltage regulator + REGULATORS_VREGM + read-write + 0x400 + + ENABLE + Enable register for VREGM + 0x000 + read-write + 0x00000001 + 0x20 + + + ENABLE + Enable the regulator + 0 + 0 + + + Disabled + Disable the regulator + 0x0 + + + Enabled + Enable the regulator + 0x1 + + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + 0x00000000 + 0x20 + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 0x1 + + + + + + + POFCON + Power-fail comparator configuration + 0x530 + read-write + 0x00000000 + 0x20 + + + POF + Enable or disable power-fail comparator + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + THRESHOLD + Power-fail comparator threshold setting + 1 + 4 + + + V17 + Set threshold to 1.7 V + 0x0 + + + V18 + Set threshold to 1.8 V + 0x1 + + + V19 + Set threshold to 1.9 V + 0x2 + + + V20 + Set threshold to 2.0 V + 0x3 + + + V21 + Set threshold to 2.1 V + 0x4 + + + V22 + Set threshold to 2.2 V + 0x5 + + + V23 + Set threshold to 2.3 V + 0x6 + + + V24 + Set threshold to 2.4 V + 0x7 + + + V25 + Set threshold to 2.5 V + 0x8 + + + V26 + Set threshold to 2.6 V + 0x9 + + + V27 + Set threshold to 2.7 V + 0xA + + + V28 + Set threshold to 2.8 V + 0xB + + + + + EVENTDISABLE + Disable the POFWARN power-fail warning event + 7 + 7 + + + Enabled + POFWARN event is generated + 0x0 + + + Disabled + POFWARN event is not generated + 0x1 + + + + + + + POFSTAT + Power-fail comparator status register + 0x534 + read-only + 0x00000000 + 0x20 + + + COMPARATOR + Power-fail comparator status + 0 + 0 + + + Above + Voltage detected above VPOF threshold + 0x0 + + + Below + Voltage detected below VPOF threshold + 0x1 + + + + + + + VREGMAIN + Register interface for main voltage regulator. + REGULATORS_VREGMAIN + read-write + 0x600 + + DCDCEN + Enable DC/DC converter for better power efficiency + 0x00 + read-write + 0x00000000 + 0x20 + + + VAL + Enable DC/DC buck converter + 0 + 0 + + + Disabled + Disable DC/DC converter and use LDO + 0x0 + + + Enabled + Enable DC/DC converter + 0x1 + + + + + + + INDUCTORDET + VREGMAIN inductor detection + 0x04 + read-only + 0x00000000 + 0x20 + + + DETECTED + 0 + 0 + + + InductorNotDetected + VREGMAIN inductor not detected + 0x0 + + + InductorDetected + VREGMAIN inductor detected + 0x1 + + + + + + + + + + GLOBAL_OSCILLATORS_S + Oscillator control 1 + 0x50120000 + + + + + GLOBAL_REGULATORS_S + Voltage regulators 1 + 0x50120000 + GLOBAL_OSCILLATORS_S + + + + + \ No newline at end of file diff --git a/pyocd/target/builtin/__init__.py b/pyocd/target/builtin/__init__.py index 7530ccbc7..715ec6438 100644 --- a/pyocd/target/builtin/__init__.py +++ b/pyocd/target/builtin/__init__.py @@ -61,6 +61,7 @@ from . import target_nRF52832_xxAA from . import target_nRF52833_xxAA from . import target_nRF52840_xxAA +from . import target_nRF54L15 from . import target_nRF91xx from . import target_S32K344 from . import target_STM32F103RC @@ -208,6 +209,7 @@ 'nrf52833': target_nRF52833_xxAA.NRF52833, 'nrf52840' : target_nRF52840_xxAA.NRF52840, 'nrf91' : target_nRF91xx.NRF91XX, + 'nrf54l' : target_nRF54L15.NRF54L15, 's32k344': target_S32K344.S32K344, 'stm32f103rc': target_STM32F103RC.STM32F103RC, 'stm32f051': target_STM32F051T8.STM32F051, diff --git a/pyocd/target/builtin/target_nRF54L15.py b/pyocd/target/builtin/target_nRF54L15.py new file mode 100644 index 000000000..588fd2c99 --- /dev/null +++ b/pyocd/target/builtin/target_nRF54L15.py @@ -0,0 +1,80 @@ +# Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from ...core.memory_map import FlashRegion, RamRegion, MemoryMap +from ...debug.svd.loader import SVDFile +from ..family.target_nRF54L import NRF54L + +FLASH_ALGO = { + 'load_address' : 0x20000000, + + # Flash algorithm as a hex string + 'instructions': [ + 0xE00ABE00, + 0xf8d24a02, 0x2b013400, 0x4770d1fb, 0x5004b000, 0x47702000, 0x47702000, 0x49072001, 0xf8c1b508, + 0xf7ff0500, 0xf8c1ffed, 0x20000540, 0xffe8f7ff, 0x0500f8c1, 0xbf00bd08, 0x5004b000, 0x2301b508, + 0xf8c14906, 0xf7ff3500, 0xf04fffdb, 0x600333ff, 0xf7ff2000, 0xf8c1ffd5, 0xbd080500, 0x5004b000, + 0x2301b538, 0x4d0c4614, 0x0103f021, 0x3500f8c5, 0xffc6f7ff, 0x44214622, 0x42911b00, 0x2000d105, + 0xffbef7ff, 0x0500f8c5, 0x4613bd38, 0x4b04f853, 0x461a5014, 0xbf00e7f1, 0x5004b000, 0x00000000 + ], + + # Relative function addresses + 'pc_init': 0x20000015, + 'pc_unInit': 0x20000019, + 'pc_program_page': 0x20000065, + 'pc_erase_sector': 0x20000041, + 'pc_eraseAll': 0x2000001d, + + 'static_base' : 0x20000000 + 0x00000004 + 0x000000a0, + 'begin_stack' : 0x20000300, + 'begin_data' : 0x20000000 + 0x1000, + 'page_size' : 0x4, + 'analyzer_supported' : False, + 'analyzer_address' : 0x00000000, + 'page_buffers' : [0x20001000, 0x20001004], # Enable double buffering + 'min_program_length' : 0x4, + + # Flash information + 'flash_start': 0x0, + 'flash_size': 0x17d000, + 'sector_sizes': ( + (0x0, 0x17d000), + (0xffd000, 0x1000), + ) +} + +class NRF54L15(NRF54L): + MEMORY_MAP = MemoryMap( + FlashRegion( + start=0x0, + length=0x0017D000, + blocksize=0x1000, + is_boot_memory=True, + algo=FLASH_ALGO, + ), + # User Information Configation Registers (UICR) as a flash region + FlashRegion( + start=0x00FFD000, + length=0x1000, + blocksize=0x4, + is_testable=False, + is_erasable=False, + algo=FLASH_ALGO, + ), + RamRegion(start=0x20000000, length=0x40000), + ) + + def __init__(self, session): + super(NRF54L15, self).__init__(session, self.MEMORY_MAP) + self._svd_location = SVDFile.from_builtin("nrf54l15.svd") diff --git a/pyocd/target/family/__init__.py b/pyocd/target/family/__init__.py index 7ef8bb893..201d3cd83 100644 --- a/pyocd/target/family/__init__.py +++ b/pyocd/target/family/__init__.py @@ -22,6 +22,7 @@ from . import target_kinetis from . import target_lpc5500 from . import target_nRF52 +from . import target_nRF54L from . import target_nRF91 class FamilyInfo(NamedTuple): @@ -41,5 +42,6 @@ class FamilyInfo(NamedTuple): FAMILIES = [ FamilyInfo("NXP", re.compile(r'MK[LEVWS]?.*'), target_kinetis.Kinetis ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF52[0-9]+.*'), target_nRF52.NRF52 ), + FamilyInfo("Nordic Semiconductor", re.compile(r'nRF54L[0-9]+.*'), target_nRF54L.NRF54L ), FamilyInfo("Nordic Semiconductor", re.compile(r'nRF91[0-9]+.*'), target_nRF91.NRF91 ), ] diff --git a/pyocd/target/family/target_nRF54L.py b/pyocd/target/family/target_nRF54L.py new file mode 100644 index 000000000..91ea80008 --- /dev/null +++ b/pyocd/target/family/target_nRF54L.py @@ -0,0 +1,178 @@ +# pyOCD debugger +# Copyright (c) 2006-2013 Arm Limited +# Copyright (c) 2019 Monadnock Systems Ltd. +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import logging +from time import sleep +import os +import re +from zipfile import ZipFile +from tempfile import TemporaryDirectory +from intelhex import IntelHex + +from ...core import exceptions +from ...core.memory_map import FlashRegion +from ...core.target import Target +from ...coresight.coresight_target import CoreSightTarget +from ...flash.eraser import FlashEraser +from ...flash.file_programmer import FileProgrammer +from ...utility.timeout import Timeout +from ...utility.progress import print_progress +from ...commands.base import CommandBase +from ...commands.execution_context import CommandSet + +AHB_AP_NUM = 0x0 +AUX_AHB_AP_NUM = 0x1 +CTRL_AP_NUM = 0x2 + +CTRL_AP_RESET = 0x000 +CTRL_AP_ERASEALL = 0x004 +CTRL_AP_ERASEALLSTATUS = 0x008 +CTRL_AP_ERASEPROTECTSTATUS = 0x00C +CTRL_AP_ERASEPROTECTDISABLE = 0x010 +CTRL_AP_APPROTECTSTATUS = 0x014 +CTRL_AP_MAILBOX_TXDATA = 0x020 +CTRL_AP_MAILBOX_TXSTATUS = 0x024 +CTRL_AP_MAILBOX_RXDATA = 0x028 +CTRL_AP_MAILBOX_RXSTATUS = 0x02C +CTRL_AP_IDR = 0x0FC + +CTRL_AP_ERASEALLSTATUS_READY = 0x0 +CTRL_AP_ERASEALLSTATUS_READYTORESET = 0x1 +CTRL_AP_ERASEALLSTATUS_BUSY = 0x2 +CTRL_AP_ERASEALLSTATUS_ERROR = 0x3 + +CTRL_AP_APPROTECTSTATUS_APPROTECT_MSK = 0x1 +CTRL_AP_APPROTECTSTATUS_SECUREAPPROTECT_MSK = 0x2 +CTRL_AP_ERASEPROTECTSTATUS_MSK = 0x1 + +CTRL_IDR_EXPECTED = 0x32880000 + +MASS_ERASE_TIMEOUT = 30.0 + +CSW_DEVICEEN = 0x00000040 + +LOG = logging.getLogger(__name__) + +def bytes_to_word(bts): + result = 0 + for i, b in enumerate(bts): + result |= b << (8*i) + return result + +def word_to_bytes(wrd): + result = [] + for i in range(4): + result.append((wrd >> (8*i)) & 0xFF) + return bytes(result) + +class NRF54L(CoreSightTarget): + + VENDOR = "Nordic Semiconductor" + + def __init__(self, session, memory_map=None): + super(NRF54L, self).__init__(session, memory_map) + self.ctrl_ap = None + self.was_locked = False + + def create_init_sequence(self): + seq = super(NRF54L, self).create_init_sequence() + + # Must check whether security is enabled, and potentially auto-unlock, before + # any init tasks that require system bus access. + seq.wrap_task('discovery', + lambda seq: seq.insert_before('find_components', + ('check_ctrl_ap_idr', self.check_ctrl_ap_idr), + ('check_flash_security', self.check_flash_security), + ) + ) + seq.insert_before('post_connect_hook', + ('check_part_info', self.check_part_info)) + + return seq + + def check_ctrl_ap_idr(self): + LOG.info("Checking CTRL-AP IDR") + self.ctrl_ap = self.dp.aps[CTRL_AP_NUM] + + # Check CTRL-AP ID. + if self.ctrl_ap.idr != CTRL_IDR_EXPECTED: + LOG.error("%s: bad CTRL-AP IDR (is 0x%08x)", self.part_number, self.ctrl_ap.idr) + + def ap_is_enabled(self): + csw = self.dp.read_ap(AHB_AP_NUM << 24) + return csw & CSW_DEVICEEN + + def check_flash_security(self): + """@brief Check security and unlock device. + + This init task determines whether the device is locked (APPROTECT enabled). If it is, + and if auto unlock is enabled, then perform a mass erase to unlock the device. + + This init task runs *before* cores are created. + """ + + target_id = self.dp.read_dp(0x24) + if target_id & 0xFFF != 0x289: + LOG.error(f"This doesn't look like a Nordic Semiconductor device!") + if target_id & 0xF0000 != 0xC0000: + LOG.error(f"This doesn't look like an nRF54L device!") + + if not self.ap_is_enabled(): + if self.session.options.get('auto_unlock'): + LOG.warning("%s APPROTECT enabled: will try to unlock via mass erase", self.part_number) + + self.mass_erase() + else: + LOG.warning("%s is not in a secure state", self.part_number) + + + def check_part_info(self): + partno = self.read32(0x00FFC31C) + variant = self.read32(0x00FFC320) + + LOG.info(f"This appears to be an nRF{partno:X} " + + f"{word_to_bytes(variant).decode('ASCII', errors='ignore')}") + + def mass_erase(self): + # See Nordic Whitepaper nWP-027 for magic numbers and order of operations from the vendor + self.ctrl_ap.write_reg(CTRL_AP_ERASEALL, 1) + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + status = self.ctrl_ap.read_reg(CTRL_AP_ERASEALLSTATUS) + if status == CTRL_AP_ERASEALLSTATUS_BUSY: + break + sleep(0.5) + else: + # Timed out + LOG.error("Mass erase timeout waiting for ERASEALLSTATUS") + return False + with Timeout(MASS_ERASE_TIMEOUT) as to: + while to.check(): + status = self.ctrl_ap.read_reg(CTRL_AP_ERASEALLSTATUS) + if status == CTRL_AP_ERASEALLSTATUS_READYTORESET: + break + sleep(0.5) + else: + # Timed out + LOG.error("Mass erase timeout waiting for ERASEALLSTATUS") + return False + sleep(0.01) + self.ctrl_ap.write_reg(CTRL_AP_RESET, 2) + self.ctrl_ap.write_reg(CTRL_AP_RESET, 0) + sleep(0.2) + return True