LayoutAnalyzer (beta with testing features for ICs)

Release notes for supported features:

• GDSII file input and simulation file input
  • Does not support array references, mirroring, magnification, or rotation in the GDSII file
  • Must state physical extents in each Cartesian dimension, the frequency sweep, the bottom z-coordinate and height and relative permittivity of each layer, and the coordinates of each port (must only have a single coordinate differ between source and return) along with the port direction in the simulation input file
• SPICE subcircuit file output of all linear components
  • SPICE subcircuit file meant to be used with Sandia Xyce
  • Alternative: SPEF file output without ability to consider nonlinear effects or DC biasing
• Essential solver capability for Y-parameter output
• User must supply transistor model and identify ports defined for each I/O pin and each transistor of interest
  • The post-simulation step uses Sandia Xyce to combine the SPICE subcircuit, transistor model, and port excitation signals to run arbitrary circuit simulations of the system with large-signal effects and biasing