{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"sv-tests","owner":"chipsalliance","isFork":false,"description":"Test suite designed to check compliance with the SystemVerilog standard.","allTopics":["rtl","verilog","systemverilog","hdl","compliance-testing","symbiflow"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":23,"issueCount":47,"starsCount":265,"forksCount":70,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T14:29:59.584Z"}},{"type":"Public","name":"Cores-VeeR-EL2","owner":"chipsalliance","isFork":false,"description":"VeeR EL2 Core","allTopics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":19,"issueCount":27,"starsCount":233,"forksCount":68,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T16:43:09.349Z"}},{"type":"Public","name":"caliptra-rtl","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra RoT IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":5,"issueCount":54,"starsCount":57,"forksCount":31,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-04T12:43:48.896Z"}},{"type":"Public","name":"aib-protocols","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":2,"starsCount":21,"forksCount":6,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-20T10:50:35.085Z"}},{"type":"Public","name":"verible-formatter-action","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":3,"starsCount":7,"forksCount":8,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-02T13:24:44.655Z"}},{"type":"Public","name":"uvm-verilator","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":59,"forksCount":16,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-09-20T11:28:22.526Z"}},{"type":"Public","name":"Cores-VeeR-EH1","owner":"chipsalliance","isFork":false,"description":"VeeR EH1 core","allTopics":["processor","rtl","risc","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","veer","fpga","riscv","risc-v"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":16,"starsCount":787,"forksCount":213,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-29T19:16:55.794Z"}},{"type":"Public","name":"Cores-VeeR-EH2","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":12,"starsCount":206,"forksCount":56,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-12-22T16:53:54.638Z"}}],"repositoryCount":8,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"chipsalliance repositories"}