{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"rvdecoderdb","owner":"chipsalliance","isFork":false,"description":"The Scala parser to parse riscv/riscv-opcodes generate","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T17:54:53.310Z"}},{"type":"Public","name":"t1","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":10,"issueCount":14,"starsCount":93,"forksCount":19,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T17:02:15.931Z"}},{"type":"Public","name":"chisel","owner":"chipsalliance","isFork":false,"description":"Chisel: A Modern Hardware Design Language","allTopics":["chip-generator","chisel","rtl","chisel3","firrtl","scala","verilog"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":151,"issueCount":301,"starsCount":3819,"forksCount":576,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-05T23:31:56.839Z"}},{"type":"Public","name":"rocket-chip","owner":"chipsalliance","isFork":false,"description":"Rocket Chip Generator","allTopics":["chisel","scala","rocket-chip","chip-generator","riscv","rtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":60,"issueCount":224,"starsCount":3081,"forksCount":1088,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-30T21:12:56.845Z"}},{"type":"Public","name":"rocket-chip-inclusive-cache","owner":"chipsalliance","isFork":false,"description":"An RTL generator for a last-level shared inclusive TileLink cache controller","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":4,"issueCount":5,"starsCount":15,"forksCount":13,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-30T05:44:10.088Z"}},{"type":"Public","name":"rocket-chip-blocks","owner":"chipsalliance","isFork":false,"description":"RTL blocks compatible with the Rocket Chip Generator","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":5,"issueCount":0,"starsCount":14,"forksCount":14,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-26T18:59:08.779Z"}},{"type":"Public","name":"diplomacy","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":8,"starsCount":16,"forksCount":7,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-26T17:27:43.117Z"}},{"type":"Public","name":"firtool-resolver","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-25T18:40:06.169Z"}},{"type":"Public","name":"chisel-interface","owner":"chipsalliance","isFork":false,"description":"The 'missing header' for Chisel","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":35,"issueCount":0,"starsCount":13,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-19T14:30:55.815Z"}},{"type":"Public","name":"rocket-chip-fpga-shells","owner":"chipsalliance","isFork":false,"description":"Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":1,"starsCount":15,"forksCount":17,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-06T17:57:36.575Z"}},{"type":"Public","name":"firrtl","owner":"chipsalliance","isFork":false,"description":"Flexible Intermediate Representation for RTL","allTopics":["compiler","hardware","representation","transformation","intermediate","firrtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":111,"issueCount":176,"starsCount":704,"forksCount":175,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-04T15:58:01.253Z"}},{"type":"Public template","name":"chisel-template","owner":"chipsalliance","isFork":false,"description":"A template project for beginning new Chisel work","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":3,"issueCount":11,"starsCount":554,"forksCount":177,"license":"The Unlicense","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-26T06:51:00.234Z"}},{"type":"Public","name":"treadle","owner":"chipsalliance","isFork":false,"description":"Chisel/Firrtl execution engine","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":11,"issueCount":15,"starsCount":150,"forksCount":31,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-24T15:22:39.637Z"}},{"type":"Public","name":"amba","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-05T21:42:14.908Z"}},{"type":"Public","name":"cde","owner":"chipsalliance","isFork":false,"description":"A Scala library for Context-Dependent Environments","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":3,"starsCount":42,"forksCount":21,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-25T19:17:28.252Z"}},{"type":"Public","name":"tilelink","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":5,"issueCount":1,"starsCount":21,"forksCount":7,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-25T03:02:49.383Z"}},{"type":"Public","name":"playground","owner":"chipsalliance","isFork":false,"description":"chipyard in mill :P","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":3,"issueCount":6,"starsCount":72,"forksCount":34,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-11-20T12:55:12.073Z"}},{"type":"Public","name":"rocket","owner":"chipsalliance","isFork":false,"description":"The working draft to split rocket core out from rocket chip","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":8,"issueCount":2,"starsCount":14,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-12-22T21:21:18.957Z"}}],"repositoryCount":18,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"chipsalliance repositories"}