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CORE_V_MCU high level design specs #428

CORE_V_MCU high level design specs

CORE_V_MCU high level design specs #428

Workflow file for this run

# Copyright 2020 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Run functional regression checks
name: ci
on: [push, pull_request]
jobs:
##################
# Verilator Lint #
##################
# (tempoarily) disable verilog linting until Verilator v5.008 is available for GitHub
#verilator_lint:
# name: Verilator Lint
# runs-on: ubuntu-latest
# steps:
# - uses: actions/checkout@v2
# - uses: actions/setup-python@v2
# with:
# python-version: 3.9
# - name: Install requirements
# run: pip install -r python-requirements.txt
# - name: Install Verilator
# run: |
# echo 'deb http://download.opensuse.org/repositories/home:/phiwag:/edatools/xUbuntu_20.04/ /' | sudo tee /etc/apt/sources.list.d/home:phiwag:edatools.list
# curl -fsSL https://download.opensuse.org/repositories/home:phiwag:edatools/xUbuntu_20.04/Release.key | gpg --dearmor | sudo tee /etc/apt/trusted.gpg.d/home_phiwag_edatools.gpg > /dev/null
# sudo apt update
# sudo apt install verilator
# - name: Run Lint
# run: |
# ./util/verilog-lint