lint

Pandoc required to generate PDF #540

Sign in to view logs

Triggered via pull request August 30, 2023 19:28

MikeOpenHWGroup

synchronize #300

MikeOpenHWGroup:install_pandoc

Status Failure

Total duration 1m 2s

Artifacts –

This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

lint.yml

on: pull_request

Format Verilog Sources

Vendor Up-to-Date

Annotations

10 errors and 2 warnings

Format Verilog Sources: rtl/core-v-mcu/components/apb_soc_ctrl.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/efpga_subsystem/efpga_subsystem.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/fc/cv32e40p_fp_wrapper.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/fc/fc_subsystem.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/axi64_2_lint32_wrap.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/clk_and_control.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/interleaved_crossbar.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/lint_2_axi_wrap.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/soc_clk_rst_gen.sv#L1

Files differ (M)

Format Verilog Sources: rtl/core-v-mcu/soc/soc_event_generator.sv#L1

Files differ (M)

Format Verilog Sources

The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2, actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/

Vendor Up-to-Date

The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2, actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/