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<title>Glossary And Acronyms — NVDLA Documentation</title>
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<div class="section" id="glossary-and-acronyms">
<h1>Glossary And Acronyms<a class="headerlink" href="#glossary-and-acronyms" title="Permalink to this headline">¶</a></h1>
<dl class="glossary simple">
<dt id="term-NVDLA">NVDLA<a class="headerlink" href="#term-NVDLA" title="Permalink to this term">¶</a></dt><dd><p>NVIDIA Deep Learning Accelerator. Hardware logic implementing different function engines.</p>
</dd>
<dt id="term-DLA">DLA<a class="headerlink" href="#term-DLA" title="Permalink to this term">¶</a></dt><dd><p>Deep Learning Accelerator</p>
</dd>
<dt id="term-UMD">UMD<a class="headerlink" href="#term-UMD" title="Permalink to this term">¶</a></dt><dd><p>User Mode Driver, software running in user space. It provides interfaces to user application</p>
</dd>
<dt id="term-KMD">KMD<a class="headerlink" href="#term-KMD" title="Permalink to this term">¶</a></dt><dd><p>Kernel Mode Driver, software running in kernel space. It implement low level functions such as hardware
programming and provides interfaces to UMD</p>
</dd>
<dt id="term-NVDLA-Loadable">NVDLA Loadable<a class="headerlink" href="#term-NVDLA-Loadable" title="Permalink to this term">¶</a></dt><dd><p>Format used to store compiled neural network.</p>
</dd>
<dt id="term-hw-layer">hw-layer<a class="headerlink" href="#term-hw-layer" title="Permalink to this term">¶</a></dt><dd><p>One complete hardware block processing. It starts with a set of register configuration with an
enable field. When it is done, it triggers ONE interrupt.</p>
</dd>
<dt id="term-SDP">SDP<a class="headerlink" href="#term-SDP" title="Permalink to this term">¶</a></dt><dd><p>Single data processor, a functional sub unit in NVDLA engine</p>
</dd>
<dt id="term-PDP">PDP<a class="headerlink" href="#term-PDP" title="Permalink to this term">¶</a></dt><dd><p>Planar data processor, a functional sub unit in NVDLA engine</p>
</dd>
<dt id="term-CDP">CDP<a class="headerlink" href="#term-CDP" title="Permalink to this term">¶</a></dt><dd><p>Channel data processor, a functional sub unit in NVDLA engine</p>
</dd>
<dt id="term-Rubik">Rubik<a class="headerlink" href="#term-Rubik" title="Permalink to this term">¶</a></dt><dd><p>Data operation processor. A functional sub unit in NVDLA engine to
support data layout transformation</p>
</dd>
<dt id="term-BDMA">BDMA<a class="headerlink" href="#term-BDMA" title="Permalink to this term">¶</a></dt><dd><p>Bridge DMA. BDMA transform data from CVSRAM to MC and vice versa</p>
</dd>
<dt id="term-CDMA">CDMA<a class="headerlink" href="#term-CDMA" title="Permalink to this term">¶</a></dt><dd><p>Convolution DMA, responsible for load image/weight/feature data to convolution core</p>
</dd>
<dt id="term-RDMA">RDMA<a class="headerlink" href="#term-RDMA" title="Permalink to this term">¶</a></dt><dd><p>Read DMA, instanced in SDP/CDP/PDP/Rubik engines which responsible for load
input data from external memory (either MC or CVSRAM)</p>
</dd>
<dt id="term-WDMA">WDMA<a class="headerlink" href="#term-WDMA" title="Permalink to this term">¶</a></dt><dd><p>Write DMA, instanced in SDP/CDP/PDP/Rubik engines and responsible for write
output data to external memory (either MC or CVSRAM)</p>
</dd>
<dt id="term-CBB">CBB<a class="headerlink" href="#term-CBB" title="Permalink to this term">¶</a></dt><dd><p>Control backbone. System control data path that connected to NVDLA</p>
</dd>
<dt id="term-DBB">DBB<a class="headerlink" href="#term-DBB" title="Permalink to this term">¶</a></dt><dd><p>Data backbone. The path that NVDLA uses to perform DMA to system memory, such as the DRAM interface.</p>
</dd>
<dt id="term-AMBA">AMBA<a class="headerlink" href="#term-AMBA" title="Permalink to this term">¶</a></dt><dd><p>ARM Advanced Microcontroller Bus Architecture. A set of ARM defined bus standards.</p>
</dd>
<dt id="term-AXI">AXI<a class="headerlink" href="#term-AXI" title="Permalink to this term">¶</a></dt><dd><p>Advanced eXtensible Interface. The third generation of AMBA interface defined in the AMBA 3 specification.</p>
</dd>
<dt id="term-CNN">CNN<a class="headerlink" href="#term-CNN" title="Permalink to this term">¶</a></dt><dd><p>Convolutional Neural Network. A class of artificial neural networks.</p>
</dd>
<dt id="term-CSB">CSB<a class="headerlink" href="#term-CSB" title="Permalink to this term">¶</a></dt><dd><p>Configuration Space Bus. (See <a class="reference internal" href="hw/v1/hwarch.html#external-interfaces"><span class="std std-ref">External Interfaces</span></a>.)</p>
</dd>
<dt id="term-DBBIF">DBBIF<a class="headerlink" href="#term-DBBIF" title="Permalink to this term">¶</a></dt><dd><p>The NVDLA interface to the DBB. (See <a class="reference internal" href="hw/v1/hwarch.html#external-interfaces"><span class="std std-ref">External Interfaces</span></a>.)</p>
</dd>
<dt id="term-IRQ">IRQ<a class="headerlink" href="#term-IRQ" title="Permalink to this term">¶</a></dt><dd><p>Interrupt request. (See <a class="reference internal" href="hw/v1/hwarch.html#external-interfaces"><span class="std std-ref">External Interfaces</span></a>.)</p>
</dd>
<dt id="term-SRAMIF">SRAMIF<a class="headerlink" href="#term-SRAMIF" title="Permalink to this term">¶</a></dt><dd><p>The NVDLA interface to an optional high-performance SRAM subsystem.</p>
</dd>
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