diff --git a/hw/dv/sv/cip_lib/cip_base_virtual_sequencer.sv b/hw/dv/sv/cip_lib/cip_base_virtual_sequencer.sv index 473fbd1da1e8aa..1f0c458238be5c 100644 --- a/hw/dv/sv/cip_lib/cip_base_virtual_sequencer.sv +++ b/hw/dv/sv/cip_lib/cip_base_virtual_sequencer.sv @@ -18,55 +18,4 @@ class cip_base_virtual_sequencer #(type CFG_T = cip_base_env_cfg, `uvm_component_new - bit rnd_rst_started; - - - virtual task run_phase(uvm_phase phase); - super.run_phase(phase); - fork - monitor_reset(); - join_none - endtask - - // Method to get the current running sequence - virtual task kill_running_sequence(); - dv_base_vseq running_seq; - - // Get the current sequence (if any) - - $cast(running_seq, get_current_item()); - - if (running_seq != null) begin - // Cast to the specific sequence type if needed - running_seq.kill(); - `uvm_info(get_type_name(), "sequence is killed", UVM_MEDIUM) - end -endtask - - - virtual task monitor_reset(); - forever begin - @(rnd_rst_started) - `uvm_info(`gfn, "Sequencer - reset occurred", UVM_HIGH) - tl_sequencer_h.m_last_req_buffer.delete(); - tl_sequencer_h.m_last_rsp_buffer.delete(); - - foreach(tl_sequencer_hs[i]) begin - tl_sequencer_hs[i].m_last_req_buffer.delete(); - tl_sequencer_hs[i].m_last_rsp_buffer.delete(); - end - - if(!m_req_fifo.is_empty()) begin - m_req_fifo.flush(); - end - - kill_running_sequence(); - - //stop_sequences(); - - rnd_rst_started = 0; - `uvm_info(`gfn, "Sequencer - out of handle the pos reset", UVM_HIGH) - end - endtask - endclass diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv index 0436fd96494a94..7b2dc006f1db34 100644 --- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv +++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv @@ -272,32 +272,23 @@ class cip_base_vseq #( rsp = tl_seq.rsp; - if(rsp != null) begin - if (!write) begin - data = rsp.d_data; - if (check_exp_data && !cfg.under_reset) begin - bit [BUS_DW-1:0] masked_data = data & compare_mask; - exp_data &= compare_mask; - `DV_CHECK_EQ(masked_data, exp_data, $sformatf("addr 0x%0h read out mismatch", addr)) - end - end - if (check_rsp && !cfg.under_reset && tl_intg_err_type == TlIntgErrNone) begin - `DV_CHECK_EQ(rsp.d_error, exp_err_rsp, - $sformatf("unexpected error response for addr: 0x%x", rsp.a_addr)) + if (!write) begin + data = rsp.d_data; + if (check_exp_data && !cfg.under_reset) begin + bit [BUS_DW-1:0] masked_data = data & compare_mask; + exp_data &= compare_mask; + `DV_CHECK_EQ(masked_data, exp_data, $sformatf("addr 0x%0h read out mismatch", addr)) end - - // Expose whether the transaction ran and whether it generated an error. Note that we - // probably only want to do a RAL update if it ran and caused no error. - completed = rsp.rsp_completed; - saw_err = rsp.d_error; - - end else begin - // Expose whether the transaction ran and whether it generated an error. Note that we - // probably only want to do a RAL update if it ran and caused no error. - completed = 0; - saw_err = 0; - end + if (check_rsp && !cfg.under_reset && tl_intg_err_type == TlIntgErrNone) begin + `DV_CHECK_EQ(rsp.d_error, exp_err_rsp, + $sformatf("unexpected error response for addr: 0x%x", rsp.a_addr)) + end + + // Expose whether the transaction ran and whether it generated an error. Note that we + // probably only want to do a RAL update if it ran and caused no error. + completed = rsp.rsp_completed; + saw_err = rsp.d_error; endtask // CIP spec indicates all comportable IPs will have the same standardized interrupt csrs. We can @@ -716,6 +707,7 @@ class cip_base_vseq #( // override this task from {block}_common_vseq if needed virtual task rand_reset_eor_clean_up(); endtask + // Run the given sequence together with a TL errors vseq. Suddenly inject a reset after at most // reset_delay_bound cycles. When we come out of reset, check all CSR values to ensure they are // the documented reset values. @@ -725,13 +717,12 @@ class cip_base_vseq #( `DV_CHECK_FATAL(seq != null) `uvm_info(`gfn, $sformatf("running run_seq_with_rand_reset_vseq for sequence %s", seq.get_full_name()), UVM_MEDIUM) + for (int i = 1; i <= num_times; i++) begin bit ongoing_reset; bit do_read_and_check_all_csrs; bit vseq_done = 1'b0; - - `uvm_info(`gfn, $sformatf("running run_seq_with_rand_reset_vseq iteration %0d/%0d", i, num_times), UVM_LOW) // Arbitration: requests at highest priority granted in FIFO order, so that we can predict @@ -747,9 +738,8 @@ class cip_base_vseq #( end begin : run_stress_seq dv_base_vseq #(RAL_T, CFG_T, COV_T, VIRTUAL_SEQUENCER_T) dv_vseq; - dv_vseq = dv_base_vseq #(RAL_T, CFG_T, COV_T, VIRTUAL_SEQUENCER_T)::type_id::create("dv_vseq"); `downcast(dv_vseq, seq.clone()) - + dv_vseq.do_apply_reset = 0; dv_vseq.set_sequencer(p_sequencer); `DV_CHECK_RANDOMIZE_FATAL(dv_vseq) @@ -790,10 +780,6 @@ class cip_base_vseq #( end join_any - //if(i == num_times) begin - p_sequencer.rnd_rst_started = 1; - //end - // If vseq_done is false then we have issued a reset (the second process in the fork) but // the vseq that we were racing against hasn't noticed the reset and stopped. Killing that // process will cause confusing errors (because there will be some sequence that's waiting @@ -803,16 +789,11 @@ class cip_base_vseq #( // can_reset_with_csr_accesses=1: we expect the vseq to run to completion before the reset // signal is de-asserted. To make things easier to debug if it hasn't done, fail in an // understandable way here. - - - //wait(vseq_done) if (cfg.can_reset_with_csr_accesses) `DV_CHECK_FATAL(vseq_done) - `uvm_info(`gfn, $sformatf("\nStress w/ reset is done for run %0d/%0d", i, num_times), - UVM_HIGH) - disable fork; - + `uvm_info(`gfn, $sformatf("\nStress w/ reset is done for run %0d/%0d", i, num_times), + UVM_LOW) // delay to avoid race condition when sending item and checking no item after reset occur // at the same time #1ps; diff --git a/hw/dv/sv/dv_lib/dv_base_sequencer.sv b/hw/dv/sv/dv_lib/dv_base_sequencer.sv index d934d5440e0ba2..33d43109485815 100644 --- a/hw/dv/sv/dv_lib/dv_base_sequencer.sv +++ b/hw/dv/sv/dv_lib/dv_base_sequencer.sv @@ -20,7 +20,6 @@ class dv_base_sequencer #(type ITEM_T = uvm_sequence_item, CFG_T cfg; - `uvm_component_new function void build_phase(uvm_phase phase); @@ -29,7 +28,4 @@ class dv_base_sequencer #(type ITEM_T = uvm_sequence_item, if (cfg.has_rsp_fifo) rsp_analysis_fifo = new("rsp_analysis_fifo", this); endfunction : build_phase - - - endclass diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv index 449358de203c6b..59bc607bc54cb7 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_base_vseq.sv @@ -12,6 +12,7 @@ class gpio_base_vseq extends cip_base_vseq #( // Delay between consecutive transactions rand uint delay; bit do_init_reset = 1; + constraint delay_c { delay dist {0 :/ 20, [1:5] :/ 40, [6:15] :/ 30, [20:25] :/ 10}; } diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv index 50ff6fab5e9599..5bcf0b0bbc7da3 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv @@ -21,13 +21,10 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; logic [TL_DW-1:0] csr_val; `DV_CHECK_RANDOMIZE_FATAL(this) - //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; // Insert some random delay - cfg.clk_rst_vif.wait_clks(delay); - - + cfg.clk_rst_vif.wait_clks_or_rst(delay); randcase // drive new gpio data in @@ -43,7 +40,7 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; drive_gpio_in(gpio_i); - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; @@ -73,7 +70,7 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; if (!cfg.clk_rst_vif.rst_n) break; // Add single clock cycle delay to avoid update and predict at // the same time due to weak pull-up after undrive_gpio_in() - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv index aaed97f6f03536..21022507158762 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv @@ -23,12 +23,10 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; - //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); - + cfg.clk_rst_vif.wait_clks_or_rst(delay); randcase // drive new gpio data in @@ -47,7 +45,7 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; @@ -95,11 +93,10 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; // Read interrupt state register value begin bit [TL_DW-1:0] reg_rd_data; - //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); // read intr_state register csr_rd(.ptr(ral.intr_state), .value(reg_rd_data)); end diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv index 4b51381453ab04..ab4b377bc70b29 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv @@ -30,7 +30,7 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); `uvm_info(msg_id, $sformatf("delay = %0d", delay), UVM_HIGH) //Skip if a reset is ongoing... @@ -60,7 +60,7 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; cfg.gpio_vif.drive(gpio_i); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay_before_gpio_change, delay_before_gpio_change inside {[1:5]};) - cfg.clk_rst_vif.wait_clks(delay_before_gpio_change); + cfg.clk_rst_vif.wait_clks_or_rst(delay_before_gpio_change); end gpio_tgl_cycle_done = 1'b1; end @@ -73,7 +73,7 @@ class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; - cfg.clk_rst_vif.wait_clks(rd_period); + cfg.clk_rst_vif.wait_clks_or_rst(rd_period); `uvm_info(msg_id, $sformatf("Reading intr_state after %0d more clock cycles", rd_period), UVM_HIGH) diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv index 4b41cf73d37c6e..a388019eee81ab 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv @@ -31,7 +31,7 @@ class gpio_random_dout_din_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; `DV_CHECK_RANDOMIZE_FATAL(this) - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); randcase // drive new gpio data in @@ -51,7 +51,7 @@ class gpio_random_dout_din_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) break; diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv index afa24a93c0d2f8..825a2b713e71e1 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv @@ -26,7 +26,7 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; // Wait for minimum 1 clock cycle initially to avoid reading of data_in // immediately as the first iteration after reset, while data_in prediction // is still being processed - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; @@ -36,7 +36,7 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); randcase // drive new gpio data in @@ -52,7 +52,7 @@ class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; // Wait for one clock cycle for us to read data_in reg reliably - cfg.clk_rst_vif.wait_clks(1); + cfg.clk_rst_vif.wait_clks_or_rst(1); end // long reg write 1: begin diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv index f4cb968184fd80..bfe4d01352f6b6 100644 --- a/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv +++ b/hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv @@ -31,14 +31,12 @@ class gpio_smoke_vseq extends gpio_base_vseq; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans) `uvm_info(`gfn, $sformatf("No. of transactions (gpio_i) = %0d", num_trans), UVM_LOW) - for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin bit [TL_DW-1:0] csr_rd_val; string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)}; `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_i) `uvm_info(msg_id, $sformatf("gpio_i = %0h", gpio_i), UVM_LOW) - cfg.gpio_vif.drive(gpio_i); `ifdef GPIO_ASYNC_ON // If the CDC synchronizer prims are instantiated, it takes 2-3 cycles longer for inputs @@ -51,7 +49,7 @@ class gpio_smoke_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); // Reading data_in will trigger a check inside scoreboard csr_rd(.ptr(ral.data_in), .value(csr_rd_val)); @@ -68,7 +66,6 @@ class gpio_smoke_vseq extends gpio_base_vseq; logic [NUM_GPIOS-1:0] obs_gpio_o; string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)}; - //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; @@ -78,7 +75,6 @@ class gpio_smoke_vseq extends gpio_base_vseq; gpio_o, gpio_o, gpio_oe, gpio_oe), UVM_LOW) ral.direct_out.set(gpio_o); ral.direct_oe.set(gpio_oe); - csr_update(.csr(ral.direct_out)); csr_update(.csr(ral.direct_oe)); // Wait at least one clock cycle @@ -86,7 +82,7 @@ class gpio_smoke_vseq extends gpio_base_vseq; //Skip if a reset is ongoing... if (!cfg.clk_rst_vif.rst_n) return; - cfg.clk_rst_vif.wait_clks(delay); + cfg.clk_rst_vif.wait_clks_or_rst(delay); `uvm_info(msg_id, $sformatf("waiting for %0d clock cycles", delay), UVM_LOW) end endtask : body