From dd8bb93fb21889b8a823bef083d2f246bca37c48 Mon Sep 17 00:00:00 2001 From: Michael Schaffner Date: Thu, 31 Oct 2019 16:02:29 -0700 Subject: [PATCH] [i2c/flash_ctrl/rv_plic] Add KNOWN assertions to all outputs --- hw/ip/flash_ctrl/rtl/flash_ctrl.sv | 9 +++++++++ hw/ip/i2c/rtl/i2c.sv | 16 +++++++++++++++- hw/ip/rv_plic/data/rv_plic.sv.tpl | 6 ++++++ hw/ip/rv_plic/rtl/rv_plic.sv | 6 ++++++ .../ip/rv_plic/rtl/autogen/rv_plic.sv | 6 ++++++ 5 files changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv index 188e88b73b836..e30a6a1022f02 100644 --- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv @@ -475,5 +475,14 @@ module flash_ctrl ( assign unused_scratch = reg2hw.scratch; + // Assertions + `ASSERT_KNOWN(TlKnownO_A, tl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(FlashKnownO_A, flash_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrOpErrorKnownO_A, intr_op_error_o, clk_i, !rst_ni) endmodule diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv index 74a20c0e2cc93..9b60cbe1c90d5 100644 --- a/hw/ip/i2c/rtl/i2c.sv +++ b/hw/ip/i2c/rtl/i2c.sv @@ -88,6 +88,20 @@ module i2c ( assign cio_scl_en_o = ~scl_int; assign cio_sda_en_o = ~sda_int; - `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0) + `ASSERT_KNOWN(scanmodeKnown_A, scanmode_i, clk_i, 0) + `ASSERT_KNOWN(TlKnownO_A, tl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(CioSclKnownO_A, cio_scl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(CioSclEnKnownO_A, cio_scl_en_o, clk_i, !rst_ni) + `ASSERT_KNOWN(CioSdaKnownO_A, cio_sda_o, clk_i, !rst_ni) + `ASSERT_KNOWN(CioSdaEnKnownO_A, cio_sda_en_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrFmtWtmkKnownO_A, intr_fmt_watermark_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrRxWtmkKnownO_A, intr_rx_watermark_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrFmtOflwKnownO_A, intr_fmt_overflow_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrRxOflwKnownO_A, intr_rx_overflow_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrNakKnownO_A, intr_nak_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrSclInterfKnownO_A, intr_scl_interference_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrSdaInterfKnownO_A, intr_sda_interference_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrStretchTimeoutKnownO_A, intr_stretch_timeout_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IntrSdaUnstableKnownO_A, intr_sda_unstable_o, clk_i, !rst_ni) endmodule diff --git a/hw/ip/rv_plic/data/rv_plic.sv.tpl b/hw/ip/rv_plic/data/rv_plic.sv.tpl index 7c9d0fc47eaae..8a88bb971dad3 100644 --- a/hw/ip/rv_plic/data/rv_plic.sv.tpl +++ b/hw/ip/rv_plic/data/rv_plic.sv.tpl @@ -206,4 +206,10 @@ module rv_plic #( .devmode_i (1'b1) ); + // Assertions + `ASSERT_KNOWN(TlKnownO_A, tl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqKnownO_A, irq_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o, clk_i, !rst_ni) + `ASSERT_KNOWN(MsipKnownO_A, msip_o, clk_i, !rst_ni) + endmodule diff --git a/hw/ip/rv_plic/rtl/rv_plic.sv b/hw/ip/rv_plic/rtl/rv_plic.sv index 18376cb234a7a..6b71ba7341980 100644 --- a/hw/ip/rv_plic/rtl/rv_plic.sv +++ b/hw/ip/rv_plic/rtl/rv_plic.sv @@ -227,5 +227,11 @@ module rv_plic #( .devmode_i (1'b1) ); + // Assertions + `ASSERT_KNOWN(TlKnownO_A, tl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqKnownO_A, irq_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o, clk_i, !rst_ni) + `ASSERT_KNOWN(MsipKnownO_A, msip_o, clk_i, !rst_ni) + endmodule diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv index 6307802bf313d..bddd28875a08d 100644 --- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv +++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv @@ -258,4 +258,10 @@ module rv_plic #( .devmode_i (1'b1) ); + // Assertions + `ASSERT_KNOWN(TlKnownO_A, tl_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqKnownO_A, irq_o, clk_i, !rst_ni) + `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o, clk_i, !rst_ni) + `ASSERT_KNOWN(MsipKnownO_A, msip_o, clk_i, !rst_ni) + endmodule