debug module

[mgaletakis]

i am trying to program / load an executable into ibex_demo_system following the commands in github on Arty-A7.
The FPGA is programmed ok but on last command ( ./util/load_demo_system.sh run ./sw/hello_test/hello_test.elf) it seems that openocd cant halt ibex. I am attaching the screen log at the end. Have you see something in the past? any Hint?

Open On-Chip Debugger 0.12.0+dev-00094-gb6b4f9d46 (2023-03-23-14:56)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
force hard breakpoints
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
Info : datacount=2 progbufsize=8
Error: unable to halt hart 0
Error: dmcontrol=0x80000001
Error: dmstatus =0x00000c82
Error: Fatal: Hart 0 failed to halt during examine()
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

[marnovandermaas]

Have you tried running the commands specified in the read me?
https://github.com/lowRISC/ibex-demo-system/blob/main/rtl/system/ibex_demo_system.sv#L394-L409

I don't think we currently generate the .elf file you mention.

[marnovandermaas]

I'm closing this issue, but feel free to reopen this issue or open another issue if you have further questions.