From 9023870bca0a749b1761a30d5249a6520367fc5e Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Mon, 19 Feb 2024 20:37:22 +0000 Subject: [PATCH] Add lcd_backlight IO --- data/pins_sonata.xdc | 1 + rtl/fpga/top_sonata.sv | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/data/pins_sonata.xdc b/data/pins_sonata.xdc index b3629f27..ed6ae3eb 100644 --- a/data/pins_sonata.xdc +++ b/data/pins_sonata.xdc @@ -64,6 +64,7 @@ set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports lcd_dc]; set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports lcd_copi]; set_property -dict { PACKAGE_PIN R5 IOSTANDARD LVCMOS33 } [get_ports lcd_clk]; set_property -dict { PACKAGE_PIN P5 IOSTANDARD LVCMOS33 } [get_ports lcd_cs]; +set_property -dict { PACKAGE_PIN N5 IOSTANDARD LVCMOS33 } [get_ports lcd_backlight]; ## UART set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports ser0_tx]; diff --git a/rtl/fpga/top_sonata.sv b/rtl/fpga/top_sonata.sv index f1a09f22..24f68d7d 100644 --- a/rtl/fpga/top_sonata.sv +++ b/rtl/fpga/top_sonata.sv @@ -22,6 +22,7 @@ module top_sonata ( output logic lcd_copi, output logic lcd_clk, output logic lcd_cs, + output logic lcd_backlight, output logic ser0_tx, input logic ser0_rx, @@ -62,9 +63,6 @@ module top_sonata ( assign nav_sw_n = ~nav_sw; assign user_sw_n = ~user_sw; - // No LCD backlight FPGA IO on v0.2 board, so leave this unconnected - logic lcd_backlight; - ibex_demo_system #( .GpiWidth(13), .GpoWidth(12),