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The output seems to can't represent some situation #8
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You are right! We plan to update the output format and the evaluator to accommodate it. To be specific, the output formate will also indicate the location of vias. Here is an example: Net0 { x_l y_l z_l x_h y_h z_h0 0 0 0 0 0 0 0 0 0 0 1 # a via 0 0 1 0 2 1 0 2 1 0 2 2 # a via ... } We will release the updated output format soon. And our evaluator will also be updated accordingly. Thanks! |
Thanks a lot for your questions!
Really appreciate your questions and patience! |
For the given example in spec:
According to the solution, it seems that the solution is output all covered Gcell but not all used edges since (0, 2) should have a via but the solution does not cover it.
For the following net, red means wires(same as example in spec, horizontal in metal3 and vertical in metal2), blue means pins, green means vias, note that in (1, 2), I don't want to have a via there since it is congestion there. But since Gcell (1, 2, metal2) and (1, 2, metal3) are adjecent Gcell, it will be viewed as a via there, which is not what I want.
Is there any way to solve this?
If I have misunderstood anything, please let me know.
Thanks.
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