Question on incompleted nets

[12zys]

Hi，I have a question：
If all pins of a net are located in the same Gcell, for example(ariane133_51.net)：
FE_OFN64581_n_11
(
[(0, 166, 681)]
[(0, 166, 681)]
)
How should we handle it? If we don't output it, it will be marked as a incompleted net.

[liangrj2014]

Thanks for the question! Can you try generating a via connecting [0, 166, 681] to [1, 166, 681] for this net?

[12zys]

@liangrj2014 Thanks for your response, and it seems like a viable solution, but my concern is whether this is indeed the appropriate method to handle such a situation. Additionally, if we adjust the net to: FE_OFN64581_n_11 ( [(9, 166, 681)] [(9, 166, 681)] ), this method (generating a via connecting [8, 166, 681] to [9, 166, 681] ) would be ineffective. And layer 9 is the top layer, making it impossible to generate vias from layer 9 to a higher layer.