Fix some Chisel 6 warnings

leros-dev · Jul 25, 2024 · f713e45 · f713e45
1 parent a232848
commit f713e45
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/leros/InstrMem.scala b/src/main/scala/leros/InstrMem.scala
@@ -1,6 +1,7 @@
 package leros
 
 import chisel3._
+import chisel3.util._
 import leros.util.Assembler
 
 
@@ -21,5 +22,6 @@ class InstrMem(memAddrWidth: Int, prog: String) extends Module {
   val progMem = VecInit(code.toIndexedSeq.map(_.asUInt(16.W)))
   val memReg = RegInit(0.U(memAddrWidth.W))
   memReg := io.addr
-  io.instr := progMem(memReg)
+  val index = log2Ceil(code.length)
+  io.instr := progMem(memReg(index - 1, 0))
 }