More restructure

src/main/scala/leros/Decode.scala

@@ -15,13 +15,12 @@ class DecodeOut extends Bundle {
   val isRegOpd = Bool()
   val useDecOpd = Bool()
   val nextState = State()
+  val enaByte = Bool()
+  val enaHalf = Bool()
   val isStore = Bool()
   val isStoreInd = Bool()
   val isStoreIndB = Bool()
   val isStoreIndH = Bool()
-  val isLoadInd = Bool()
-  val isLoadIndB = Bool()
-  val isLoadIndH = Bool()
   val isDataAccess = Bool()
   val isBranch = Bool()
   val brType = UInt(4.W)
@@ -43,13 +42,12 @@ object DecodeOut {
     v.isRegOpd := false.B
     v.useDecOpd := false.B
     v.nextState := execute
+    v.enaByte := false.B
+    v.enaHalf := false.B
     v.isStore := false.B
     v.isStoreInd := false.B
     v.isStoreIndB := false.B
     v.isStoreIndH := false.B
-    v.isLoadInd := false.B
-    v.isLoadIndB := false.B
-    v.isLoadIndH := false.B
     v.isDataAccess := false.B
     v.isBranch := false.B
     v.brType := 0.U
@@ -97,6 +95,12 @@ class Decode() extends Module {
   d.operand := sigExt.asUInt
   when (noSext) { d.operand := instr(7, 0) }
 
+  // TODO: here is code duplication, should be merged with code above
+  val instrSignExt = Wire(SInt(32.W))
+  instrSignExt := instr(7, 0).asSInt
+  val off = Wire(SInt(10.W))
+  off := instrSignExt << 2 // default word
+
   switch(instr(15, 8)) {
     is(ADD.U) {
       d.op := add.U
@@ -190,22 +194,26 @@ class Decode() extends Module {
       d.nextState := loadAddr
     }
     is (LDIND.U) {
+      d.nextState := loadInd
       d.isDataAccess := true.B
-      d.isLoadInd := true.B
       d.op := ld.U
       d.enaMask := MaskAll
     }
     is (LDINDB.U) {
+      d.nextState := loadInd
+      d.enaByte := true.B
       d.isDataAccess := true.B
-      d.isLoadIndB := true.B
       d.op := ld.U
       d.enaMask := MaskAll
+      off := instrSignExt
     }
     is(LDINDH.U) {
+      d.nextState := loadInd
+      d.enaHalf := true.B
       d.isDataAccess := true.B
-      d.isLoadIndH := true.B
       d.op := ld.U
       d.enaMask := MaskAll
+      off := instrSignExt << 1
     }
     is (STIND.U) {
       d.isDataAccess := true.B
@@ -214,26 +222,19 @@ class Decode() extends Module {
     is (STINDB.U) {
       d.isDataAccess := true.B
       d.isStoreIndB := true.B
+      off := instrSignExt
     }
     is(STINDH.U) {
       d.isDataAccess := true.B
       d.isStoreIndH := true.B
+      off := instrSignExt << 1
     }
     is(SCALL.U) {
       d.exit := true.B
     }
   }
 
-  // TODO: here is code duplication, should be merged with code above
-  val instrSignExt = Wire(SInt(32.W))
-  instrSignExt := instr(7, 0).asSInt
-  val off = Wire(SInt(10.W))
-  off := instrSignExt << 2 // default word
-  when(d.isLoadIndH || d.isStoreIndH) {
-    off := instrSignExt << 1
-  }.elsewhen(d.isLoadIndB || d.isStoreIndB) {
-    off := instrSignExt
-  }
+
   d.off := off
 
   io.dout := d

src/main/scala/leros/Leros.scala

@@ -12,8 +12,6 @@ import leros.State._
  */
 class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends LerosBase(prog) {
 
-
-
   val alu = Module(new AluAccu(size))
 
   val accu = alu.io.accu
@@ -64,12 +62,14 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends LerosBa
   // ALU connection
   alu.io.op := decReg.op
   alu.io.enaMask := 0.U
-  alu.io.enaByte := decReg.isLoadIndB
-  alu.io.enaHalf := decReg.isLoadIndH
+  // TODO: Maybe this should be in the state machine, instead of decode?
+  // Maybe not.
+  alu.io.enaByte := decReg.enaByte
+  alu.io.enaHalf := decReg.enaHalf
   alu.io.off := effAddrOffReg
   alu.io.din := Mux(decReg.useDecOpd, decReg.operand, dataRead)
 
-  // connection to the external world (test)
+  // connection to the external world (for testing)
   val exit = RegInit(false.B)
   val outReg = RegInit(0.U(32.W))
   io.led := outReg
@@ -92,41 +92,32 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends LerosBa
 
     is (loadAddr) {
       addrReg := dataRead
-      alu.io.enaMask := 0.U
     }
+
+    is (loadInd) {
+      // nothing to be done here
+    }
+
     is (execute) {
 
-      when(decReg.isLoadInd) {
-        // nothing to be done here
-      }
-      when(decReg.isLoadIndB) {
-        // nothing to be done here
-      }
-      when(decReg.isLoadIndH) {
-        // nothing to be done here
-      }
       when(decReg.isStore) {
         dataMem.io.wr := true.B
-        alu.io.enaMask := 0.U
       }
       when(decReg.isStoreInd) {
         dataMem.io.wr := true.B
-        alu.io.enaMask := 0.U
         // TODO: this is a super quick hack to get the LED blinking
         outReg := accu
       }
       when(decReg.isStoreIndB) {
         // wr and wrMask could be set in decode and registered
         dataMem.io.wr := true.B
         dataMem.io.wrMask := "b0001".U << effAddrOffReg
-        alu.io.enaMask := 0.U
         vecAccu(effAddrOffReg) := accu(7, 0)
         dataMem.io.wrData := vecAccu(3) ## vecAccu(2) ## vecAccu(1) ## vecAccu(0)
       }
       when(decReg.isStoreIndH) {
         dataMem.io.wr := true.B
         dataMem.io.wrMask := "b0011".U << effAddrOffReg
-        alu.io.enaMask := 0.U
         vecAccu(effAddrOffReg) := accu(7, 0)
         vecAccu(effAddrOffReg | 1.U) := accu(15, 8)
         dataMem.io.wrData := vecAccu(3) ## vecAccu(2) ## vecAccu(1) ## vecAccu(0)

src/main/scala/leros/State.scala

@@ -3,7 +3,7 @@ package leros
 import chisel3.ChiselEnum
 object State extends ChiselEnum {
   val fetch, execute,
-  loadAddr, loadInd, loadIndB, loadIndH,
+  loadAddr, loadInd,
   store, storeInd, storeindB, storeIndH,
   branch, jal = Value
 }