From b7debc2c6eeccec68cbbb0726d2734c3a4cf7fc5 Mon Sep 17 00:00:00 2001 From: Martin Schoeberl Date: Mon, 13 May 2024 11:05:03 +0200 Subject: [PATCH] Switch to arithmetic right shift --- TODO.md | 1 + asm/test/imm.s | 16 +-- asm/test/lhi.s | 16 +-- asm/test/lhi3.s | 96 ++++++------- asm/test/loadix.s | 148 ++++++++++---------- asm/test/mem.s | 16 +-- asm/test/mem2.s | 48 +++---- asm/test/mem3.s | 18 +-- asm/test/mem4.s | 48 +++---- asm/test/shift.s | 19 +-- src/main/scala/leros/AluAccu.scala | 4 +- src/main/scala/leros/Decode.scala | 4 +- src/main/scala/leros/shared/Constants.scala | 6 +- src/main/scala/leros/sim/LerosSim.scala | 2 +- src/main/scala/leros/util/Assembler.scala | 2 +- src/test/scala/leros/AluAccuTest.scala | 2 +- src/test/scala/leros/CompareTest.scala | 2 - 17 files changed, 224 insertions(+), 224 deletions(-) diff --git a/TODO.md b/TODO.md index 5e4e473..47ebc50 100644 --- a/TODO.md +++ b/TODO.md @@ -2,6 +2,7 @@ - [ ] Get an overview of what is implemented (and add missing to TODO) - [ ] Fix cosimulation issues, Morten does sra and not shr + - [ ] Change to arithmetic shift - [x] Have the Leros simulator as a submodule - [x] Use the simulator in GitHub actions - [ ] Get GitHub CI green diff --git a/asm/test/imm.s b/asm/test/imm.s index 1956abd..8069083 100644 --- a/asm/test/imm.s +++ b/asm/test/imm.s @@ -11,13 +11,13 @@ loadi 0xff loadh2i 0x00 and r2 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra subi 0x56 scall 0 diff --git a/asm/test/lhi.s b/asm/test/lhi.s index 19c85f6..53af5be 100644 --- a/asm/test/lhi.s +++ b/asm/test/lhi.s @@ -1,13 +1,13 @@ // test loadhi loadi 0x12 loadhi 0x23 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra subi 0x23 scall 0 diff --git a/asm/test/lhi3.s b/asm/test/lhi3.s index c305b97..9937e7d 100644 --- a/asm/test/lhi3.s +++ b/asm/test/lhi3.s @@ -10,66 +10,66 @@ store r2 load r2 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra subi 0x23 andi 0xff add r1 store r1 load r2 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra subi 0x45 andi 0xff add r1 store r1 load r2 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra subi 0x78 add r1 store r1 diff --git a/asm/test/loadix.s b/asm/test/loadix.s index 26da35d..bd5e90f 100644 --- a/asm/test/loadix.s +++ b/asm/test/loadix.s @@ -6,10 +6,10 @@ // sign extension? loadi -1 - shr - shr - shr - shr + sra + sra + sra + sra andi 0x0f subi 0x0f add r2 @@ -23,17 +23,17 @@ // high immediate sign extension loadhi 0xff - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra andi 0x80 - shr + sra subi 0x40 add r2 store r2 @@ -41,84 +41,84 @@ // clear upper bytes after sign extension loadi -1 loadhi 0x00 - shr + sra subi 0x7f add r2 store r2 // 3rd byte loadh2i 0x12 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra subi 0x12 add r2 store r2 // 3rd byte sign extension loadh2i 0xff - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra andi 0x80 - shr + sra subi 0x40 add r2 store r2 // 4th byte loadh3i 0x34 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra subi 0x34 add r2 store r2 @@ -126,4 +126,4 @@ // final result loadi 1 load r2 - scall 0 \ No newline at end of file + scall 0 diff --git a/asm/test/mem.s b/asm/test/mem.s index 9a56e93..f33ed0f 100644 --- a/asm/test/mem.s +++ b/asm/test/mem.s @@ -14,14 +14,14 @@ stind 0 loadi 0x01 ldind 0 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra subi 0x34 andi 0xff add r1 diff --git a/asm/test/mem2.s b/asm/test/mem2.s index 8093735..641bbaa 100644 --- a/asm/test/mem2.s +++ b/asm/test/mem2.s @@ -28,14 +28,14 @@ store r1 ldind 0 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra andi 0xff subi 0x34 add r1 @@ -62,22 +62,22 @@ loadi 0x3e stindb 2 ldind 0 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra andi 0xff subi 0x3e add r1 diff --git a/asm/test/mem3.s b/asm/test/mem3.s index f02d2b3..5cdd614 100644 --- a/asm/test/mem3.s +++ b/asm/test/mem3.s @@ -7,15 +7,15 @@ stind 0 loadi 0x01 ldindb 0 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra andi 0xff - shr + sra subi 0x7f scall 0 diff --git a/asm/test/mem4.s b/asm/test/mem4.s index a2d949b..3c21572 100644 --- a/asm/test/mem4.s +++ b/asm/test/mem4.s @@ -19,14 +19,14 @@ store r1 ldindh 0 - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra andi 0xff subi 0x34 add r1 @@ -41,22 +41,22 @@ loadi 0xcc stindb 1 ldindh 0 - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr - shr + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra + sra andi 0x0f subi 0x0f add r1 diff --git a/asm/test/shift.s b/asm/test/shift.s index ce9f612..7d71fcb 100644 --- a/asm/test/shift.s +++ b/asm/test/shift.s @@ -1,23 +1,24 @@ -// test shr +// test sra +// TODO: test sign extension loadi 0 store r2 loadi 0x01 - shr + sra add r2 store r2 loadi 0x02 - shr - shr + sra + sra add r2 store r2 loadi 0x32 - shr - shr - shr - shr + sra + sra + sra + sra subi 0x03 add r2 store r2 @@ -27,4 +28,4 @@ // final result loadi 1 load r2 - scall 0 \ No newline at end of file + scall 0 diff --git a/src/main/scala/leros/AluAccu.scala b/src/main/scala/leros/AluAccu.scala index 6879f58..a16e458 100644 --- a/src/main/scala/leros/AluAccu.scala +++ b/src/main/scala/leros/AluAccu.scala @@ -47,8 +47,8 @@ class AluAccu(size: Int) extends Module { is(xor.U) { res := a ^ b } - is(shr.U) { - res := a >> 1 + is(sra.U) { + res := a(31) ## a(31, 1) } is(ld.U) { res := b diff --git a/src/main/scala/leros/Decode.scala b/src/main/scala/leros/Decode.scala index 1fb0200..29da529 100644 --- a/src/main/scala/leros/Decode.scala +++ b/src/main/scala/leros/Decode.scala @@ -117,8 +117,8 @@ class Decode() extends Module { d.enaMask := MaskAll d.useDecOpd := true.B } - is(SHR.U) { - d.op := shr.U + is(SRA.U) { + d.op := sra.U d.enaMask := MaskAll } is(LD.U) { diff --git a/src/main/scala/leros/shared/Constants.scala b/src/main/scala/leros/shared/Constants.scala index 2973e76..4761dcb 100644 --- a/src/main/scala/leros/shared/Constants.scala +++ b/src/main/scala/leros/shared/Constants.scala @@ -7,7 +7,7 @@ package leros.shared |000010-1| addi | |000011-0| sub | |000011-1| subi | -|00010---| shr | +|00010---| sra | |00011---| - | |00100000| load | |00100001| loadi | @@ -51,7 +51,7 @@ object Constants { val ADDI = 0x09 val SUB = 0x0c val SUBI = 0x0d - val SHR = 0x10 + val SRA = 0x10 val LD = 0x20 val LDI = 0x21 val AND = 0x22 @@ -91,5 +91,5 @@ object Constants { val or = 4 val xor = 5 val ld = 6 - val shr = 7 + val sra = 7 } diff --git a/src/main/scala/leros/sim/LerosSim.scala b/src/main/scala/leros/sim/LerosSim.scala index 1607b60..9bbf9f8 100644 --- a/src/main/scala/leros/sim/LerosSim.scala +++ b/src/main/scala/leros/sim/LerosSim.scala @@ -73,7 +73,7 @@ class LerosSim(prog: String) { case ADDI => accu = accu + sext(opd) case SUB => accu = accu - regVal case SUBI => accu = accu - sext(opd) - case SHR => accu = accu >>> 1 + case SRA => accu = accu >> 1 case LD => accu = regVal case LDI => accu = sext(opd) case LDHI => accu = (accu & 0xff) + ((opd << 24) >> 16) diff --git a/src/main/scala/leros/util/Assembler.scala b/src/main/scala/leros/util/Assembler.scala index 5c0ac90..a68375f 100644 --- a/src/main/scala/leros/util/Assembler.scala +++ b/src/main/scala/leros/util/Assembler.scala @@ -85,7 +85,7 @@ object Assembler { case "andi" => (ANDI << 8) + toInt(tokens(1)) case "ori" => (ORI << 8) + toInt(tokens(1)) case "xori" => (XORI << 8) + toInt(tokens(1)) - case "shr" => (SHR << 8) + case "sra" => (SRA << 8) case "loadi" => (LDI << 8) + toInt(tokens(1)) case "loadhi" => (LDHI << 8) + toInt(tokens(1)) case "loadh2i" => (LDH2I << 8) + toInt(tokens(1)) diff --git a/src/test/scala/leros/AluAccuTest.scala b/src/test/scala/leros/AluAccuTest.scala index 15c11ea..98f2830 100644 --- a/src/test/scala/leros/AluAccuTest.scala +++ b/src/test/scala/leros/AluAccuTest.scala @@ -21,7 +21,7 @@ class AluAccuTest extends AnyFlatSpec with ChiselScalatestTester { case 4 => a | b case 5 => a ^ b case 6 => b - case 7 => a >>> 1 + case 7 => a >> 1 case _ => -123 // This shall not happen } } diff --git a/src/test/scala/leros/CompareTest.scala b/src/test/scala/leros/CompareTest.scala index 6214f7d..50edfa7 100644 --- a/src/test/scala/leros/CompareTest.scala +++ b/src/test/scala/leros/CompareTest.scala @@ -56,8 +56,6 @@ class CompareTest extends AnyFlatSpec with ChiselScalatestTester { assert(maxCycles > 0, "Running out of cycles") } val hw = removeDuplicates(l.toSeq) - Predef.println(swsim) - Predef.println(hw) assert(swsim.length == hw.length) for (v <- swsim.zip(hw)) { assert(v._1 == v._2)