diff --git a/build.sbt b/build.sbt
index cf2a66d..53bbee2 100644
--- a/build.sbt
+++ b/build.sbt
@@ -1,4 +1,4 @@
-scalaVersion := "2.13.10"
+scalaVersion := "2.13.14"
 
 scalacOptions ++= Seq(
   "-deprecation",
@@ -12,9 +12,26 @@ scalacOptions ++= Seq(
 // These appear because chisel use a language feature that's not available in
 // all scala implementations.
 
-// Chisel 3.5
-addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.6" cross CrossVersion.full)
-libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.6"
-libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.6"
+// Chisel 3.5 tested
+/*
+val chiselVersion = "3.6.1"
+addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)
+libraryDependencies += "edu.berkeley.cs" %% "chisel3" % chiselVersion
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.1"
+ */
 
-libraryDependencies += "io.github.chiselverify" % "chiselverify" % "0.4.0"
+val chiselVersion = "5.3.0"
+addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
+libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "5.0.2"
+
+/*
+interesting warnings with Chisel 6
+
+val chiselVersion = "6.5.0"
+addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
+libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
+libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "6.0.0"
+*/
+
+// libraryDependencies += "io.github.chiselverify" % "chiselverify" % "0.4.0"
diff --git a/ep4ce115f29.cfg b/ep4ce115f29.cfg
index 35a1053..28c1514 100644
--- a/ep4ce115f29.cfg
+++ b/ep4ce115f29.cfg
@@ -1,4 +1,5 @@
 adapter driver usb_blaster
+usb_blaster_vid_pid 0x09fb 0x6010 0x09fb 0x6810
 usb_blaster lowlevel_driver ftdi
 set CHIPNAME ep4ce115f29
 set FPGA_TAPID 0x020f10dd
diff --git a/src/test/scala/leros/AluTop.scala b/src/test/scala/leros/AluTop.scala
index 5dfaaf4..b929a26 100644
--- a/src/test/scala/leros/AluTop.scala
+++ b/src/test/scala/leros/AluTop.scala
@@ -26,5 +26,5 @@ class AluTop(size: Int) extends Module {
 }
 object AluTop extends App {
   throw new Exception("Adapt for new AluAccu")
-  (new chisel3.stage.ChiselStage).emitVerilog(new AluTop(32), Array("--target-dir", "generated"))
+  emitVerilog(new AluTop(32), Array("--target-dir", "generated"))
 }
\ No newline at end of file