From 1eb31a71585c285e2b193cf9d9a031912442fc30 Mon Sep 17 00:00:00 2001
From: Martin Schoeberl <martin@jopdesign.com>
Date: Thu, 5 Sep 2024 23:16:52 +0200
Subject: [PATCH] Use Leros.sv

---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index aa49b4f..b83e7d4 100644
--- a/Makefile
+++ b/Makefile
@@ -54,11 +54,12 @@ list-swsim:
 # Synthesize and copy targets
 
 # does not work from Makefile, C & P into shell
+# Path for chipdesign1 (not helena)
 synpath:
 	source /home/shared/Xilinx/Vivado/2017.4/settings64.sh
 
 synth:
-	./vivado_synth -t Leros -p xc7a100tcsg324-1 -x nexysA7.xdc -o build generated/Leros.v
+	./vivado_synth -t Leros -p xc7a100tcsg324-1 -x nexysA7.xdc -o build generated/Leros.sv
 
 cp-bit:
 	-mkdir build