The low noise amplifier is controlled by setting specific fields in registers defined in file soc/sens_reg.h.
Basing on original technical reference manual, processing of voltage signal on SENSOR_VP and SENSOR_VN inputs of ESP32, up to providing raw digital value on ADC's output, may be split into four phases:
- Stage 1: charge external sampling capacitors
- Stage 2: intermediate stage, the sampling capacitors are disconnected from both the input and internal capacitors
- Stage 3: charge transfer from external sampling capacitors to the internal capacitors
- Stage 4: ADC conversion
Duration of each phase is configurable.
Below is visualization of positions of internal switches responsible for sampling the voltage signal connected to SENSOR_VP and SENSOR_VN inputs and transferring it inside the LNA and to the ADC.
Internal capacitors Cin are bypassed by closing anp_rst_fb switches and external capacitors C are charged from signal connected to Vin.
This is intermediate stage when both anp_rst_fb switches are opened.
The switch amp_short_ref is closed to connect external capacitors together and effectively short Vin input signal. The charge on external capacitors C can now be transferred to internal capacitors Cin.
Finally the signal on LNA's output is converted by the ADC and may be read by digital part of ESP32.
Duration of first three stages described above is configurable by setting SENS_SAR_AMP_WAITn fields of SENS_SAR_MEAS_WAITm_REG registers. This setting is critical to provide enough time to saturate charge on external and then internal capacitors. Reading the voltage "on the slope" may not provide repeatable readings.
Transferring between stages is controlled by FSM. The stage duration is provided in cycles. The cycle counters are driven by RTC fast clock running at 8 MHz and the single cycle duration is 0.125 ns.