me_match_v1_0_S00_AXI.v

`timescale 1 ns / 1 ps

	module me_match_v1_0_S00_AXI #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line

		// Width of S_AXI data bus
		parameter integer C_S_AXI_DATA_WIDTH	= 32,
		// Width of S_AXI address bus
		parameter integer C_S_AXI_ADDR_WIDTH	= 7
	)
	(
		// Users to add ports here

		// User ports ends
		// Do not modify the ports beyond this line

		// Global Clock Signal
		input wire  S_AXI_ACLK,
		// Global Reset Signal. This Signal is Active LOW
		input wire  S_AXI_ARESETN,
		// Write address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		// Write channel Protection type. This signal indicates the
    		// privilege and security level of the transaction, and whether
    		// the transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_AWPROT,
		// Write address valid. This signal indicates that the master signaling
    		// valid write address and control information.
		input wire  S_AXI_AWVALID,
		// Write address ready. This signal indicates that the slave is ready
    		// to accept an address and associated control signals.
		output wire  S_AXI_AWREADY,
		// Write data (issued by master, acceped by Slave) 
		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		// Write strobes. This signal indicates which byte lanes hold
    		// valid data. There is one write strobe bit for each eight
    		// bits of the write data bus.    
		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		// Write valid. This signal indicates that valid write
    		// data and strobes are available.
		input wire  S_AXI_WVALID,
		// Write ready. This signal indicates that the slave
    		// can accept the write data.
		output wire  S_AXI_WREADY,
		// Write response. This signal indicates the status
    		// of the write transaction.
		output wire [1 : 0] S_AXI_BRESP,
		// Write response valid. This signal indicates that the channel
    		// is signaling a valid write response.
		output wire  S_AXI_BVALID,
		// Response ready. This signal indicates that the master
    		// can accept a write response.
		input wire  S_AXI_BREADY,
		// Read address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		// Protection type. This signal indicates the privilege
    		// and security level of the transaction, and whether the
    		// transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_ARPROT,
		// Read address valid. This signal indicates that the channel
    		// is signaling valid read address and control information.
		input wire  S_AXI_ARVALID,
		// Read address ready. This signal indicates that the slave is
    		// ready to accept an address and associated control signals.
		output wire  S_AXI_ARREADY,
		// Read data (issued by slave)
		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		// Read response. This signal indicates the status of the
    		// read transfer.
		output wire [1 : 0] S_AXI_RRESP,
		// Read valid. This signal indicates that the channel is
    		// signaling the required read data.
		output wire  S_AXI_RVALID,
		// Read ready. This signal indicates that the master can
    		// accept the read data and response information.
		input wire  S_AXI_RREADY
	);

	// AXI4LITE signals
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;

	// Example-specific design signals
	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
	// ADDR_LSB is used for addressing 32/64 bit registers/memories
	// ADDR_LSB = 2 for 32 bits (n downto 2)
	// ADDR_LSB = 3 for 64 bits (n downto 3)
	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 4;
	//----------------------------------------------
	//-- Signals for user logic register space example
	//------------------------------------------------
	//-- Number of Slave Registers 17
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg4;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg8;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg9;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg10;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg11;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg12;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg13;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg14;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg15;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg16;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;

    //*************************************************
    	
    
    reg [2:0] st;
    localparam [2:0] IDLE=0, SA=1, COMPUTE=2, WAIT_DONE=3, DONE=4;
    
    reg [8*48-1:0] sa_bank[0:47] ;
    reg [127:0] cb_bank[0:15];
    reg [16*8-1:0] sa_buf [16-1:0] ; 
    wire [16*8-1:0] updata_data ; 
    reg [3:0] update_cnt ; 
    reg [2:0] latency_cnt ; 
    reg [5:0] real_x,real_y,updata_data_x,updata_data_y,compute_cnt;
    reg [20:0] total_sad;
    reg [31:0] min_x, min_y,min_sad;
    integer i;
    parameter latency = 3 ;
    wire [8:0]diff[0:255] ; 
    reg [8:0]abs_diff[0:255];
    reg [23:0] sum_level_0[0:15];
    
    genvar ii,j;
    //*****************************************************
    
    

	// I/O Connections assignments

	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;
	// Implement axi_awready generation
	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
	// de-asserted when reset is low.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin
	          // slave is ready to accept write address when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       

	// Implement axi_awaddr latching
	// This process is used to latch the address when both 
	// S_AXI_AWVALID and S_AXI_WVALID are valid. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin
	          // Write Address latching 
	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       

	// Implement axi_wready generation
	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
	// de-asserted when reset is low. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin
	          // slave is ready to accept write data when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       

	// Implement memory mapped register select and write logic generation
	// The write data is accepted and written to memory mapped registers when
	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
	// select byte enables of slave registers while writing.
	// These registers are cleared when reset (active low) is applied.
	// Slave register write enable is asserted when valid address and data are available
	// and the slave is ready to accept the write address and write data.
	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
    
    	// Add user logic here
	
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_reg0 <= 0;
	      slv_reg1 <= 0;
	      slv_reg2 <= 0;
	      slv_reg3 <= 0;
	      slv_reg4 <= 0;
	      slv_reg5 <= 0;
	      slv_reg6 <= 0;
	      slv_reg7 <= 0;
	      slv_reg8 <= 0;
	      slv_reg9 <= 0;
	      slv_reg10 <= 0;
	      slv_reg11 <= 0;
	      slv_reg12 <= 0;
	      slv_reg13 <= 0;
	      slv_reg14 <= 0;
	      slv_reg15 <= 0;
	      slv_reg16 <= 0;
	    end 
	  else begin
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          5'h00: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 0
	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                    if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][383-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
                    else if(slv_reg12>47&&slv_reg12<64) begin
                        cb_bank[slv_reg12-48][127-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end 
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][383-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
                  // else if(slv_reg12>47&&slv_reg12<64) begin
                   // cb_bank[slv_reg12][127-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h01: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 1
	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                    if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][351-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
                    else if(slv_reg12>47&&slv_reg12<64) begin
                        cb_bank[slv_reg12-48][95-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][351-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
                  // else if(slv_reg12>47&&slv_reg12<64) begin
                   // cb_bank[slv_reg12][95-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
               end
	          5'h02: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 2
	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                    if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][319-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
                    else if(slv_reg12>47&&slv_reg12<64) begin
                        cb_bank[slv_reg12-48][63-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][319-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
                  // else if(slv_reg12>47&&slv_reg12<64) begin
                   // cb_bank[slv_reg12][63-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
               end
	          5'h03: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 3
	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                    if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][287-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
                    else if(slv_reg12>47&&slv_reg12<64) begin
                        cb_bank[slv_reg12-48][31-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][287-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
                  // else if(slv_reg12>47&&slv_reg12<64) begin
                   // cb_bank[slv_reg12][31-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h04: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 4
	                slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][255-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
                    
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][255-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h05: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 5
	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][223-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][223-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h06: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 6
	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][191-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][191-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h07: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 7
	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][159-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][159-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h08: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 8
	                slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][127-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][127-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h09: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 9
	                slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][95-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                  // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][95-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end
              end
	          5'h0A: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 10
	                slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][63-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                 // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][63-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end 
              end
	          5'h0B: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 11
	                slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     if(slv_reg12<=47) begin
                        sa_bank[slv_reg12][31-(byte_index*8)-:8] <= S_AXI_WDATA[(byte_index*8+7) -: 8];
                    end
	              end  
                // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][31-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end 
              end
	          5'h0C: begin
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 12
	                slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
                     
	              end  
				 // if(slv_reg12<=47) begin
                    // sa_bank[slv_reg12][31-:32] <= {S_AXI_WDATA[7:0],S_AXI_WDATA[15:8],S_AXI_WDATA[23:16],S_AXI_WDATA[31:24]};
                  // end  
              end
	          5'h0D:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 13
	                slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0E:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 14
	                slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h0F:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 15
	                slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          5'h10:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
	                // Respective byte enables are asserted as per write strobes 
	                // Slave register 16
	                slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          default : begin
	                      slv_reg0 <= slv_reg0;
	                      slv_reg1 <= slv_reg1;
	                      slv_reg2 <= slv_reg2;
	                      slv_reg3 <= slv_reg3;
	                      slv_reg4 <= slv_reg4;
	                      slv_reg5 <= slv_reg5;
	                      slv_reg6 <= slv_reg6;
	                      slv_reg7 <= slv_reg7;
	                      slv_reg8 <= slv_reg8;
	                      slv_reg9 <= slv_reg9;
	                      slv_reg10 <= slv_reg10;
	                      slv_reg11 <= slv_reg11;
	                      slv_reg12 <= slv_reg12;
	                      slv_reg13 <= slv_reg13;
	                      slv_reg14 <= slv_reg14;
	                      slv_reg15 <= slv_reg15;
	                      slv_reg16 <= slv_reg16;
	                    end
	        endcase
	      end
		else begin
			slv_reg13 <= (st==DONE)? 32'b0:slv_reg13; 
            slv_reg14 <= (st==DONE)? min_x-16:slv_reg14; 
            slv_reg15 <= (st==DONE)? min_y-16:slv_reg15; 
            slv_reg16 <= (st==DONE)? min_sad:slv_reg16; 
		end
	  end
	end    

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin
	          // indicates a valid write response is available
	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0; // 'OKAY' response 
	        end                   // work error responses in future
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 
	            //check if bready is asserted while bvalid is high) 
	            //(there is a possibility that bready is always asserted high)   
	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin
	          // indicates that the slave has acceped the valid read address
	          axi_arready <= 1'b1;
	          // Read address latching
	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin
	          // Valid read data is available at the read data bus
	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0; // 'OKAY' response
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin
	          // Read data is accepted by the master
	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    

	// Implement memory mapped register select and read logic generation
	// Slave register read enable is asserted when valid address is available
	// and the slave is ready to accept the read address.
	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin
	      // Address decoding for reading registers
	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        5'h00   : reg_data_out <= slv_reg0;
	        5'h01   : reg_data_out <= slv_reg1;
	        5'h02   : reg_data_out <= slv_reg2;
	        5'h03   : reg_data_out <= slv_reg3;
	        5'h04   : reg_data_out <= slv_reg4;
	        5'h05   : reg_data_out <= slv_reg5;
	        5'h06   : reg_data_out <= slv_reg6;
	        5'h07   : reg_data_out <= slv_reg7;
	        5'h08   : reg_data_out <= slv_reg8;
	        5'h09   : reg_data_out <= slv_reg9;
	        5'h0A   : reg_data_out <= slv_reg10;
	        5'h0B   : reg_data_out <= slv_reg11;
	        5'h0C   : reg_data_out <= slv_reg12;
	        5'h0D   : reg_data_out <= slv_reg13;
	        5'h0E   : reg_data_out <= slv_reg14;
	        5'h0F   : reg_data_out <= slv_reg15;
	        5'h10   : reg_data_out <= slv_reg16;
	        default : reg_data_out <= 0;
	      endcase
	end

	// Output register or memory read data
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    
	      // When there is a valid read address (S_AXI_ARVALID) with 
	      // acceptance of read address by the slave (axi_arready), 
	      // output the read dada 
	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;     // register read data
	        end   
	    end
	end    

	// **********************************************************//


	assign updata_data = sa_bank[updata_data_y][383-updata_data_x*8-:8*16];  

	always @ (posedge S_AXI_ACLK)
	begin 
		if(st==SA || st==COMPUTE)begin 
			sa_buf[15] <= updata_data ; 
			for(i=0;i<=14;i=i+1)begin 
				sa_buf[i] <= sa_buf[i+1] ; 
			end 
		end 
	end 
always @ (posedge S_AXI_ACLK)
begin 
	if(S_AXI_ARESETN == 1'b0 )begin
		update_cnt <= 0 ; 
	end 
	else if(st==SA)begin 
		update_cnt <= update_cnt+1 ;
	end 
	else if(st==COMPUTE) begin 
		update_cnt <= 0 ; 
	end 
end 

always @ (posedge S_AXI_ACLK)
begin 
	if(S_AXI_ARESETN == 1'b0 )begin 
		st <= IDLE ; 
	end 
	else begin 
		case(st)
			IDLE : 
				if(slv_reg13!=0) st <= SA ; 	
				else st <= IDLE ; 	
			SA :
				if(update_cnt==15) st <= COMPUTE ; 
				else st <= SA ; 	
			COMPUTE : 
				if(updata_data_x==31 && updata_data_y==46) st <= WAIT_DONE ; 
				else if(compute_cnt==34) st <= SA ;  
				else st <= COMPUTE ; 
			WAIT_DONE : 
				if(real_x==31 && real_y==31) st <= DONE ; 
				else st <= WAIT_DONE ; 
			DONE : 
				st <= IDLE ; 	
			default :
				st <= IDLE ; 
		endcase 
	end 
end 

always @ (posedge S_AXI_ACLK)
begin 
	if(S_AXI_ARESETN == 1'b0 )begin 
		compute_cnt <= 0 ;
	end 
	else if(st == SA) begin 
		compute_cnt <= 0 ;
	end 
	else if(st == COMPUTE)begin 
		compute_cnt <= compute_cnt + 1 ; 
	end 
end 



always @ (posedge S_AXI_ACLK)
begin 
	if(S_AXI_ARESETN == 1'b0 )begin 
		updata_data_x <= 0 ; 
		updata_data_y <= 0 ; 
	end 
	else begin 
		case(st)
			IDLE : begin
				updata_data_x <= 0 ; 
				updata_data_y <= 0 ;
				end
			SA : begin
				updata_data_x <= updata_data_x ; 
				updata_data_y <= updata_data_y +1  ;	
				end
			COMPUTE : 
				if(compute_cnt==34)begin 
					updata_data_x <= updata_data_x + 1; 
					updata_data_y <= 0 ;
				end 
				else begin 	
					updata_data_x <= updata_data_x ; 
					updata_data_y <= (updata_data_y==47)? 47 : updata_data_y +1  ;		
				end  	
			default :
				begin 
					updata_data_x <= updata_data_x ; 
					updata_data_y <= updata_data_y ;
				end 
		endcase 
	end 
end 

always @ (posedge S_AXI_ACLK)
begin 
	if(st==SA)begin 
		latency_cnt <= 0 ; 
	end 
	else if(st==COMPUTE)begin 
		if(latency_cnt < latency)
			latency_cnt<= latency_cnt + 1  ;  
	end 
end 

always @ (posedge S_AXI_ACLK)
begin 
	if(st==IDLE)begin 
		real_x <= 0; 	//cordinate x 
		real_y <= 0; 	//cordinate y
	end 
	else if((st==COMPUTE || st == WAIT_DONE)&& latency_cnt==latency)begin 
		if(real_y==31)begin 
			real_y <= 0; 
			real_x <= real_x + 1 ;  
 		end 
		else begin
			real_y <= real_y + 1 ;
			real_x <= real_x ;  
		end 
	end 
end 

always @ (posedge S_AXI_ACLK)
begin 
	if(st==IDLE)begin 
		min_x <= 0; 	
		min_y <= 0; 
		min_sad <= {32{1'b1}} ; 
	end 
	else if((st==COMPUTE || st==WAIT_DONE)&& latency_cnt==latency) begin 
        if(total_sad<=min_sad) begin
            if(total_sad<min_sad) begin
                min_sad<=total_sad;
                min_x<=real_x;
                min_y<=real_y;	
            end
            else if(total_sad==min_sad) begin
                if((real_y > min_y)|| ((real_y == min_y) && (real_x >= min_x))) begin
                    min_sad<=total_sad;
                    min_x<=real_x;
                    min_y<=real_y;	
                end
            end
        end
    
    
		/*if(total_sad==min_sad ) begin
			if((real_y > min_y)|| ((real_y == min_y) && (real_x > min_x))) begin
				min_sad<=total_sad;
				min_x<=real_x;
				min_y<=real_y;
			end
		end
		else if(total_sad<min_sad ) begin
			min_sad<=total_sad;
			min_x<=real_x;
			min_y<=real_y;		
		end */
	end 
end 


generate
	for(ii=0;ii<16;ii=ii+1) begin
		for(j=0;j<16;j=j+1) begin
			assign diff[ii*16+j] = sa_buf[ii][127-j*8-:8] - cb_bank[ii][127-j*8-:8];
		end
	end
endgenerate

integer jdx;
always @(posedge S_AXI_ACLK) begin
	for (jdx = 0; jdx < 256; jdx = jdx + 1) begin
      if (S_AXI_ARESETN == 1'b0)
        abs_diff[jdx] <= 0;
      else
        abs_diff[jdx] <= (diff[jdx][8] == 1'b1)? -diff[jdx] : diff[jdx];
    end
end

integer idx;
always @(posedge S_AXI_ACLK) begin
	for (idx = 0; idx < 16; idx = idx + 1)
	begin
	  sum_level_0[idx] <= abs_diff[idx*16] + 
						  abs_diff[idx*16+1 ]+
						  abs_diff[idx*16+2 ]+
						  abs_diff[idx*16+3 ]+
						  abs_diff[idx*16+4 ]+
						  abs_diff[idx*16+5 ]+
						  abs_diff[idx*16+6 ]+
						  abs_diff[idx*16+7 ]+
						  abs_diff[idx*16+8 ]+
						  abs_diff[idx*16+9 ]+
						  abs_diff[idx*16+10]+
						  abs_diff[idx*16+11]+
						  abs_diff[idx*16+12]+
						  abs_diff[idx*16+13]+
						  abs_diff[idx*16+14]+
						  abs_diff[idx*16+15];
	end
end

always @(posedge S_AXI_ACLK) begin

	  total_sad <= sum_level_0[0 ] + 
				   sum_level_0[1 ]+
				   sum_level_0[2 ]+
				   sum_level_0[3 ]+
				   sum_level_0[4 ]+
				   sum_level_0[5 ]+
				   sum_level_0[6 ]+
				   sum_level_0[7 ]+
				   sum_level_0[8 ]+
				   sum_level_0[9 ]+
				   sum_level_0[10]+
				   sum_level_0[11]+
				   sum_level_0[12]+
				   sum_level_0[13]+
				   sum_level_0[14]+
				   sum_level_0[15];

end

	
	endmodule