ASMI.v

// megafunction wizard: %ALTASMI_PARALLEL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altasmi_parallel 

// ============================================================
// File Name: ASMI.v
// Megafunction Name(s):
// 			altasmi_parallel
//
// Simulation Library Files(s):
// 			altera_mf;cycloneii;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************


//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//altasmi_parallel CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" EPCS_TYPE="EPCS16" PAGE_SIZE=256 PORT_BULK_ERASE="PORT_USED" PORT_FAST_READ="PORT_UNUSED" PORT_ILLEGAL_ERASE="PORT_USED" PORT_ILLEGAL_WRITE="PORT_USED" PORT_RDID_OUT="PORT_UNUSED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_RDID="PORT_UNUSED" PORT_READ_SID="PORT_USED" PORT_READ_STATUS="PORT_UNUSED" PORT_SECTOR_ERASE="PORT_USED" PORT_SECTOR_PROTECT="PORT_USED" PORT_SHIFT_BYTES="PORT_USED" PORT_WREN="PORT_USED" PORT_WRITE="PORT_USED" USE_EAB="ON" addr bulk_erase busy clkin data_valid datain dataout epcs_id illegal_erase illegal_write rden read read_sid sector_erase sector_protect shift_bytes wren write INTENDED_DEVICE_FAMILY="Cyclone III" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 9.1SP2 cbx_a_gray2bin 2010:03:24:20:43:42:SJ cbx_a_graycounter 2010:03:24:20:43:42:SJ cbx_altasmi_parallel 2010:03:24:20:43:42:SJ cbx_altdpram 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cyclone 2010:03:24:20:43:43:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_fifo_common 2010:03:24:20:43:42:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_scfifo 2010:03:24:20:43:43:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = a_graycounter 5 cycloneii_asmiblock 1 lpm_compare 2 lpm_counter 2 lut 76 mux21 1 reg 134 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module  ASMI_altasmi_parallel_cv82
	( 
	addr,
	bulk_erase,
	busy,
	clkin,
	data_valid,
	datain,
	dataout,
	epcs_id,
	illegal_erase,
	illegal_write,
	rden,
	read,
	read_sid,
	sector_erase,
	sector_protect,
	shift_bytes,
	wren,
	write) /* synthesis synthesis_clearbox=2 */;
	input   [23:0]  addr;
	input   bulk_erase;
	output   busy;
	input   clkin;
	output   data_valid;
	input   [7:0]  datain;
	output   [7:0]  dataout;
	output   [7:0]  epcs_id;
	output   illegal_erase;
	output   illegal_write;
	input   rden;
	input   read;
	input   read_sid;
	input   sector_erase;
	input   sector_protect;
	input   shift_bytes;
	input   wren;
	input   write;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   bulk_erase;
	tri0   [7:0]  datain;
	tri0   read;
	tri0   read_sid;
	tri0   sector_erase;
	tri0   sector_protect;
	tri0   shift_bytes;
	tri1   wren;
	tri0   write;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  [2:0]   wire_addbyte_cntr_q;
	wire  [2:0]   wire_gen_cntr_q;
	wire  [1:0]   wire_spstage_cntr_q;
	wire  [1:0]   wire_stage_cntr_q;
	wire  [1:0]   wire_wrstage_cntr_q;
	wire  wire_cycloneii_asmiblock2_data0out;
	reg	add_msb_reg;
	wire	wire_add_msb_reg_ena;
	wire	[23:0]	wire_addr_reg_d;
	reg	[23:0]	addr_reg;
	wire	[23:0]	wire_addr_reg_ena;
	wire	[7:0]	wire_asmi_opcode_reg_d;
	reg	[7:0]	asmi_opcode_reg;
	wire	[7:0]	wire_asmi_opcode_reg_ena;
	reg	buf_empty_reg;
	reg	bulk_erase_reg;
	wire	wire_bulk_erase_reg_ena;
	reg	busy_det_reg;
	reg	clr_addmsb_reg;
	reg	clr_endrbyte_reg;
	reg	clr_read_reg;
	reg	clr_read_reg2;
	reg	clr_rstat_reg;
	reg	clr_rstat_reg2;
	reg	clr_secprot_reg;
	reg	clr_secprot_reg2;
	reg	clr_sid_reg;
	reg	clr_sid_reg2;
	reg	clr_write_reg;
	reg	clr_write_reg2;
	reg	cnt_bfend_reg;
	reg	do_wrmemadd_reg;
	reg	dvalid_reg;
	wire	wire_dvalid_reg_ena;
	reg	dvalid_reg2;
	reg	end1_cyc_reg;
	reg	end1_cyc_reg2;
	reg	end_op_hdlyreg;
	reg	end_op_reg;
	reg	end_opfdly_reg;
	reg	end_pgwrop_reg;
	wire	wire_end_pgwrop_reg_ena;
	reg	end_rbyte_reg;
	wire	wire_end_rbyte_reg_ena;
	reg	end_read_reg;
	reg	[7:0]	epcs_id_reg2;
	reg	ill_erase_reg;
	reg	ill_write_reg;
	reg	max_cnt_reg;
	reg	maxcnt_shift_reg;
	reg	maxcnt_shift_reg2;
	reg	ncs_reg;
	wire	wire_ncs_reg_ena;
	wire	[7:0]	wire_pgwrbuf_dataout_d;
	reg	[7:0]	pgwrbuf_dataout;
	wire	[7:0]	wire_pgwrbuf_dataout_ena;
	reg	read_bufdly_reg;
	wire	[7:0]	wire_read_data_reg_d;
	reg	[7:0]	read_data_reg;
	wire	[7:0]	wire_read_data_reg_ena;
	wire	[7:0]	wire_read_dout_reg_d;
	reg	[7:0]	read_dout_reg;
	wire	[7:0]	wire_read_dout_reg_ena;
	reg	read_reg;
	wire	wire_read_reg_ena;
	reg	read_sid_reg;
	reg	sec_erase_reg;
	wire	wire_sec_erase_reg_ena;
	reg	sec_prot_reg;
	wire	wire_sec_prot_reg_ena;
	reg	shftpgwr_data_reg;
	reg	shift_op_reg;
	reg	sprot_rstat_reg;
	reg	stage2_reg;
	reg	stage3_dly_reg;
	reg	stage3_reg;
	reg	stage4_reg;
	reg	start_sppoll_reg;
	wire	wire_start_sppoll_reg_ena;
	reg	start_sppoll_reg2;
	reg	start_wrpoll_reg;
	wire	wire_start_wrpoll_reg_ena;
	reg	start_wrpoll_reg2;
	wire	[7:0]	wire_statreg_int_d;
	reg	[7:0]	statreg_int;
	wire	[7:0]	wire_statreg_int_ena;
	reg	streg_datain_reg;
	wire	wire_streg_datain_reg_ena;
	reg	write_prot_reg;
	wire	wire_write_prot_reg_ena;
	reg	write_reg;
	wire	wire_write_reg_ena;
	reg	write_rstat_reg;
	wire	[7:0]	wire_wrstat_dreg_d;
	reg	[7:0]	wrstat_dreg;
	wire	[7:0]	wire_wrstat_dreg_ena;
	wire  wire_cmpr4_aeb;
	wire  wire_cmpr5_aeb;
	wire  [8:0]   wire_pgwr_data_cntr_q;
	wire  [8:0]   wire_pgwr_read_cntr_q;
	wire	wire_mux211_dataout;
	wire  [7:0]   wire_scfifo3_q;
	wire  be_write_prot;
	wire  [7:0]  berase_opcode;
	wire  bp0_wire;
	wire  bp1_wire;
	wire  bp2_wire;
	wire  buf_empty;
	wire  bulk_erase_wire;
	wire  busy_wire;
	wire  clkin_wire;
	wire  clr_read_wire;
	wire  clr_rstat_wire;
	wire  clr_secprot_wire;
	wire  clr_sid_wire;
	wire  clr_write_wire;
	wire  data0out_wire;
	wire  data_valid_wire;
	wire  do_bulk_erase;
	wire  do_fast_read;
	wire  do_memadd;
	wire  do_polling;
	wire  do_read;
	wire  do_read_rdid;
	wire  do_read_sid;
	wire  do_read_stat;
	wire  do_sec_erase;
	wire  do_sec_prot;
	wire  do_secprot_wren;
	wire  do_sprot_polling;
	wire  do_sprot_rstat;
	wire  do_wren;
	wire  do_write;
	wire  do_write_polling;
	wire  do_write_rstat;
	wire  do_write_wren;
	wire  dummy_read_buf;
	wire  end1_cyc_normal_in_wire;
	wire  end1_cyc_reg_in_wire;
	wire  end_add_cycle;
	wire  end_fast_read;
	wire  end_one_cyc_pos;
	wire  end_one_cycle;
	wire  end_operation;
	wire  end_opfdly;
	wire  end_ophdly;
	wire  end_pgwr_data;
	wire  end_read;
	wire  end_read_byte;
	wire  end_wrstage;
	wire  [7:0]  fast_read_opcode;
	wire  fast_read_wire;
	wire  ill_erase_wire;
	wire  ill_write_wire;
	wire  illegal_erase_b4out_wire;
	wire  illegal_write_b4out_wire;
	wire  in_operation;
	wire  load_opcode;
	wire  memadd_sdoin;
	wire  not_busy;
	wire  oe_wire;
	wire  [8:0]  page_size_wire;
	wire  [8:0]  pagewr_buf_not_empty;
	wire  rden_wire;
	wire  [7:0]  rdid_opcode;
	wire  reach_max_cnt;
	wire  read_buf;
	wire  read_bufdly;
	wire  [7:0]  read_opcode;
	wire  read_rdid_wire;
	wire  read_sid_wire;
	wire  read_status_wire;
	wire  read_wire;
	wire  [7:0]  rsid_opcode;
	wire  rsid_sdoin;
	wire  [7:0]  rstat_opcode;
	wire  scein_wire;
	wire  sdoin_wire;
	wire  sec_erase_wire;
	wire  sec_protect_wire;
	wire  [7:0]  secprot_opcode;
	wire  secprot_sdoin;
	wire  [7:0]  serase_opcode;
	wire  shift_bytes_wire;
	wire  shift_opcode;
	wire  shift_opdata;
	wire  shift_pgwr_data;
	wire  sid_load;
	wire  st_busy_wire;
	wire  stage2_wire;
	wire  stage3_wire;
	wire  stage4_wire;
	wire  start_poll;
	wire  start_sppoll;
	wire  start_wrpoll;
	wire  to_sdoin_wire;
	wire  [7:0]  wren_opcode;
	wire  wren_wire;
	wire  [7:0]  write_opcode;
	wire  write_prot_true;
	wire  write_sdoin;
	wire  write_wire;

	a_graycounter   addbyte_cntr
	( 
	.aclr(end_operation),
	.clk_en((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cyc_pos) & (((((do_read_sid | do_read) | do_fast_read) | do_write) | do_sec_erase) | do_read_rdid))),
	.clock((~ clkin_wire)),
	.q(wire_addbyte_cntr_q),
	.qbin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cnt_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		addbyte_cntr.width = 3,
		addbyte_cntr.lpm_type = "a_graycounter";
	a_graycounter   gen_cntr
	( 
	.aclr(end_one_cycle),
	.clk_en((in_operation & (~ end_ophdly))),
	.clock(clkin_wire),
	.q(wire_gen_cntr_q),
	.qbin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cnt_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		gen_cntr.width = 3,
		gen_cntr.lpm_type = "a_graycounter";
	a_graycounter   spstage_cntr
	( 
	.aclr(clr_secprot_wire),
	.clk_en((do_sec_prot & end_operation)),
	.clock((~ clkin_wire)),
	.q(wire_spstage_cntr_q),
	.qbin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cnt_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		spstage_cntr.width = 2,
		spstage_cntr.lpm_type = "a_graycounter";
	a_graycounter   stage_cntr
	( 
	.aclr(end_ophdly),
	.clk_en(((((((((((in_operation & end_one_cycle) & (~ (stage3_wire & (~ end_add_cycle)))) & (~ (stage4_wire & (~ end_read)))) & (~ (stage4_wire & (~ end_fast_read)))) & (~ (((do_write | do_sec_erase) | do_bulk_erase) & write_prot_true))) & (~ (do_write & (~ pagewr_buf_not_empty[8])))) & (~ (stage3_wire & st_busy_wire))) & (~ ((do_write & shift_pgwr_data) & (~ end_pgwr_data)))) & (~ (stage2_wire & do_wren))) & (~ ((((stage3_wire & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & (~ do_read_rdid))))),
	.clock(clkin_wire),
	.q(wire_stage_cntr_q),
	.qbin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cnt_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		stage_cntr.width = 2,
		stage_cntr.lpm_type = "a_graycounter";
	a_graycounter   wrstage_cntr
	( 
	.aclr(clr_write_wire),
	.clk_en((((((do_write | do_sec_erase) | do_bulk_erase) & end_wrstage) & (~ write_prot_true)) & (~ st_busy_wire))),
	.clock((~ clkin_wire)),
	.q(wire_wrstage_cntr_q),
	.qbin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.cnt_en(1'b1),
	.sclr(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		wrstage_cntr.width = 2,
		wrstage_cntr.lpm_type = "a_graycounter";
	cycloneii_asmiblock   cycloneii_asmiblock2
	( 
	.data0out(wire_cycloneii_asmiblock2_data0out),
	.dclkin(clkin_wire),
	.oe(oe_wire),
	.scein(scein_wire),
	.sdoin(sdoin_wire));
	// synopsys translate_off
	initial
		add_msb_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_addmsb_reg)
		if (clr_addmsb_reg == 1'b1) add_msb_reg <= 1'b0;
		else if  (wire_add_msb_reg_ena == 1'b1)   add_msb_reg <= addr_reg[23];
	assign
		wire_add_msb_reg_ena = ((((((do_read | do_fast_read) | do_write) | do_sec_erase) & (~ ((do_write | do_sec_erase) & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
	// synopsys translate_off
	initial
		addr_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[0:0] == 1'b1)   addr_reg[0:0] <= wire_addr_reg_d[0:0];
	// synopsys translate_off
	initial
		addr_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[1:1] == 1'b1)   addr_reg[1:1] <= wire_addr_reg_d[1:1];
	// synopsys translate_off
	initial
		addr_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[2:2] == 1'b1)   addr_reg[2:2] <= wire_addr_reg_d[2:2];
	// synopsys translate_off
	initial
		addr_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[3:3] == 1'b1)   addr_reg[3:3] <= wire_addr_reg_d[3:3];
	// synopsys translate_off
	initial
		addr_reg[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[4:4] == 1'b1)   addr_reg[4:4] <= wire_addr_reg_d[4:4];
	// synopsys translate_off
	initial
		addr_reg[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[5:5] == 1'b1)   addr_reg[5:5] <= wire_addr_reg_d[5:5];
	// synopsys translate_off
	initial
		addr_reg[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[6:6] == 1'b1)   addr_reg[6:6] <= wire_addr_reg_d[6:6];
	// synopsys translate_off
	initial
		addr_reg[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[7:7] == 1'b1)   addr_reg[7:7] <= wire_addr_reg_d[7:7];
	// synopsys translate_off
	initial
		addr_reg[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[8:8] == 1'b1)   addr_reg[8:8] <= wire_addr_reg_d[8:8];
	// synopsys translate_off
	initial
		addr_reg[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[9:9] == 1'b1)   addr_reg[9:9] <= wire_addr_reg_d[9:9];
	// synopsys translate_off
	initial
		addr_reg[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[10:10] == 1'b1)   addr_reg[10:10] <= wire_addr_reg_d[10:10];
	// synopsys translate_off
	initial
		addr_reg[11:11] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[11:11] == 1'b1)   addr_reg[11:11] <= wire_addr_reg_d[11:11];
	// synopsys translate_off
	initial
		addr_reg[12:12] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[12:12] == 1'b1)   addr_reg[12:12] <= wire_addr_reg_d[12:12];
	// synopsys translate_off
	initial
		addr_reg[13:13] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[13:13] == 1'b1)   addr_reg[13:13] <= wire_addr_reg_d[13:13];
	// synopsys translate_off
	initial
		addr_reg[14:14] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[14:14] == 1'b1)   addr_reg[14:14] <= wire_addr_reg_d[14:14];
	// synopsys translate_off
	initial
		addr_reg[15:15] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[15:15] == 1'b1)   addr_reg[15:15] <= wire_addr_reg_d[15:15];
	// synopsys translate_off
	initial
		addr_reg[16:16] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[16:16] == 1'b1)   addr_reg[16:16] <= wire_addr_reg_d[16:16];
	// synopsys translate_off
	initial
		addr_reg[17:17] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[17:17] == 1'b1)   addr_reg[17:17] <= wire_addr_reg_d[17:17];
	// synopsys translate_off
	initial
		addr_reg[18:18] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[18:18] == 1'b1)   addr_reg[18:18] <= wire_addr_reg_d[18:18];
	// synopsys translate_off
	initial
		addr_reg[19:19] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[19:19] == 1'b1)   addr_reg[19:19] <= wire_addr_reg_d[19:19];
	// synopsys translate_off
	initial
		addr_reg[20:20] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[20:20] == 1'b1)   addr_reg[20:20] <= wire_addr_reg_d[20:20];
	// synopsys translate_off
	initial
		addr_reg[21:21] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[21:21] == 1'b1)   addr_reg[21:21] <= wire_addr_reg_d[21:21];
	// synopsys translate_off
	initial
		addr_reg[22:22] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[22:22] == 1'b1)   addr_reg[22:22] <= wire_addr_reg_d[22:22];
	// synopsys translate_off
	initial
		addr_reg[23:23] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_addr_reg_ena[23:23] == 1'b1)   addr_reg[23:23] <= wire_addr_reg_d[23:23];
	assign
		wire_addr_reg_d = {(({23{not_busy}} & addr[23:1]) | ({23{stage3_wire}} & addr_reg[22:0])), (not_busy & addr[0])};
	assign
		wire_addr_reg_ena = {24{(((rden_wire | wren_wire) & not_busy) | (stage3_wire & ((((do_write | do_sec_erase) & do_memadd) | do_read) | do_fast_read)))}};
	// synopsys translate_off
	initial
		asmi_opcode_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[0:0] == 1'b1)   asmi_opcode_reg[0:0] <= wire_asmi_opcode_reg_d[0:0];
	// synopsys translate_off
	initial
		asmi_opcode_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[1:1] == 1'b1)   asmi_opcode_reg[1:1] <= wire_asmi_opcode_reg_d[1:1];
	// synopsys translate_off
	initial
		asmi_opcode_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[2:2] == 1'b1)   asmi_opcode_reg[2:2] <= wire_asmi_opcode_reg_d[2:2];
	// synopsys translate_off
	initial
		asmi_opcode_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[3:3] == 1'b1)   asmi_opcode_reg[3:3] <= wire_asmi_opcode_reg_d[3:3];
	// synopsys translate_off
	initial
		asmi_opcode_reg[4:4] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[4:4] == 1'b1)   asmi_opcode_reg[4:4] <= wire_asmi_opcode_reg_d[4:4];
	// synopsys translate_off
	initial
		asmi_opcode_reg[5:5] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[5:5] == 1'b1)   asmi_opcode_reg[5:5] <= wire_asmi_opcode_reg_d[5:5];
	// synopsys translate_off
	initial
		asmi_opcode_reg[6:6] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[6:6] == 1'b1)   asmi_opcode_reg[6:6] <= wire_asmi_opcode_reg_d[6:6];
	// synopsys translate_off
	initial
		asmi_opcode_reg[7:7] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_asmi_opcode_reg_ena[7:7] == 1'b1)   asmi_opcode_reg[7:7] <= wire_asmi_opcode_reg_d[7:7];
	assign
		wire_asmi_opcode_reg_d = {((((((((((({7{(load_opcode & do_read_sid)}} & rsid_opcode[7:1]) | ({7{(load_opcode & do_read_rdid)}} & rdid_opcode[7:1])) | ({7{(((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat))}} & secprot_opcode[7:1])) | ({7{(load_opcode & do_read)}} & read_opcode[7:1])) | ({7{(load_opcode & do_fast_read)}} & fast_read_opcode[7:1])) | ({7{(load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren)))}} & write_opcode[7:1])) | ({7{(load_opcode & do_read_stat)}} & rstat_opcode[7:1])) | ({7{(((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat))}} & serase_opcode[7:1])) | ({7{(((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat))}} & berase_opcode[7:1])) | ({7{(load_opcode & do_wren)}} & wren_opcode[7:1])) | ({7{shift_opcode}} & asmi_opcode_reg[6:0])), (((((((((((load_opcode & do_read_sid) & rsid_opcode[0]) | ((load_opcode & do_read_rdid) & rdid_opcode[0])) | ((((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & secprot_opcode[0])) | ((load_opcode & do_read) & read_opcode[0])) | ((load_opcode & do_fast_read) & fast_read_opcode[0])) | ((load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren))) & write_opcode[0])) | ((load_opcode & do_read_stat) & rstat_opcode[0])) | ((((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & serase_opcode[0])) | ((((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat)) & berase_opcode[0])) | ((load_opcode & do_wren) & wren_opcode[0]))};
	assign
		wire_asmi_opcode_reg_ena = {8{(load_opcode | shift_opcode)}};
	// synopsys translate_off
	initial
		buf_empty_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  buf_empty_reg <= wire_cmpr5_aeb;
	// synopsys translate_off
	initial
		bulk_erase_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) bulk_erase_reg <= 1'b0;
		else if  (wire_bulk_erase_reg_ena == 1'b1)   bulk_erase_reg <= bulk_erase;
	assign
		wire_bulk_erase_reg_ena = ((~ busy_wire) & wren_wire);
	// synopsys translate_off
	initial
		busy_det_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  busy_det_reg <= (~ busy_wire);
	// synopsys translate_off
	initial
		clr_addmsb_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_addmsb_reg <= (((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & end_add_cycle) & end_one_cyc_pos) | (((~ do_read) & (~ do_fast_read)) & clr_write_wire)) | (((do_sec_erase & (~ do_wren)) & (~ do_read_stat)) & end_operation));
	// synopsys translate_off
	initial
		clr_endrbyte_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  clr_endrbyte_reg <= (((((do_read | do_fast_read) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | clr_read_wire);
	// synopsys translate_off
	initial
		clr_read_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_read_reg <= ((end_operation | do_read_sid) | do_sec_prot);
	// synopsys translate_off
	initial
		clr_read_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_read_reg2 <= clr_read_reg;
	// synopsys translate_off
	initial
		clr_rstat_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_rstat_reg <= ((end_operation | do_read_sid) | do_read);
	// synopsys translate_off
	initial
		clr_rstat_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_rstat_reg2 <= clr_rstat_reg;
	// synopsys translate_off
	initial
		clr_secprot_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_secprot_reg <= (((wire_spstage_cntr_q[1] & wire_spstage_cntr_q[0]) & end_operation) | do_read_sid);
	// synopsys translate_off
	initial
		clr_secprot_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_secprot_reg2 <= clr_secprot_reg;
	// synopsys translate_off
	initial
		clr_sid_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_sid_reg <= end_operation;
	// synopsys translate_off
	initial
		clr_sid_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_sid_reg2 <= clr_sid_reg;
	// synopsys translate_off
	initial
		clr_write_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_write_reg <= ((((((((((((do_write | do_sec_erase) | do_bulk_erase) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) & end_operation) | write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((((~ do_write) & (~ do_sec_erase)) & (~ do_bulk_erase)) & end_operation)) | do_read_sid) | do_sec_prot) | do_read) | do_fast_read);
	// synopsys translate_off
	initial
		clr_write_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  clr_write_reg2 <= clr_write_reg;
	// synopsys translate_off
	initial
		cnt_bfend_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  cnt_bfend_reg <= ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]);
	// synopsys translate_off
	initial
		do_wrmemadd_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  do_wrmemadd_reg <= (wire_wrstage_cntr_q[1] & wire_wrstage_cntr_q[0]);
	// synopsys translate_off
	initial
		dvalid_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge end_operation)
		if (end_operation == 1'b1) dvalid_reg <= 1'b0;
		else if  (wire_dvalid_reg_ena == 1'b1)   dvalid_reg <= (end_read_byte & end_one_cyc_pos);
	assign
		wire_dvalid_reg_ena = (do_read | do_fast_read);
	// synopsys translate_off
	initial
		dvalid_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  dvalid_reg2 <= dvalid_reg;
	// synopsys translate_off
	initial
		end1_cyc_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  end1_cyc_reg <= end1_cyc_reg_in_wire;
	// synopsys translate_off
	initial
		end1_cyc_reg2 = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  end1_cyc_reg2 <= end_one_cycle;
	// synopsys translate_off
	initial
		end_op_hdlyreg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  end_op_hdlyreg <= end_operation;
	// synopsys translate_off
	initial
		end_op_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  end_op_reg <= (((((((((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & ((((((~ do_read) & (~ do_fast_read)) & (~ (do_write & shift_pgwr_data))) & end_one_cycle) | (do_read & end_read)) | (do_fast_read & end_fast_read))) | ((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_stat) & end_one_cycle) & (~ do_polling))) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_rdid) & end_one_cycle) & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & wire_addbyte_cntr_q[0])) | (((start_poll & do_read_stat) & do_polling) & (~ st_busy_wire))) | ((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & (do_wren | (do_bulk_erase & (~ do_read_stat)))) & end_one_cycle)) | (((do_write | do_sec_erase) | do_bulk_erase) & write_prot_true)) | ((do_write & shift_pgwr_data) & end_pgwr_data)) | (do_write & (~ pagewr_buf_not_empty[8]))) | (((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & end_one_cycle)) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & end_add_cycle) & end_one_cycle));
	// synopsys translate_off
	initial
		end_opfdly_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  end_opfdly_reg <= end_operation;
	// synopsys translate_off
	initial
		end_pgwrop_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) end_pgwrop_reg <= 1'b0;
		else if  (wire_end_pgwrop_reg_ena == 1'b1)   end_pgwrop_reg <= buf_empty;
	assign
		wire_end_pgwrop_reg_ena = ((cnt_bfend_reg & do_write) & shift_pgwr_data);
	// synopsys translate_off
	initial
		end_rbyte_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_endrbyte_reg)
		if (clr_endrbyte_reg == 1'b1) end_rbyte_reg <= 1'b0;
		else if  (wire_end_rbyte_reg_ena == 1'b1)   end_rbyte_reg <= (((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0]));
	assign
		wire_end_rbyte_reg_ena = ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]);
	// synopsys translate_off
	initial
		end_read_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  end_read_reg <= ((((~ rden_wire) & (do_read | do_fast_read)) & data_valid_wire) & end_read_byte);
	// synopsys translate_off
	initial
		epcs_id_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (sid_load == 1'b1)   epcs_id_reg2 <= {read_dout_reg[7:0]};
	// synopsys translate_off
	initial
		ill_erase_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  ill_erase_reg <= illegal_erase_b4out_wire;
	// synopsys translate_off
	initial
		ill_write_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  ill_write_reg <= illegal_write_b4out_wire;
	// synopsys translate_off
	initial
		max_cnt_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  max_cnt_reg <= wire_cmpr4_aeb;
	// synopsys translate_off
	initial
		maxcnt_shift_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  maxcnt_shift_reg <= (((reach_max_cnt & shift_bytes_wire) & wren_wire) & (~ do_write));
	// synopsys translate_off
	initial
		maxcnt_shift_reg2 = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  maxcnt_shift_reg2 <= maxcnt_shift_reg;
	// synopsys translate_off
	initial
		ncs_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge end_ophdly)
		if (end_ophdly == 1'b1) ncs_reg <= 1'b0;
		else if  (wire_ncs_reg_ena == 1'b1)   ncs_reg <= 1'b1;
	assign
		wire_ncs_reg_ena = (((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & end_one_cyc_pos);
	// synopsys translate_off
	initial
		pgwrbuf_dataout[0:0] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[0:0] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[0:0] == 1'b1)   pgwrbuf_dataout[0:0] <= wire_pgwrbuf_dataout_d[0:0];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[1:1] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[1:1] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[1:1] == 1'b1)   pgwrbuf_dataout[1:1] <= wire_pgwrbuf_dataout_d[1:1];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[2:2] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[2:2] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[2:2] == 1'b1)   pgwrbuf_dataout[2:2] <= wire_pgwrbuf_dataout_d[2:2];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[3:3] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[3:3] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[3:3] == 1'b1)   pgwrbuf_dataout[3:3] <= wire_pgwrbuf_dataout_d[3:3];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[4:4] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[4:4] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[4:4] == 1'b1)   pgwrbuf_dataout[4:4] <= wire_pgwrbuf_dataout_d[4:4];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[5:5] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[5:5] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[5:5] == 1'b1)   pgwrbuf_dataout[5:5] <= wire_pgwrbuf_dataout_d[5:5];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[6:6] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[6:6] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[6:6] == 1'b1)   pgwrbuf_dataout[6:6] <= wire_pgwrbuf_dataout_d[6:6];
	// synopsys translate_off
	initial
		pgwrbuf_dataout[7:7] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) pgwrbuf_dataout[7:7] <= 1'b0;
		else if  (wire_pgwrbuf_dataout_ena[7:7] == 1'b1)   pgwrbuf_dataout[7:7] <= wire_pgwrbuf_dataout_d[7:7];
	assign
		wire_pgwrbuf_dataout_d = {(({7{read_bufdly}} & wire_scfifo3_q[7:1]) | ({7{(~ read_bufdly)}} & pgwrbuf_dataout[6:0])), (read_bufdly & wire_scfifo3_q[0])};
	assign
		wire_pgwrbuf_dataout_ena = {8{(read_bufdly | shift_pgwr_data)}};
	// synopsys translate_off
	initial
		read_bufdly_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  read_bufdly_reg <= read_buf;
	// synopsys translate_off
	initial
		read_data_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[0:0] == 1'b1)   read_data_reg[0:0] <= wire_read_data_reg_d[0:0];
	// synopsys translate_off
	initial
		read_data_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[1:1] == 1'b1)   read_data_reg[1:1] <= wire_read_data_reg_d[1:1];
	// synopsys translate_off
	initial
		read_data_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[2:2] == 1'b1)   read_data_reg[2:2] <= wire_read_data_reg_d[2:2];
	// synopsys translate_off
	initial
		read_data_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[3:3] == 1'b1)   read_data_reg[3:3] <= wire_read_data_reg_d[3:3];
	// synopsys translate_off
	initial
		read_data_reg[4:4] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[4:4] == 1'b1)   read_data_reg[4:4] <= wire_read_data_reg_d[4:4];
	// synopsys translate_off
	initial
		read_data_reg[5:5] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[5:5] == 1'b1)   read_data_reg[5:5] <= wire_read_data_reg_d[5:5];
	// synopsys translate_off
	initial
		read_data_reg[6:6] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[6:6] == 1'b1)   read_data_reg[6:6] <= wire_read_data_reg_d[6:6];
	// synopsys translate_off
	initial
		read_data_reg[7:7] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		if (wire_read_data_reg_ena[7:7] == 1'b1)   read_data_reg[7:7] <= wire_read_data_reg_d[7:7];
	assign
		wire_read_data_reg_d = {read_dout_reg[7:0]};
	assign
		wire_read_data_reg_ena = {8{(((((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & end_one_cyc_pos) & end_read_byte)}};
	// synopsys translate_off
	initial
		read_dout_reg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[0:0] == 1'b1)   read_dout_reg[0:0] <= wire_read_dout_reg_d[0:0];
	// synopsys translate_off
	initial
		read_dout_reg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[1:1] == 1'b1)   read_dout_reg[1:1] <= wire_read_dout_reg_d[1:1];
	// synopsys translate_off
	initial
		read_dout_reg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[2:2] == 1'b1)   read_dout_reg[2:2] <= wire_read_dout_reg_d[2:2];
	// synopsys translate_off
	initial
		read_dout_reg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[3:3] == 1'b1)   read_dout_reg[3:3] <= wire_read_dout_reg_d[3:3];
	// synopsys translate_off
	initial
		read_dout_reg[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[4:4] == 1'b1)   read_dout_reg[4:4] <= wire_read_dout_reg_d[4:4];
	// synopsys translate_off
	initial
		read_dout_reg[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[5:5] == 1'b1)   read_dout_reg[5:5] <= wire_read_dout_reg_d[5:5];
	// synopsys translate_off
	initial
		read_dout_reg[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[6:6] == 1'b1)   read_dout_reg[6:6] <= wire_read_dout_reg_d[6:6];
	// synopsys translate_off
	initial
		read_dout_reg[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		if (wire_read_dout_reg_ena[7:7] == 1'b1)   read_dout_reg[7:7] <= wire_read_dout_reg_d[7:7];
	assign
		wire_read_dout_reg_d = {read_dout_reg[6:0], data0out_wire};
	assign
		wire_read_dout_reg_ena = {8{((stage4_wire & ((do_read | do_fast_read) | do_read_sid)) | (stage3_wire & (do_read_stat | do_read_rdid)))}};
	// synopsys translate_off
	initial
		read_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_read_wire)
		if (clr_read_wire == 1'b1) read_reg <= 1'b0;
		else if  (wire_read_reg_ena == 1'b1)   read_reg <= read;
	assign
		wire_read_reg_ena = ((~ busy_wire) & rden_wire);
	// synopsys translate_off
	initial
		read_sid_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_sid_wire)
		if (clr_sid_wire == 1'b1) read_sid_reg <= 1'b0;
		else if  (busy_wire == 1'b0)   read_sid_reg <= read_sid;
	// synopsys translate_off
	initial
		sec_erase_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) sec_erase_reg <= 1'b0;
		else if  (wire_sec_erase_reg_ena == 1'b1)   sec_erase_reg <= sector_erase;
	assign
		wire_sec_erase_reg_ena = ((~ busy_wire) & wren_wire);
	// synopsys translate_off
	initial
		sec_prot_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) sec_prot_reg <= 1'b0;
		else if  (wire_sec_prot_reg_ena == 1'b1)   sec_prot_reg <= sector_protect;
	assign
		wire_sec_prot_reg_ena = ((~ busy_wire) & wren_wire);
	// synopsys translate_off
	initial
		shftpgwr_data_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge end_ophdly)
		if (end_ophdly == 1'b1) shftpgwr_data_reg <= 1'b0;
		else  shftpgwr_data_reg <= (((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]);
	// synopsys translate_off
	initial
		shift_op_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  shift_op_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
	// synopsys translate_off
	initial
		sprot_rstat_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) sprot_rstat_reg <= 1'b0;
		else  sprot_rstat_reg <= ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]);
	// synopsys translate_off
	initial
		stage2_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  stage2_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
	// synopsys translate_off
	initial
		stage3_dly_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire)
		  stage3_dly_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
	// synopsys translate_off
	initial
		stage3_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  stage3_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
	// synopsys translate_off
	initial
		stage4_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire)
		  stage4_reg <= (wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0]));
	// synopsys translate_off
	initial
		start_sppoll_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) start_sppoll_reg <= 1'b0;
		else if  (wire_start_sppoll_reg_ena == 1'b1)   start_sppoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
	assign
		wire_start_sppoll_reg_ena = ((do_sprot_rstat & do_polling) & end_one_cycle);
	// synopsys translate_off
	initial
		start_sppoll_reg2 = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) start_sppoll_reg2 <= 1'b0;
		else  start_sppoll_reg2 <= start_sppoll_reg;
	// synopsys translate_off
	initial
		start_wrpoll_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) start_wrpoll_reg <= 1'b0;
		else if  (wire_start_wrpoll_reg_ena == 1'b1)   start_wrpoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
	assign
		wire_start_wrpoll_reg_ena = ((do_write_rstat & do_polling) & end_one_cycle);
	// synopsys translate_off
	initial
		start_wrpoll_reg2 = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) start_wrpoll_reg2 <= 1'b0;
		else  start_wrpoll_reg2 <= start_wrpoll_reg;
	// synopsys translate_off
	initial
		statreg_int[0:0] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[0:0] <= 1'b0;
		else if  (wire_statreg_int_ena[0:0] == 1'b1)   statreg_int[0:0] <= wire_statreg_int_d[0:0];
	// synopsys translate_off
	initial
		statreg_int[1:1] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[1:1] <= 1'b0;
		else if  (wire_statreg_int_ena[1:1] == 1'b1)   statreg_int[1:1] <= wire_statreg_int_d[1:1];
	// synopsys translate_off
	initial
		statreg_int[2:2] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[2:2] <= 1'b0;
		else if  (wire_statreg_int_ena[2:2] == 1'b1)   statreg_int[2:2] <= wire_statreg_int_d[2:2];
	// synopsys translate_off
	initial
		statreg_int[3:3] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[3:3] <= 1'b0;
		else if  (wire_statreg_int_ena[3:3] == 1'b1)   statreg_int[3:3] <= wire_statreg_int_d[3:3];
	// synopsys translate_off
	initial
		statreg_int[4:4] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[4:4] <= 1'b0;
		else if  (wire_statreg_int_ena[4:4] == 1'b1)   statreg_int[4:4] <= wire_statreg_int_d[4:4];
	// synopsys translate_off
	initial
		statreg_int[5:5] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[5:5] <= 1'b0;
		else if  (wire_statreg_int_ena[5:5] == 1'b1)   statreg_int[5:5] <= wire_statreg_int_d[5:5];
	// synopsys translate_off
	initial
		statreg_int[6:6] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[6:6] <= 1'b0;
		else if  (wire_statreg_int_ena[6:6] == 1'b1)   statreg_int[6:6] <= wire_statreg_int_d[6:6];
	// synopsys translate_off
	initial
		statreg_int[7:7] = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge clr_rstat_wire)
		if (clr_rstat_wire == 1'b1) statreg_int[7:7] <= 1'b0;
		else if  (wire_statreg_int_ena[7:7] == 1'b1)   statreg_int[7:7] <= wire_statreg_int_d[7:7];
	assign
		wire_statreg_int_d = {read_dout_reg[7:0]};
	assign
		wire_statreg_int_ena = {8{((end_operation | ((do_polling & end_one_cyc_pos) & stage3_dly_reg)) & do_read_stat)}};
	// synopsys translate_off
	initial
		streg_datain_reg = 0;
	// synopsys translate_on
	always @ ( negedge clkin_wire or  posedge end_opfdly)
		if (end_opfdly == 1'b1) streg_datain_reg <= 1'b0;
		else if  (wire_streg_datain_reg_ena == 1'b1)   streg_datain_reg <= wrstat_dreg[7];
	assign
		wire_streg_datain_reg_ena = ((do_sec_prot & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0]);
	// synopsys translate_off
	initial
		write_prot_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) write_prot_reg <= 1'b0;
		else if  (wire_write_prot_reg_ena == 1'b1)   write_prot_reg <= (((do_write | do_sec_erase) & ((((((((((((addr_reg[20] & addr_reg[19]) & addr_reg[18]) & addr_reg[17]) & addr_reg[16]) & (~ bp2_wire)) & (~ bp1_wire)) & bp0_wire) | ((((((addr_reg[20] & addr_reg[19]) & addr_reg[18]) & addr_reg[17]) & (~ bp2_wire)) & bp1_wire) & (~ bp0_wire))) | (((((addr_reg[20] & addr_reg[19]) & addr_reg[18]) & (~ bp2_wire)) & bp1_wire) & bp0_wire)) | ((((addr_reg[20] & addr_reg[19]) & bp2_wire) & (~ bp1_wire)) & (~ bp0_wire))) | (((addr_reg[20] & bp2_wire) & (~ bp1_wire)) & bp0_wire)) | (bp2_wire & bp1_wire))) | be_write_prot);
	assign
		wire_write_prot_reg_ena = (((((do_sec_erase | do_write) | do_bulk_erase) & (~ wire_wrstage_cntr_q[1])) & wire_wrstage_cntr_q[0]) & end_ophdly);
	// synopsys translate_off
	initial
		write_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) write_reg <= 1'b0;
		else if  (wire_write_reg_ena == 1'b1)   write_reg <= write;
	assign
		wire_write_reg_ena = ((~ busy_wire) & wren_wire);
	// synopsys translate_off
	initial
		write_rstat_reg = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_write_wire)
		if (clr_write_wire == 1'b1) write_rstat_reg <= 1'b0;
		else  write_rstat_reg <= (((do_write | do_sec_erase) | do_bulk_erase) & (((~ wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) | (wire_wrstage_cntr_q[1] & (~ wire_wrstage_cntr_q[0]))));
	// synopsys translate_off
	initial
		wrstat_dreg[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[0:0] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[0:0] == 1'b1)   wrstat_dreg[0:0] <= wire_wrstat_dreg_d[0:0];
	// synopsys translate_off
	initial
		wrstat_dreg[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[1:1] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[1:1] == 1'b1)   wrstat_dreg[1:1] <= wire_wrstat_dreg_d[1:1];
	// synopsys translate_off
	initial
		wrstat_dreg[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[2:2] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[2:2] == 1'b1)   wrstat_dreg[2:2] <= wire_wrstat_dreg_d[2:2];
	// synopsys translate_off
	initial
		wrstat_dreg[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[3:3] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[3:3] == 1'b1)   wrstat_dreg[3:3] <= wire_wrstat_dreg_d[3:3];
	// synopsys translate_off
	initial
		wrstat_dreg[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[4:4] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[4:4] == 1'b1)   wrstat_dreg[4:4] <= wire_wrstat_dreg_d[4:4];
	// synopsys translate_off
	initial
		wrstat_dreg[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[5:5] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[5:5] == 1'b1)   wrstat_dreg[5:5] <= wire_wrstat_dreg_d[5:5];
	// synopsys translate_off
	initial
		wrstat_dreg[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[6:6] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[6:6] == 1'b1)   wrstat_dreg[6:6] <= wire_wrstat_dreg_d[6:6];
	// synopsys translate_off
	initial
		wrstat_dreg[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clkin_wire or  posedge clr_secprot_wire)
		if (clr_secprot_wire == 1'b1) wrstat_dreg[7:7] <= 1'b0;
		else if  (wire_wrstat_dreg_ena[7:7] == 1'b1)   wrstat_dreg[7:7] <= wire_wrstat_dreg_d[7:7];
	assign
		wire_wrstat_dreg_d = {(({7{not_busy}} & datain[7:1]) | ({7{stage3_wire}} & wrstat_dreg[6:0])), (not_busy & datain[0])};
	assign
		wire_wrstat_dreg_ena = {8{((wren_wire & not_busy) | (((do_sec_prot & stage3_wire) & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0]))}};
	lpm_compare   cmpr4
	( 
	.aeb(wire_cmpr4_aeb),
	.agb(),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa({page_size_wire[8:0]}),
	.datab({wire_pgwr_data_cntr_q[8:0]})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr4.lpm_width = 9,
		cmpr4.lpm_type = "lpm_compare";
	lpm_compare   cmpr5
	( 
	.aeb(wire_cmpr5_aeb),
	.agb(),
	.ageb(),
	.alb(),
	.aleb(),
	.aneb(),
	.dataa({wire_pgwr_data_cntr_q[8:0]}),
	.datab({wire_pgwr_read_cntr_q[8:0]})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cmpr5.lpm_width = 9,
		cmpr5.lpm_type = "lpm_compare";
	lpm_counter   pgwr_data_cntr
	( 
	.aclr(clr_write_wire),
	.clk_en((((shift_bytes_wire & wren_wire) & (~ reach_max_cnt)) & (~ do_write))),
	.clock(clkin_wire),
	.cout(),
	.eq(),
	.q(wire_pgwr_data_cntr_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({9{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		pgwr_data_cntr.lpm_direction = "UP",
		pgwr_data_cntr.lpm_port_updown = "PORT_UNUSED",
		pgwr_data_cntr.lpm_width = 9,
		pgwr_data_cntr.lpm_type = "lpm_counter";
	lpm_counter   pgwr_read_cntr
	( 
	.aclr(clr_write_wire),
	.clk_en(read_buf),
	.clock(clkin_wire),
	.cout(),
	.eq(),
	.q(wire_pgwr_read_cntr_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({9{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		pgwr_read_cntr.lpm_direction = "UP",
		pgwr_read_cntr.lpm_port_updown = "PORT_UNUSED",
		pgwr_read_cntr.lpm_width = 9,
		pgwr_read_cntr.lpm_type = "lpm_counter";
	assign		wire_mux211_dataout = (do_fast_read === 1'b1) ? wire_addbyte_cntr_q[2] : (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0]));
	scfifo   scfifo3
	( 
	.aclr(clr_write_wire),
	.almost_empty(),
	.almost_full(),
	.clock(clkin_wire),
	.data({datain[7:0]}),
	.empty(),
	.full(),
	.q(wire_scfifo3_q),
	.rdreq((read_buf | dummy_read_buf)),
	.usedw(),
	.wrreq(((shift_bytes_wire & wren_wire) & (~ do_write)))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.sclr(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		scfifo3.lpm_numwords = 258,
		scfifo3.lpm_width = 8,
		scfifo3.lpm_widthu = 9,
		scfifo3.use_eab = "ON",
		scfifo3.lpm_type = "scfifo";
	assign
		be_write_prot = (do_bulk_erase & ((bp2_wire | bp1_wire) | bp0_wire)),
		berase_opcode = 8'b11000111,
		bp0_wire = statreg_int[2],
		bp1_wire = statreg_int[3],
		bp2_wire = statreg_int[4],
		buf_empty = buf_empty_reg,
		bulk_erase_wire = bulk_erase_reg,
		busy = busy_wire,
		busy_wire = ((((((((do_read_rdid | do_read_sid) | do_read) | do_fast_read) | do_write) | do_sec_prot) | do_read_stat) | do_sec_erase) | do_bulk_erase),
		clkin_wire = clkin,
		clr_read_wire = clr_read_reg2,
		clr_rstat_wire = clr_rstat_reg2,
		clr_secprot_wire = clr_secprot_reg2,
		clr_sid_wire = clr_sid_reg2,
		clr_write_wire = clr_write_reg2,
		data0out_wire = wire_cycloneii_asmiblock2_data0out,
		data_valid = data_valid_wire,
		data_valid_wire = dvalid_reg2,
		dataout = {read_data_reg[7:0]},
		do_bulk_erase = ((((((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & (~ sec_erase_wire)) & bulk_erase_wire),
		do_fast_read = 1'b0,
		do_memadd = do_wrmemadd_reg,
		do_polling = (do_write_polling | do_sprot_polling),
		do_read = ((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & read_wire),
		do_read_rdid = 1'b0,
		do_read_sid = ((~ read_rdid_wire) & read_sid_wire),
		do_read_stat = ((((((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & read_status_wire) | do_write_rstat) | do_sprot_rstat),
		do_sec_erase = (((((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & sec_erase_wire),
		do_sec_prot = (((~ read_rdid_wire) & (~ read_sid_wire)) & sec_protect_wire),
		do_secprot_wren = ((do_sec_prot & (~ wire_spstage_cntr_q[1])) & (~ wire_spstage_cntr_q[0])),
		do_sprot_polling = ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]),
		do_sprot_rstat = sprot_rstat_reg,
		do_wren = (do_write_wren | do_secprot_wren),
		do_write = (((((~ read_rdid_wire) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & write_wire),
		do_write_polling = ((((do_write | do_sec_erase) | do_bulk_erase) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])),
		do_write_rstat = write_rstat_reg,
		do_write_wren = ((~ wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]),
		dummy_read_buf = maxcnt_shift_reg2,
		end1_cyc_normal_in_wire = (((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | ((((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & wire_gen_cntr_q[2]) & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0]))) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | (((do_write | do_sec_erase) | do_bulk_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))),
		end1_cyc_reg_in_wire = end1_cyc_normal_in_wire,
		end_add_cycle = wire_mux211_dataout,
		end_fast_read = end_read_reg,
		end_one_cyc_pos = end1_cyc_reg2,
		end_one_cycle = end1_cyc_reg,
		end_operation = end_op_reg,
		end_opfdly = end_opfdly_reg,
		end_ophdly = end_op_hdlyreg,
		end_pgwr_data = end_pgwrop_reg,
		end_read = end_read_reg,
		end_read_byte = end_rbyte_reg,
		end_wrstage = end_operation,
		epcs_id = {epcs_id_reg2[7:0]},
		fast_read_opcode = {8{1'b0}},
		fast_read_wire = 1'b0,
		ill_erase_wire = ill_erase_reg,
		ill_write_wire = ill_write_reg,
		illegal_erase = ill_erase_wire,
		illegal_erase_b4out_wire = ((do_sec_erase | do_bulk_erase) & write_prot_true),
		illegal_write = ill_write_wire,
		illegal_write_b4out_wire = ((do_write & write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))),
		in_operation = busy_wire,
		load_opcode = (((((~ wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
		memadd_sdoin = add_msb_reg,
		not_busy = busy_det_reg,
		oe_wire = 1'b0,
		page_size_wire = 9'b100000000,
		pagewr_buf_not_empty = {(pagewr_buf_not_empty[7] | wire_pgwr_data_cntr_q[8]), (pagewr_buf_not_empty[6] | wire_pgwr_data_cntr_q[7]), (pagewr_buf_not_empty[5] | wire_pgwr_data_cntr_q[6]), (pagewr_buf_not_empty[4] | wire_pgwr_data_cntr_q[5]), (pagewr_buf_not_empty[3] | wire_pgwr_data_cntr_q[4]), (pagewr_buf_not_empty[2] | wire_pgwr_data_cntr_q[3]), (pagewr_buf_not_empty[1] | wire_pgwr_data_cntr_q[2]), (pagewr_buf_not_empty[0] | wire_pgwr_data_cntr_q[1]), wire_pgwr_data_cntr_q[0]},
		rden_wire = rden,
		rdid_opcode = {8{1'b0}},
		reach_max_cnt = max_cnt_reg,
		read_buf = (((((end_one_cycle & do_write) & (~ do_read_stat)) & (~ do_wren)) & ((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) | (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0])))) & (~ buf_empty)),
		read_bufdly = read_bufdly_reg,
		read_opcode = 8'b00000011,
		read_rdid_wire = 1'b0,
		read_sid_wire = read_sid_reg,
		read_status_wire = 1'b0,
		read_wire = read_reg,
		rsid_opcode = 8'b10101011,
		rsid_sdoin = (do_read_sid & stage3_wire),
		rstat_opcode = 8'b00000101,
		scein_wire = (~ ncs_reg),
		sdoin_wire = to_sdoin_wire,
		sec_erase_wire = sec_erase_reg,
		sec_protect_wire = sec_prot_reg,
		secprot_opcode = 8'b00000001,
		secprot_sdoin = (stage3_wire & streg_datain_reg),
		serase_opcode = 8'b11011000,
		shift_bytes_wire = shift_bytes,
		shift_opcode = shift_op_reg,
		shift_opdata = stage2_wire,
		shift_pgwr_data = shftpgwr_data_reg,
		sid_load = (end_operation & do_read_sid),
		st_busy_wire = statreg_int[0],
		stage2_wire = stage2_reg,
		stage3_wire = stage3_reg,
		stage4_wire = stage4_reg,
		start_poll = (start_wrpoll | start_sppoll),
		start_sppoll = start_sppoll_reg2,
		start_wrpoll = start_wrpoll_reg2,
		to_sdoin_wire = (((((shift_opdata & asmi_opcode_reg[7]) | rsid_sdoin) | memadd_sdoin) | write_sdoin) | secprot_sdoin),
		wren_opcode = 8'b00000110,
		wren_wire = wren,
		write_opcode = 8'b00000010,
		write_prot_true = write_prot_reg,
		write_sdoin = ((((do_write & stage4_wire) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]) & pgwrbuf_dataout[7]),
		write_wire = write_reg;
endmodule //ASMI_altasmi_parallel_cv82
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ASMI (
	addr,
	bulk_erase,
	clkin,
	datain,
	rden,
	read,
	read_sid,
	sector_erase,
	sector_protect,
	shift_bytes,
	wren,
	write,
	busy,
	data_valid,
	dataout,
	epcs_id,
	illegal_erase,
	illegal_write)/* synthesis synthesis_clearbox = 2 */;

	input	[23:0]  addr;
	input	  bulk_erase;
	input	  clkin;
	input	[7:0]  datain;
	input	  rden;
	input	  read;
	input	  read_sid;
	input	  sector_erase;
	input	  sector_protect;
	input	  shift_bytes;
	input	  wren;
	input	  write;
	output	  busy;
	output	  data_valid;
	output	[7:0]  dataout;
	output	[7:0]  epcs_id;
	output	  illegal_erase;
	output	  illegal_write;

	wire [7:0] sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire  sub_wire3;
	wire [7:0] sub_wire4;
	wire  sub_wire5;
	wire [7:0] dataout = sub_wire0[7:0];
	wire  illegal_write = sub_wire1;
	wire  busy = sub_wire2;
	wire  data_valid = sub_wire3;
	wire [7:0] epcs_id = sub_wire4[7:0];
	wire  illegal_erase = sub_wire5;

	ASMI_altasmi_parallel_cv82	ASMI_altasmi_parallel_cv82_component (
				.datain (datain),
				.addr (addr),
				.sector_erase (sector_erase),
				.clkin (clkin),
				.sector_protect (sector_protect),
				.wren (wren),
				.read (read),
				.bulk_erase (bulk_erase),
				.write (write),
				.shift_bytes (shift_bytes),
				.rden (rden),
				.read_sid (read_sid),
				.dataout (sub_wire0),
				.illegal_write (sub_wire1),
				.busy (sub_wire2),
				.data_valid (sub_wire3),
				.epcs_id (sub_wire4),
				.illegal_erase (sub_wire5))/* synthesis synthesis_clearbox=2
	 clearbox_macroname = altasmi_parallel
	 clearbox_defparam = "epcs_type=EPCS16;intended_device_family=Cyclone III;page_size=256;port_bulk_erase=PORT_USED;port_fast_read=PORT_UNUSED;port_illegal_erase=PORT_USED;port_illegal_write=PORT_USED;port_rdid_out=PORT_UNUSED;port_read_address=PORT_UNUSED;port_read_rdid=PORT_UNUSED;port_read_sid=PORT_USED;port_read_status=PORT_UNUSED;port_sector_erase=PORT_USED;port_sector_protect=PORT_USED;port_shift_bytes=PORT_USED;port_wren=PORT_USED;port_write=PORT_USED;use_eab=ON;" */;

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: EPCS_TYPE STRING "EPCS16"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: PAGE_SIZE NUMERIC "256"
// Retrieval info: CONSTANT: PORT_BULK_ERASE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FAST_READ STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ILLEGAL_ERASE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_ILLEGAL_WRITE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_RDID_OUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_READ_ADDRESS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_READ_RDID STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_READ_SID STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_READ_STATUS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SECTOR_ERASE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SECTOR_PROTECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SHIFT_BYTES STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_WREN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_WRITE STRING "PORT_USED"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: addr 0 0 24 0 INPUT NODEFVAL addr[23..0]
// Retrieval info: USED_PORT: bulk_erase 0 0 0 0 INPUT NODEFVAL bulk_erase
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL busy
// Retrieval info: USED_PORT: clkin 0 0 0 0 INPUT NODEFVAL clkin
// Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL data_valid
// Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL datain[7..0]
// Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL dataout[7..0]
// Retrieval info: USED_PORT: epcs_id 0 0 8 0 OUTPUT NODEFVAL epcs_id[7..0]
// Retrieval info: USED_PORT: illegal_erase 0 0 0 0 OUTPUT NODEFVAL illegal_erase
// Retrieval info: USED_PORT: illegal_write 0 0 0 0 OUTPUT NODEFVAL illegal_write
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL rden
// Retrieval info: USED_PORT: read 0 0 0 0 INPUT NODEFVAL read
// Retrieval info: USED_PORT: read_sid 0 0 0 0 INPUT NODEFVAL read_sid
// Retrieval info: USED_PORT: sector_erase 0 0 0 0 INPUT NODEFVAL sector_erase
// Retrieval info: USED_PORT: sector_protect 0 0 0 0 INPUT NODEFVAL sector_protect
// Retrieval info: USED_PORT: shift_bytes 0 0 0 0 INPUT NODEFVAL shift_bytes
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: USED_PORT: write 0 0 0 0 INPUT NODEFVAL write
// Retrieval info: CONNECT: @clkin 0 0 0 0 clkin 0 0 0 0
// Retrieval info: CONNECT: @read 0 0 0 0 read 0 0 0 0
// Retrieval info: CONNECT: @rden 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @addr 0 0 24 0 addr 0 0 24 0
// Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
// Retrieval info: CONNECT: @read_sid 0 0 0 0 read_sid 0 0 0 0
// Retrieval info: CONNECT: epcs_id 0 0 8 0 @epcs_id 0 0 8 0
// Retrieval info: CONNECT: @write 0 0 0 0 write 0 0 0 0
// Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
// Retrieval info: CONNECT: illegal_write 0 0 0 0 @illegal_write 0 0 0 0
// Retrieval info: CONNECT: @shift_bytes 0 0 0 0 shift_bytes 0 0 0 0
// Retrieval info: CONNECT: @sector_protect 0 0 0 0 sector_protect 0 0 0 0
// Retrieval info: CONNECT: @sector_erase 0 0 0 0 sector_erase 0 0 0 0
// Retrieval info: CONNECT: @bulk_erase 0 0 0 0 bulk_erase 0 0 0 0
// Retrieval info: CONNECT: illegal_erase 0 0 0 0 @illegal_erase 0 0 0 0
// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ASMI_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneii
// Retrieval info: LIB_FILE: lpm