Generator for CSR (Control/Status Registers) mapping module
Can be useful for ASIC/FPGA designers.
Using Jinja2 ( http://jinja.pocoo.org/ ) and Python of course.
Have fun!
Generator for CSR (Control/Status Registers) mapping module
Can be useful for ASIC/FPGA designers.
Using Jinja2 ( http://jinja.pocoo.org/ ) and Python of course.
Have fun!