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fan.cpp
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fan.cpp
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/***********************************************************************
Copyright (C) 1991,
Virginia Polytechnic Institute & State University
This program was originally written by Mr. Hyung K. Lee
under the supervision of Dr. Dong S. Ha, in the Bradley
Department of Electrical Engineering, VPI&SU, in 1991.
This program is released for research use only. This program,
or any derivative thereof, may not be reproduced nor used
for any commercial product without the written permission
of the authors.
For detailed information, please contact to
Dr. Dong S. Ha
Bradley Department of Electrical Engineering
Virginia Polytechnic Institute & State University
Blacksburg, VA 24061
Ph.: (540) 231-4942
Fax: (540) 231-3362
E-Mail: [email protected]
Web: http://www.ee.vt.edu/ha
REFERENCE:
H. K. Lee and D. S. Ha, "On the Generation of Test Patterns
for Combinational Circuits," Technical Report No. 12_93,
Dep't of Electrical Eng., Virginia Polytechnic Institute
and State University.
***********************************************************************/
/**************************** HISTORY **********************************
atalanta: version 1.0 H. K. Lee, 8/15/1991
atalanta: version 1.1 H. K. Lee, 10/5/1992
Add dynamic unique path sensitization, H. K. Lee, 1/20/'94
atalanta: version 2.0 H. K. Lee, 6/30/1997
Added diagnostic mode, H. K. Lee, 6/30/1997
***********************************************************************/
/*-----------------------------------------------------------------
filename fan.c
implements the FAN algorithm.
------------------------------------------------------------------*/
#include "stdafx.h"
#include <stdio.h>
#include <stdlib.h>
#include "learn.h"
#include "sim.h"
#include "fan.h"
#include "parameter.h"
#include "define.h"
#include "macro.h"
extern GATEPTR *g_net;
extern int *g_PrimaryIn, *g_PrimaryOut, *g_iHeadGateIndex;
extern char learnmode, logmode;
extern level g_iTruthTable1[MAXGTYPE][ATALEVEL];
extern level g_iTruthTable2[MAXGTYPE][ATALEVEL][ATALEVEL];
extern STACKTYPE g_unjustStack, /* set of unjustified lines */
g_initObjStack, /* set of initial objectives */
g_curObjStack, /* set of current objectives */
g_fanObjStack, /* set of fanout objectives */
g_headObjStack, /* set of head objectives */
g_finalObjStack, /* set of final objectives */
g_DfrontierStack, /* set of Dfrotiers */
g_stack; /* stack for backtracing */
extern struct ROOTTREE g_tree;
extern STACKPTR g_pEventListStack;
extern int mac_i;
extern char gen_all_pat, no_faultsim;
extern int g_iNoPatternsForOneTime;
extern int ntest_each_limit;
extern FILE *g_fpTestFile, *g_fpLogFile;
//extern void Dprintio();
int SELECTMODE = 0; /* 0: easiest first, 1: hardest first */
/* constant for the dynamic unique path sensitization */
int dy_id = INFINITY;
GATEPTR dyn_dom[MAXGATE];
/* macros for the gate evaluation using the truthtable */
#define gate_eval1(g,v,f,i) \
if(g->inCount==1) v=g_iTruthTable1[g->type][g->inList[0]->output]; \
else if(g->inCount==2) \
v=g_iTruthTable2[g->type][g->inList[0]->output][g->inList[1]->output];\
else { \
f = (g->type==NAND) ? AND : \
(g->type==NOR) ? OR : g->type; \
v=g_iTruthTable2[f][g->inList[0]->output][g->inList[1]->output];\
for(i=2;i<g->inCount;i++) \
v=g_iTruthTable2[f][v][g->inList[i]->output]; \
v=(g->type==NAND||g->type==NOR)? A_NOT(v) : v; \
}
/* initNetAndFreach
Initialization of flags and data structures.
changed=0, all set=empty.
Identifies all reachable gates from the faulty line.
*/
void initNetAndFreach(int iNoGate, GATEPTR pFaultyGate, int iMaxDPI) //init_net
{
//INPUT: pFaultyGate
//OUTPUT: freach
register int i, j;
register GATEPTR pGate;
/* clear changed ochange and set freach */
for (i = 0; i < iNoGate; i++)
{
if (is_free(g_net[i]))
{
set(g_net[i]->changed); //don't pay attention to LFREE gates
}
else
{
reset(g_net[i]->changed);
}
reset(g_net[i]->freach);
g_net[i]->output = X;
g_net[i]->xpath = 1;
}
/* clear all sets */
for (i = 0; i < iMaxDPI; i++)
{
clearevent(i);
}
clear(g_DfrontierStack);
clear(g_unjustStack);
clear(g_initObjStack);
clear(g_curObjStack);
clear(g_fanObjStack);
clear(g_headObjStack);
clear(g_finalObjStack);
clear(g_stack);
clear(g_tree);
/* flag all reachable gates from the faulty gate */
pushevent(pFaultyGate);
for (i = pFaultyGate->dpi; i < iMaxDPI; i++)
while (!is_empty(g_pEventListStack[i]))
{
pGate = popevent(i);
reset(pGate->changed); //changed == 0 ------------> Need to handle
set(pGate->freach); //All outputs of pFaultyGate --------------> freach = 1
for (j = 0; j < pGate->outCount; j++)
{
pushevent(pGate->outList[j]);
}
}
}
/* refFaultyGateOutput
box 1 of the FAN algorithm.
Defines input and output values of the faulty gate.
Returns the level of the highest level gate in which
backward implication is required.
If a CONFLICT condition (redundant faults) occurs,
returns (-1).
*/
int refFaultyGateOutput(FAULTPTR pFault) //set_faulty_gate
{
//INPUT: pFault
//OUTPUT: iLastDPI & g_stack & many gates's ouput
register int i, iLastDPI;
register GATEPTR pGate;
level iOriginalLineValue, iLineValue;
GATEPTR pUpflowGate;
iLastDPI = 0;
pGate = pFault->gate;
pUpflowGate = (pFault->line == OUTFAULT) ? pGate : pGate->inList[pFault->line]; //get the upflow gate
iLineValue = (pFault->type == SA0) ? D : DBAR; //D: 1/0 DBAR: 0/1
/* input stuck-at faults */
if (pFault->line >= 0) /////////////pUpflowGate -> pFault -> pGate
{
/* input line pFault */
pUpflowGate->output = (iLineValue == D) ? ONE : ZERO; /* faulty line */ //get pUpflowGate's output!!
push(g_stack, pUpflowGate);
//output change ------> push into g_stack !!
switch (pGate->type)
{
case AND:
case NAND:
set(pGate->changed);
for (i = 0; i< pGate->inCount; i++)
{
if (i != pFault->line) //For every other inputs
{
if (pGate->inList[i]->output == X)
{
pGate->inList[i]->output = ONE; //activate other inputs
push(g_stack, pGate->inList[i]);
}
else if (pGate->inList[i]->output != ONE)
{
return(-1); //conflict occurs!
}
}
}
pGate->output = (pGate->type == NAND) ? A_NOT(iLineValue) : iLineValue; //get pGate's output!!
push(g_stack, pGate);
break;
case OR:
case NOR:
set(pGate->changed);
for (i = 0; i< pGate->inCount; i++)
{
if (i != pFault->line) //For every other inputs
{
if (pGate->inList[i]->output == X)
{
pGate->inList[i]->output = ZERO; //activate other inputs
push(g_stack, pGate->inList[i]);
}
else if (pGate->inList[i]->output != ZERO)
{
return(-1); //conflict occurs!
}
}
}
pGate->output = (pGate->type == NOR) ? A_NOT(iLineValue) : iLineValue; //get pGate's output!!
push(g_stack, pGate);
break;
case NOT:
pGate->output = A_NOT(iLineValue);
push(g_stack, pGate);
break;
case BUFF:
case PO:
pGate->output = iLineValue;
push(g_stack, pGate);
break;
case XOR:
case XNOR:
break; //where's code?? no support for XOR and XNOR?
}
/* schedule events */
if (pGate->output != X)
{
schedule_output(pGate); //lead to refFaultyGateOutput
}
for (i = 0; i< pGate->inCount; i++)
{
if (pGate->inList[i]->output != X) //Always != X
{
iLastDPI = max(pGate->inList[i]->dpi, iLastDPI);
schedule_input(pGate, i); //lead to refFaultyGateOutput
}
}
}
else /////////////pGate -> pFault
{
/* output line pFault */
//pGate->output = (iLineValue == D) ? ONE : ZERO;
pGate->output = iLineValue;
push(g_stack, pGate);
schedule_output(pGate);
if (is_head(pGate)) //pGate->outCount >= 2 (FANOUT)
{
set(pGate->changed);
}
//pGate->outCount == 1
else if (pGate->inCount == 1) ////////////////////pGate->inList[0] ----> pGate ----> pFault
{
set(pGate->changed);
iOriginalLineValue = (iLineValue == D) ? ONE : ZERO;
pGate->inList[0]->output = g_iTruthTable1[pGate->type][iOriginalLineValue]; //get input gate's output
push(g_stack, pGate->inList[0]);
schedule_input(pGate, 0);
iLastDPI = pGate->inList[0]->dpi;
}
else if ((iLineValue == D && (pGate->type == AND || pGate->type == NOR)) || //Why ???
(iLineValue == DBAR && (pGate->type == NAND || pGate->type == OR))) //(pGate->inCount >= 2)
{
set(pGate->changed);
iOriginalLineValue = (pGate->type == AND || pGate->type == NAND) ? ONE : ZERO;
for (i = 0; i< pGate->inCount; i++)
{
if (pGate->inList[i]->output == X)
{
pGate->inList[i]->output = iOriginalLineValue;
iLastDPI = max(pGate->inList[i]->dpi, iLastDPI);
push(g_stack, pGate->inList[i]);
schedule_input(pGate, i);
}
}
}
else
{
pushevent(pGate);
iLastDPI = pGate->dpi;
}
}
return(iLastDPI);
}
/* getFaultyGateOutput
Evaluates the faulty gate function and returns the output value.
*/
level getFaultyGateOutput(register GATEPTR pGate, FAULTPTR pFault) //faulty_gate_eval
{
//Precondition: pGate == pFault->gate
//OUTPUT: pGate->output
register int i, j;
register level iVaule;
//level fval;
logic iGateType;
if (pGate->inCount == 0) //pGate -> pFault
{
return(pGate->output);
}
if (pFault->line == OUTFAULT) //(pGate->inList[0]) -> pGate -> pFault
{
j = 0;
iVaule = pGate->inList[0]->output;
}
else //(pGate->inList[j]) -> pFault -> pGate
{
j = pFault->line;
iVaule = pGate->inList[j]->output;
if (iVaule == ZERO && pFault->type == SA1)
{
iVaule = DBAR; //iVaule = pGate->input
}
else if (iVaule == ONE && pFault->type == SA0)
{
iVaule = D; //iVaule = pGate->input
}
}
if (pGate->inCount == 1)
{
iVaule = g_iTruthTable1[pGate->type][iVaule]; //iVaule = pGate->output
}
else //pGate->inCount > 1
{
iGateType = (pGate->type == NAND) ? AND : (pGate->type == NOR) ? OR : pGate->type;
for (i = 0; i < j; i++)
iVaule = g_iTruthTable2[iGateType][iVaule][pGate->inList[i]->output];
for (++i; i< pGate->inCount; i++)
iVaule = g_iTruthTable2[iGateType][iVaule][pGate->inList[i]->output];
if (pGate->type == NAND || pGate->type == NOR)
{
iVaule = A_NOT(iVaule);
}
}
if (pFault->line == OUTFAULT) //pGate -> pFault
{
if (iVaule == ZERO && pFault->type == SA1)
{
iVaule = DBAR;
}
else if (iVaule == ONE && pFault->type == SA0)
{
iVaule = D;
}
}
return(iVaule);
}
/* eval
Evaluate good circuit in forward and backward completely.
Set changed flag if the gate is evaluated permanently.
Push the evaluated gate to stack for backtracking.
Schedule next events.
*/
status eval(register GATEPTR pGate, FAULTPTR pFault)
{
register int i, j;
register level iValue, iTempValue;
int iNumX;
logic iTempValue2;
GATEPTR *pGateInList;
reset(pGate->changed);
pGateInList = pGate->inList;
/* if a line is a head line, stop */
if (is_head(pGate))
{
set(pGate->changed);
return(FORWARD);
}
/* faulty pGate evaluation */
if (pGate == pFault->gate)
{
iValue = getFaultyGateOutput(pGate, pFault);
if (iValue == X)
{
if (pGate->output != X)
{
for (i = iNumX = 0; i< pGate->inCount; i++)
if (pGateInList[i]->output == X)
{
iNumX++; j = i;
}
if (iNumX == 1)
{
/* backward implication */
iValue = (pGate->output == D) ? ONE : (pGate->output == DBAR) ? ZERO : pGate->output;
iValue = g_iTruthTable1[pGate->type][iValue];
switch (pGate->type)
{
case XOR:
case XNOR:
iTempValue = (j == 0) ? pGateInList[1]->output : pGateInList[0]->output;
if (iTempValue == ONE)
{
iValue = g_iTruthTable1[NOT][iValue];
}
break;
}
pGateInList[j]->output = iValue;
set(pGate->changed);
push(g_stack, pGateInList[j]);
schedule_input(pGate, j);
return(BACKWARD);
}
else
{
push(g_unjustStack, pGate);
}
}
}
else if (iValue == pGate->output)
{
set(pGate->changed);
}
else if (pGate->output == X)
{
/* forward imp */
set(pGate->changed);
pGate->output = iValue;
push(g_stack, pGate);
schedule_output(pGate);
}
else
{
return(CONFLICT);
}
return(FORWARD);
}
/* fault free pGate evaluation */
gate_eval1(pGate, iValue, iTempValue2, i);
if (iValue == pGate->output)
{
/* no event */
if (iValue != X)
{
set(pGate->changed);
}
return(FORWARD);
}
if (pGate->output == X)
{
/* forward implication */
pGate->output = iValue;
push(g_stack, pGate);
set(pGate->changed);
schedule_output(pGate);
return(FORWARD);
}
if (iValue != X)
{
return(CONFLICT);
} /* conflict */
/* backward implication */
switch (pGate->type)
{
case AND:
case NAND:
case OR:
case NOR:
iTempValue = (pGate->type == AND || pGate->type == NOR) ? ONE : ZERO;
if (pGate->output == iTempValue)
{
set(pGate->changed);
for (i = 0; i< pGate->inCount; i++)
if (pGateInList[i]->output == X)
{
pGateInList[i]->output = g_iTruthTable1[pGate->type][iTempValue];
push(g_stack, pGateInList[i]);
schedule_input(pGate, i);
}
i = BACKWARD;
}
else
{
for (i = iNumX = 0; i< pGate->inCount; i++)
if (pGateInList[i]->output == X)
{
iNumX++; j = i;
}
if (iNumX == 1)
{
pGateInList[j]->output = g_iTruthTable1[pGate->type][pGate->output];
set(pGate->changed);
push(g_stack, pGateInList[j]);
schedule_input(pGate, j);
i = BACKWARD;
}
else
{
push(g_unjustStack, pGate);
i = FORWARD;
}
}
break;
case BUFF:
case NOT:
case PO:
pGateInList[0]->output = g_iTruthTable1[pGate->type][pGate->output];
set(pGate->changed);
push(g_stack, pGateInList[0]);
schedule_input(pGate, 0);
i = BACKWARD;
break;
case XOR:
case XNOR:
for (i = iNumX = 0; i< pGate->inCount; i++)
if (pGateInList[i]->output == X)
{
iNumX++; j = i;
}
if (iNumX == 1)
{
iTempValue = (j == 0) ? pGateInList[1]->output : pGateInList[0]->output;
iValue = g_iTruthTable1[pGate->type][pGate->output];
if (iTempValue == ONE)
{
iValue = g_iTruthTable1[NOT][iValue];
}
pGateInList[j]->output = iValue;
set(pGate->changed);
push(g_stack, pGateInList[j]);
schedule_input(pGate, j);
i = BACKWARD;
}
else
{
push(g_unjustStack, pGate);
i = FORWARD;
}
break;
}
#ifdef LEARNFLG
if (learnmode == 'y' && pGate->plearn != NULL)
{
if (pGate->output == ZERO || pGate->output == ONE)
{
switch (imply_learn(pGate, pGate->output))
{
case BACKWARD:
i = BACKWARD; break;
case CONFLICT:
i = CONFLICT; break;
}
}
}
#endif
return(i);
}
/* implyForwardAndBackward
box 3 of the FAN algorithm.
Forward and backward implication.
*/
bool implyForwardAndBackward(int iMaxDPI, bool bBackward, int iLastDPI, FAULTPTR pFault) //imply
{
register int i, iStartDPI;
status iStatus;
GATEPTR pGate;
if (bBackward)
{
iStartDPI = iLastDPI;
}
else
{
iStartDPI = 0;
}
while (TRUE)
{
/* backward implication */
if (bBackward)
{
for (i = iStartDPI; i >= 0; i--) //clear all stacks from 0 to iStartDPI
{
while (!is_empty(g_pEventListStack[i]))
{
pGate = pop(g_pEventListStack[i]);
if ((iStatus = eval(pGate, pFault)) == CONFLICT)
{
return(FALSE); //conflict!!
}
}
}
}
/* forward implication */
reset(bBackward);
for (i = 0; i < iMaxDPI; i++)
{
while (!is_empty(g_pEventListStack[i]))
{
if ((iStatus = eval(pop(g_pEventListStack[i]), pFault)) == CONFLICT)
{
return(FALSE); //conflict!!
}
else if (iStatus == BACKWARD)
{
iStartDPI = i - 1;
set(bBackward);
break;
}
}
if (bBackward)
{
break;
}
}
if (!bBackward)
{
break;
}
}
return(TRUE);
}
/* unique_sensitize
Box 6 in Fig 9 of the FAN algorithm.
Predetermines all neccessary inputs of the uniquely
sensitizable path.
Returns -1 if no sensitized values exist.
Otherwise, returns the highest depth for backward implication.
*/
int unique_sensitize(register GATEPTR pGate, GATEPTR pFaultyGate)
{
register int i;
register LINKPTR pLink;
register GATEPTR pNextGate;
int iLastDPI; /* the largest depth of sensitized lines */
bool bFlag;
level iValue;
iLastDPI = (-1);
/* sensitize the current pGate */
if (pGate != pFaultyGate)
{
//pFaultyGate ----------> pGate
//other Gates ---iValue---> pGate
iValue = (pGate->type == AND || pGate->type == NAND) ? ONE :
(pGate->type == OR || pGate->type == NOR) ? ZERO : X;
if (iValue != X)
{
for (i = 0; i< pGate->inCount; i++)
if (pGate->inList[i]->output == X)
{
pGate->inList[i]->output = iValue;
iLastDPI = max(pGate->inList[i]->dpi, iLastDPI);
push(g_stack, pGate->inList[i]);
schedule_input(pGate, i);
}
}
}
/* sensitize pNextGate path */
while (pGate != NULL)
{
if (pGate->outCount == 0)
{
break;
}
else if (pGate->outCount == 1) //pGate -> pNextGate
{
pNextGate = pGate->outList[0];
}
else if (pGate->u_path == NULL)
{
break;
}
else
{
pNextGate = pGate->u_path->ngate;
}
//pGate -------------------> pNextGate
//pNextGate->inList[i] ---iValue---> pNextGate
iValue = (pNextGate->type == AND || pNextGate->type == NAND) ? ONE :
(pNextGate->type == OR || pNextGate->type == NOR) ? ZERO :
X;
if (iValue != X) //////////if iValue == X, then pNextGate can't have multiple outputs!!!
{
if (pGate->outCount == 1)
{
/* one fanout */
for (i = 0; i< pNextGate->inCount; i++)
if (pNextGate->inList[i] != pGate && pNextGate->inList[i]->output == X)
{
pNextGate->inList[i]->output = iValue;
iLastDPI = max(pNextGate->inList[i]->dpi, iLastDPI);
push(g_stack, pNextGate->inList[i]);
schedule_input(pNextGate, i);
}
}
else //pGate->outCount > 1
{
/* multiple fanout */
for (i = 0; i< pNextGate->inCount; i++)
if (pNextGate->inList[i]->output == X)
{
set(bFlag);
for (pLink = pGate->u_path->next; pLink != NULL; pLink = pLink->next)
if (pNextGate->inList[i] == pLink->ngate)
{
reset(bFlag);
break;
}
if (bFlag)
{
pNextGate->inList[i]->output = iValue;
iLastDPI = max(pNextGate->inList[i]->dpi, iLastDPI);
push(g_stack, pNextGate->inList[i]);
schedule_input(pNextGate, i);
}
}
}
}
pGate = pNextGate;
}
return(iLastDPI);
}
/*------dynamic_unique_sensitize---------------------------------
Dynamic unique path sensitization
Finds dynamic dominators for the given D-frontier gates
and assigns mandatory signals.
Algorithm:
This is a three step algorithm finding dynamic dominators.
1. Propagate all D-frontier gates in the forward order.
2. Trace back in the backward order ---
This step finds all X-paths.
3. Find dynamic dominators by tracing X-paths.
Assigns non-controlling values to inputs of dynamic
dominators which can be be reachable from D-frontier gates.
Implemented by H. K. Lee, 1/20/1994
---------------------------------------------------------------------*/
int dynamic_unique_sensitize(GATEPTR *Dfront, int nod, int maxdpi, GATEPTR *dom_array, GATEPTR faulty_gate)
{
int ndom = 0, ngate;
int dy_id2;
register int i, j, k; //,l,m,n;
register GATEPTR gut, next; //gate, g not used
//GATEPTR Dominator;
int ndominator = 0,no_dom = 0; //new_dom not used
int flag = FALSE;
int debug = TRUE;
int v1,send = -1;
GATEPTR xpo[MAXPO]; int nxpo;
/* pass 1: D-frontier propagation */
++dy_id;
for (i = nxpo = 0; i <= nod; i++)
{
gut = Dfront[i];
if (gut->freach1 < dy_id)
{
push(g_pEventListStack[gut->dpi], gut);
gut->freach1 = dy_id;
}
}
for (i = 0; i < maxdpi; i++)
{
while (!is_empty(g_pEventListStack[i]))
{
gut = pop(g_pEventListStack[i]);
if (gut->type == PO)
{
xpo[nxpo++] = gut;
}
for (j = 0; j< gut->outCount; j++)
{
next = gut->outList[j];
if ((next->output == X) && (next->freach1 < dy_id))
{
push(g_pEventListStack[next->dpi], next);
next->freach1 = dy_id;
}
}
}
}
/* pass 2: Backward propagation --- X-path */
dy_id2 = dy_id + 1;
for (i = 0; i < nxpo; i++)
{
gut = xpo[i];
gut->freach1 = dy_id2;
for (j = 0; j< gut->inCount; j++)
{
next = gut->inList[j];
if (next->freach1 == dy_id)
{
push(g_pEventListStack[next->dpi], next);
next->freach1 = dy_id2;
}
}
}
for (i = maxdpi - 1; i >= 0; i--)
while (!is_empty(g_pEventListStack[i]))
{
gut = pop(g_pEventListStack[i]);
for (j = 0; j< gut->inCount; j++)
{
next = gut->inList[j];
if (next->freach1 == dy_id)
{
push(g_pEventListStack[next->dpi], next);
next->freach1 = dy_id2;
}
}
}
/* pass 3: Compute dominators */
dy_id = dy_id2 + 1;
for (i = ngate = 0; i <= nod; i++)
{
gut = Dfront[i];
push(g_pEventListStack[gut->dpi], gut);
ngate++;
gut->freach1 = dy_id;
}
for (i = k = 0; i < maxdpi; i++)
{
if (ngate == 1 && g_pEventListStack[i].last == 0)
{
dom_array[k++] = g_pEventListStack[i].list[0];
}
while (!is_empty(g_pEventListStack[i]))
{
gut = pop(g_pEventListStack[i]);
ngate--;
if (gut->type == PO)
{
ngate = INFINITY; break;
}
for (j = 0; j< gut->outCount; j++)
{
next = gut->outList[j];
if (next->freach1 == dy_id2)
{
push(g_pEventListStack[next->dpi], next);
next->freach1 = dy_id;
ngate++;
}
}
}
if (ngate == INFINITY)
{
break;
}
}
/* Assign non-controlling values to dominators */
send = (-1);
while (--k >= 0)
{
gut = dom_array[k];
/*
printf("dominator: gut=%d #Dfrontier=%d\n",gut->index,nod+1);
*/
if (gut == faulty_gate)
{
continue;
}
v1 = (gut->type == AND || gut->type == NAND) ? ONE : (gut->type == OR || gut->type == NOR) ? ZERO : X;
if (v1 != X)
{
for (i = 0; i< gut->inCount; i++)
{
next = gut->inList[i];
if (next->freach1 < dy_id && next->output == X)
{
next->output = v1;
/*
printf("\tmandatory signal assignment: gut=%d val=%d\n", next->index, v1);
*/
send = max(next->dpi, send);
push(g_stack, next);
schedule_input(gut, i);
}
}
}
}
return(send);
}
/* closest_po
Finds the gate closiest from a primary output.
*/
GATEPTR closest_po(STACKPTR pObjectiveStack, int *piClose)
{
register int i, iDPO;
register GATEPTR pGate;
if (ptr_is_empty(pObjectiveStack))
{
return(NULL);
}
*piClose = pObjectiveStack->last;
iDPO = pObjectiveStack->list[*piClose]->dpo;
for (i = (pObjectiveStack->last) - 1; i >= 0; i--)
if (pObjectiveStack->list[i]->dpo < iDPO)
{
iDPO = pObjectiveStack->list[i]->dpo;
*piClose = i;
}
pGate = pObjectiveStack->list[*piClose];
return(pGate);
}
/* select_hardest
Finds the hardest gate to satisfy
*/
GATEPTR select_hardest(STACKPTR pObjectiveStack, int *piClose)
{
register int i, iDPO;
register GATEPTR pGate;
if (ptr_is_empty(pObjectiveStack))
{
return(NULL);
}
*piClose = pObjectiveStack->last;
iDPO = pObjectiveStack->list[*piClose]->dpo;
for (i = (pObjectiveStack->last) - 1; i >= 0; i--)
if (pObjectiveStack->list[i]->dpo > iDPO)
{
iDPO = pObjectiveStack->list[i]->dpo;
*piClose = i;
}
pGate = pObjectiveStack->list[*piClose];
return(pGate);
}
/* backtrace
Fiqure 8, of the FAN algorithm.
Multiple backtrace.
*/
status backtrace(status iState)
{
int i;
register int j;
register level v1;
GATEPTR a_curr_obj, *input;
int n0, n1, nn0, nn1;
int easiest, easy_cont;
/* box 1: Initialization of objective and its logic level */
if (iState == 81)
{
copy(g_initObjStack, g_curObjStack, i);
for (i = 0; i <= g_initObjStack.last; i++)
{