Add support for arm64e (Fixes #4490)

python_bindings/src/halide/halide_/PyEnums.cpp

@@ -180,6 +180,7 @@ void define_enums(py::module &m) {
         .value("LLVMLargeCodeModel", Target::Feature::LLVMLargeCodeModel)
         .value("RVV", Target::Feature::RVV)
         .value("ARMv81a", Target::Feature::ARMv81a)
+        .value("ARM64e", Target::Feature::ARM64e)
         .value("SanitizerCoverage", Target::Feature::SanitizerCoverage)
         .value("ProfileByTimer", Target::Feature::ProfileByTimer)
         .value("SPIRV", Target::Feature::SPIRV)

src/CodeGen_ARM.cpp

@@ -2445,9 +2445,13 @@ string CodeGen_ARM::mcpu_target() const {
         }
     } else {
         if (target.os == Target::IOS) {
-            return "cyclone";
+            if (target.has_feature(Target::ARM64e)) {
+                return "apple-a12";
+            } else {
+                return "cyclone";  // aka Apple A7
+            }
         } else if (target.os == Target::OSX) {
-            return "apple-a12";
+            return "apple-m1";
         } else if (target.has_feature(Target::SVE2)) {
             return "cortex-x1";
         } else {
@@ -2482,7 +2486,7 @@ string CodeGen_ARM::mattrs() const {
         }
     } else {
         // TODO: Should Halide's SVE flags be 64-bit only?
-        // TODO: Sound we ass "-neon" if NoNEON is set? Does this make any sense?
+        // TODO: Sound we add "-neon" if NoNEON is set? Does this make any sense?
         if (target.has_feature(Target::SVE2)) {
             attrs.emplace_back("+sve2");
         } else if (target.has_feature(Target::SVE)) {

src/LLVM_Runtime_Linker.cpp

@@ -486,7 +486,11 @@ llvm::Triple get_triple_for_target(const Target &target) {
         } else {
             user_assert(target.bits == 64) << "Target bits must be 32 or 64\n";
 #ifdef WITH_AARCH64
-            triple.setArch(llvm::Triple::aarch64);
+            if (target.has_feature(Target::ARM64e)) {
+                triple.setArch(llvm::Triple::aarch64, llvm::Triple::AArch64SubArch_arm64e);
+            } else {
+                triple.setArch(llvm::Triple::aarch64);
+            }
 #else
             user_error << "AArch64 llvm target not enabled in this build of Halide\n";
 #endif

src/Target.cpp

@@ -581,6 +581,7 @@ const std::map<std::string, Target::Feature> feature_name_map = {
     {"llvm_large_code_model", Target::LLVMLargeCodeModel},
     {"rvv", Target::RVV},
     {"armv81a", Target::ARMv81a},
+    {"arm64e", Target::ARM64e},
     {"sanitizer_coverage", Target::SanitizerCoverage},
     {"profile_by_timer", Target::ProfileByTimer},
     {"spirv", Target::SPIRV},
@@ -1385,9 +1386,10 @@ bool Target::get_runtime_compatible_target(const Target &other, Target &result)
     // clang-format on
 
     // clang-format off
-    const std::array<Feature, 15> intersection_features = {{
+    const std::array<Feature, 16> intersection_features = {{
         ARMv7s,
         ARMv81a,
+        ARM64e,
         AVX,
         AVX2,
         AVX512,

src/Target.h

@@ -155,6 +155,7 @@ struct Target {
         LLVMLargeCodeModel = halide_llvm_large_code_model,
         RVV = halide_target_feature_rvv,
         ARMv81a = halide_target_feature_armv81a,
+        ARM64e = halide_target_feature_arm64e,
         SanitizerCoverage = halide_target_feature_sanitizer_coverage,
         ProfileByTimer = halide_target_feature_profile_by_timer,
         SPIRV = halide_target_feature_spirv,

src/runtime/HalideRuntime.h

@@ -1435,6 +1435,7 @@ typedef enum halide_target_feature_t {
     halide_llvm_large_code_model,                 ///< Use the LLVM large code model to compile
     halide_target_feature_rvv,                    ///< Enable RISCV "V" Vector Extension
     halide_target_feature_armv81a,                ///< Enable ARMv8.1-a instructions
+    halide_target_feature_arm64e,                 ///< Enable ARM64e (requires ARMv8.3a)
     halide_target_feature_sanitizer_coverage,     ///< Enable hooks for SanitizerCoverage support.
     halide_target_feature_profile_by_timer,       ///< Alternative to halide_target_feature_profile using timer interrupt for systems without threads or applicartions that need to avoid them.
     halide_target_feature_spirv,                  ///< Enable SPIR-V code generation support.

test/correctness/cross_compilation.cpp

@@ -21,6 +21,7 @@ int main(int argc, char **argv) {
         "arm-64-android",
         "arm-64-android-hvx",
         "arm-64-ios",
+        "arm-64-ios-arm64e",
         "arm-64-linux",
         "arm-64-noos-semihosting",
         "arm-64-windows",

test/correctness/simd_op_check.h

@@ -121,6 +121,7 @@ class SimdOpCheckTest {
                  Target::ARMFp16,
                  Target::ARMv7s,
                  Target::ARMv81a,
+                 Target::ARM64e,
                  Target::AVX,
                  Target::AVX2,
                  Target::AVX512,