From dc81db24aa8dec807b2ab95623dcc3a89715c88a Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Fri, 24 Jun 2022 15:02:37 +0200 Subject: [PATCH] Connect PLL's clock enable to dynamic clock control logic Signed-off-by: Robert Szczepanski --- soc/hps_proto2_platform.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/soc/hps_proto2_platform.py b/soc/hps_proto2_platform.py index 118d031ac..d8542b66c 100644 --- a/soc/hps_proto2_platform.py +++ b/soc/hps_proto2_platform.py @@ -7,9 +7,9 @@ from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc from litex.build.lattice import LatticePlatform, oxide from litex.build.lattice.programmer import LatticeProgrammer -from litex.soc.cores.clock import NXOSCA, NXPLL +from litex.soc.cores.clock import NXOSCA # from litex.soc.cores.ram import NXLRAM -from hps_lattice_nx import NXLRAM +from hps_lattice_nx import NXLRAM, NXPLL hps_io = [ ("done", 0, Pins("A5"), IOStandard("LVCMOS18H")), @@ -100,6 +100,12 @@ def __init__(self, platform, sys_clk_freq): AsyncResetSynchronizer(self.cd_cfu, ~self.sys_pll.locked | (por_counter != 0)), ] + def do_finalize(self): + self.comb += [ + self.sys_pll.enable.sys.eq(self.sys_clk_enable), + self.sys_pll.enable.cfu.eq(self.cfu_clk_enable), + ] + _nextpnr_report_filename = 'nextpnr-nexus-report.json'