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DE2_115.map.rpt
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DE2_115.map.rpt
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Analysis & Synthesis report for DE2_115
Sun Apr 15 16:00:32 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. State Machine - |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state
11. State Machine - |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state2
12. State Machine - |DE2_115|uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state2
13. State Machine - |DE2_115|uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state1
14. Registers Removed During Synthesis
15. Removed Registers Triggering Further Register Optimizations
16. General Register Statistics
17. Multiplexer Restructuring Statistics (Restructuring Performed)
18. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component
19. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated
20. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p
21. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p
22. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|altsyncram_2t01:fifo_ram
23. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp
24. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12
25. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp
26. Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15
27. Source assignments for uart_top:uart_top|my_ram:my_ram_rec|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated
28. Source assignments for uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated
29. Parameter Settings for User Entity Instance: uart_top:uart_top|rec:uartrec
30. Parameter Settings for User Entity Instance: uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component
31. Parameter Settings for User Entity Instance: uart_top:uart_top|my_ram:my_ram_rec|altsyncram:altsyncram_component
32. Parameter Settings for User Entity Instance: uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram
33. Parameter Settings for User Entity Instance: uart_top:uart_top|send:uartsend
34. Parameter Settings for User Entity Instance: uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component
35. Parameter Settings for User Entity Instance: uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram
36. dcfifo Parameter Settings by Entity Instance
37. altsyncram Parameter Settings by Entity Instance
38. Port Connectivity Checks: "uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram"
39. Port Connectivity Checks: "uart_top:uart_top|send:uartsend"
40. Port Connectivity Checks: "uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram"
41. Port Connectivity Checks: "uart_top:uart_top|my_ram:my_ram_rec"
42. Port Connectivity Checks: "uart_top:uart_top|rec:uartrec"
43. Elapsed Time Per Partition
44. Analysis & Synthesis Messages
45. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Apr 15 16:00:32 2018 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; DE2_115 ;
; Top-level Entity Name ; DE2_115 ;
; Family ; Cyclone IV E ;
; Total logic elements ; 84 ;
; Total combinational functions ; 83 ;
; Dedicated logic registers ; 57 ;
; Total registers ; 57 ;
; Total pins ; 512 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 2,048 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE115F29C7 ; ;
; Top-level entity name ; DE2_115 ; DE2_115 ;
; Family name ; Cyclone IV E ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------+---------+
; FIFO/contr_fifo_send_ram.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/FIFO/contr_fifo_send_ram.v ; ;
; FIFO/contr_fifo_rec_ram.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/FIFO/contr_fifo_rec_ram.v ; ;
; RAM/my_ram.v ; yes ; User Wizard-Generated File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/RAM/my_ram.v ; ;
; FIFO/my_fifo.v ; yes ; User Wizard-Generated File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/FIFO/my_fifo.v ; ;
; UART/send.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/UART/send.v ; ;
; UART/rec.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/UART/rec.v ; ;
; main/uart_top.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/main/uart_top.v ; ;
; main/DE2_115.v ; yes ; User Verilog HDL File ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/main/DE2_115.v ; ;
; dcfifo.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf ; ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc ; ;
; a_graycounter.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc ; ;
; a_fefifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc ; ;
; a_gray2bin.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc ; ;
; dffpipe.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc ; ;
; alt_sync_fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; altsyncram_fifo.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ; ;
; aglobal131.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc ; ;
; db/dcfifo_lvg1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/dcfifo_lvg1.tdf ; ;
; db/a_graycounter_nn6.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/a_graycounter_nn6.tdf ; ;
; db/a_graycounter_j5c.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/a_graycounter_j5c.tdf ; ;
; db/altsyncram_2t01.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/altsyncram_2t01.tdf ; ;
; db/alt_synch_pipe_v5d.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/alt_synch_pipe_v5d.tdf ; ;
; db/dffpipe_uu8.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/dffpipe_uu8.tdf ; ;
; db/alt_synch_pipe_06d.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/alt_synch_pipe_06d.tdf ; ;
; db/dffpipe_vu8.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/dffpipe_vu8.tdf ; ;
; db/cmpr_b66.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/cmpr_b66.tdf ; ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc ; ;
; db/altsyncram_75g1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/db/altsyncram_75g1.tdf ; ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 84 ;
; ; ;
; Total combinational functions ; 83 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 28 ;
; -- 3 input functions ; 10 ;
; -- <=2 input functions ; 45 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 54 ;
; -- arithmetic mode ; 29 ;
; ; ;
; Total registers ; 57 ;
; -- Dedicated logic registers ; 57 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 512 ;
; Total memory bits ; 2048 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 65 ;
; Total fan-out ; 1177 ;
; Average fan-out ; 0.90 ;
+---------------------------------------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
; |DE2_115 ; 83 (0) ; 57 (0) ; 2048 ; 0 ; 0 ; 0 ; 512 ; 0 ; |DE2_115 ; work ;
; |uart_top:uart_top| ; 83 (0) ; 57 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top ; work ;
; |contr_fifo_send_ram:contr_fifo_send_ram| ; 32 (32) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram ; work ;
; |my_ram:my_ram_send| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top|my_ram:my_ram_send ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component ; work ;
; |altsyncram_75g1:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated ; work ;
; |send:uartsend| ; 51 (51) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_115|uart_top:uart_top|send:uartsend ; work ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
; uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 8 ; -- ; -- ; 2048 ; None ;
+----------------------------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------+---------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------+---------------------------------------------------------------------------+
; Altera ; RAM: 1-PORT ; N/A ; N/A ; N/A ; |DE2_115|uart_top:uart_top|my_ram:my_ram_rec ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/RAM/my_ram.v ;
; Altera ; RAM: 1-PORT ; N/A ; N/A ; N/A ; |DE2_115|uart_top:uart_top|my_ram:my_ram_send ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/RAM/my_ram.v ;
; Altera ; FIFO ; N/A ; N/A ; N/A ; |DE2_115|uart_top:uart_top|my_fifo:rec_fifo ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/FIFO/my_fifo.v ;
+--------+--------------+---------+--------------+--------------+-----------------------------------------------+---------------------------------------------------------------------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------+
; State Machine - |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state ;
+----------+----------+----------+---------------------------------------------------------+
; Name ; state.00 ; state.10 ; state.01 ;
+----------+----------+----------+---------------------------------------------------------+
; state.00 ; 0 ; 0 ; 0 ;
; state.01 ; 1 ; 0 ; 1 ;
; state.10 ; 1 ; 1 ; 0 ;
+----------+----------+----------+---------------------------------------------------------+
Encoding Type: One-Hot
+-------------------------------------------------------------------------------------------+
; State Machine - |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state2 ;
+---------------+--------------+---------------+---------------+----------------------------+
; Name ; state2.wtran ; state2.wwtran ; state2.wwrite ; state2.00 ;
+---------------+--------------+---------------+---------------+----------------------------+
; state2.00 ; 0 ; 0 ; 0 ; 0 ;
; state2.wwrite ; 0 ; 0 ; 1 ; 1 ;
; state2.wwtran ; 0 ; 1 ; 0 ; 1 ;
; state2.wtran ; 1 ; 0 ; 0 ; 1 ;
+---------------+--------------+---------------+---------------+----------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------+
; State Machine - |DE2_115|uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state2 ;
+---------------+-------------------------------------------------------------------------+
; Name ; state2.wwrite ;
+---------------+-------------------------------------------------------------------------+
; state2.rfree ; 0 ;
; state2.wwrite ; 1 ;
+---------------+-------------------------------------------------------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------+
; State Machine - |DE2_115|uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state1 ;
+--------------+-------------+------------+-----------------------------------------------+
; Name ; state1.free ; state1.wat ; state1.write ;
+--------------+-------------+------------+-----------------------------------------------+
; state1.free ; 0 ; 0 ; 0 ;
; state1.write ; 1 ; 0 ; 1 ;
; state1.wat ; 1 ; 1 ; 0 ;
+--------------+-------------+------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|addr[0] ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|wren ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|addr[1..7] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|UartBuff[1..8] ; Lost fanout ;
; uart_top:uart_top|send:uartsend|Datainbuf[0] ; Stuck at GND due to stuck port data_in ;
; uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state2~8 ; Lost fanout ;
; uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|state2~9 ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state2~6 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[1] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[1] ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|en_2 ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|en_1 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[1] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[1] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a4 ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|rdreq ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a2 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a3 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a0 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a1 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[1] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|en ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a4 ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|wrreq ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[4] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a2 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[2] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a3 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[3] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a0 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a1 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[1] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|parity6 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[0..4] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|count[0..3] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|count_bit[1..3] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|StartF ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|cnt[0..15] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|parity9 ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|sub_parity7a[0,1] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|count_bit[0] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|UartBuff[0] ; Lost fanout ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|sub_parity10a[0,1] ; Lost fanout ;
; uart_top:uart_top|rec:uartrec|bit_collect[0..2] ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state2.wwrite ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state1.write ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state1.wat ; Lost fanout ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state1.free ; Lost fanout ;
; Total Number of Removed Registers = 110 ; ;
+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------------------------+--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+--------------------------------------------------------------------------------------------------+--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|addr[0] ; Lost Fanouts ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|rdptr_g[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe14a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a4, ;
; ; ; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|rdreq, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a2, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a3, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a0, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|counter5a1, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12|dffe13a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|parity6, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|delayed_wrptr_g[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|sub_parity7a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p|sub_parity7a[0], ;
; ; ; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|state2.wwrite ;
; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|en_2 ; Lost Fanouts ; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|en_1, ;
; ; ; uart_top:uart_top|rec:uartrec|en, uart_top:uart_top|rec:uartrec|count[3], ;
; ; ; uart_top:uart_top|rec:uartrec|count[2], uart_top:uart_top|rec:uartrec|count[1], ;
; ; ; uart_top:uart_top|rec:uartrec|count[0], uart_top:uart_top|rec:uartrec|count_bit[3], ;
; ; ; uart_top:uart_top|rec:uartrec|count_bit[2], ;
; ; ; uart_top:uart_top|rec:uartrec|count_bit[1], uart_top:uart_top|rec:uartrec|StartF, ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[15], uart_top:uart_top|rec:uartrec|cnt[14], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[13], uart_top:uart_top|rec:uartrec|cnt[12], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[11], uart_top:uart_top|rec:uartrec|cnt[10], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[9], uart_top:uart_top|rec:uartrec|cnt[7], ;
; ; ; uart_top:uart_top|rec:uartrec|count_bit[0], ;
; ; ; uart_top:uart_top|rec:uartrec|UartBuff[0], ;
; ; ; uart_top:uart_top|rec:uartrec|bit_collect[1], ;
; ; ; uart_top:uart_top|rec:uartrec|bit_collect[2], ;
; ; ; uart_top:uart_top|rec:uartrec|bit_collect[0] ;
; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[4] ; Lost Fanouts ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|wrptr_g[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe17a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a4, ;
; ; ; uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram|wrreq, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[4], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a2, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[2], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a3, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[3], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a0, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[0], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|counter8a1, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15|dffe16a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|parity9, ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|sub_parity10a[1], ;
; ; ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p|sub_parity10a[0] ;
; uart_top:uart_top|rec:uartrec|UartBuff[8] ; Lost Fanouts ; uart_top:uart_top|rec:uartrec|cnt[8], uart_top:uart_top|rec:uartrec|cnt[6], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[5], uart_top:uart_top|rec:uartrec|cnt[4], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[3], uart_top:uart_top|rec:uartrec|cnt[2], ;
; ; ; uart_top:uart_top|rec:uartrec|cnt[1], uart_top:uart_top|rec:uartrec|cnt[0] ;
+--------------------------------------------------------------------------------------------------+--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 57 ;
; Number of registers using Synchronous Clear ; 34 ;
; Number of registers using Synchronous Load ; 2 ;
; Number of registers using Asynchronous Clear ; 25 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 31 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------+
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |DE2_115|uart_top:uart_top|send:uartsend|cnt[12] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |DE2_115|uart_top:uart_top|send:uartsend|Datainbuf[5] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE2_115|uart_top:uart_top|rec:uartrec|count[1] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |DE2_115|uart_top:uart_top|rec:uartrec|count_bit[3] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |DE2_115|uart_top:uart_top|send:uartsend|bincnt[3] ;
; 8:1 ; 8 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|addr[7] ;
; 8:1 ; 3 bits ; 15 LEs ; 6 LEs ; 9 LEs ; No ; |DE2_115|uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram|Selector17 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+----------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+----------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+----------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated ;
+---------------------------------------+-------+------+-------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------------+-------+------+-------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ;
; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ;
; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2 ; - ; - ;
; POWER_UP_LEVEL ; LOW ; - ; wrptr_g ;
+---------------------------------------+-------+------+-------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_nn6:rdptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ;
; POWER_UP_LEVEL ; HIGH ; - ; parity6 ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|a_graycounter_j5c:wrptr_g1p ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ;
; POWER_UP_LEVEL ; HIGH ; - ; parity9 ;
+----------------+-------+------+----------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|altsyncram_2t01:fifo_ram ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF ; - ; - ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_v5d:rs_dgwp|dffpipe_uu8:dffpipe12 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF ; - ; - ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ;
+-----------------------------+------------------------+------+---------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component|dcfifo_lvg1:auto_generated|alt_synch_pipe_06d:ws_dgrp|dffpipe_vu8:dffpipe15 ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_ram:my_ram_rec|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component|altsyncram_75g1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------------------------------------------------------+
+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|rec:uartrec ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------+
; cout ; 325 ; Signed Integer ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component ;
+-------------------------+--------------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+--------------+----------------------------------------------------------------+
; WIDTH_BYTEENA ; 1 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 8 ; Signed Integer ;
; LPM_NUMWORDS ; 16 ; Signed Integer ;
; LPM_WIDTHU ; 4 ; Signed Integer ;
; LPM_SHOWAHEAD ; OFF ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; DELAY_RDUSEDW ; 1 ; Untyped ;
; DELAY_WRUSEDW ; 1 ; Untyped ;
; RDSYNC_DELAYPIPE ; 4 ; Signed Integer ;
; WRSYNC_DELAYPIPE ; 4 ; Signed Integer ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; ADD_USEDW_MSB_BIT ; OFF ; Untyped ;
; WRITE_ACLR_SYNCH ; OFF ; Untyped ;
; READ_ACLR_SYNCH ; OFF ; Untyped ;
; CBXI_PARAMETER ; dcfifo_lvg1 ; Untyped ;
+-------------------------+--------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|my_ram:my_ram_rec|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 8 ; Signed Integer ;
; NUMWORDS_A ; 256 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_75g1 ; Untyped ;
+------------------------------------+----------------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram ;
+----------------+-------+-----------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------------------------------------+
; free ; 00 ; Unsigned Binary ;
; write ; 01 ; Unsigned Binary ;
; wat ; 10 ; Unsigned Binary ;
; rfree ; 00 ; Unsigned Binary ;
; wwrite ; 01 ; Unsigned Binary ;
; wwtran ; 10 ; Unsigned Binary ;
; wtran ; 11 ; Unsigned Binary ;
; count1 ; 999 ; Signed Integer ;
; countk ; 999 ; Signed Integer ;
; countM ; 499 ; Signed Integer ;
+----------------+-------+-----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|send:uartsend ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------------+
; cout ; 5207 ; Signed Integer ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+-------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+-------------------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 8 ; Signed Integer ;
; NUMWORDS_A ; 256 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; CBXI_PARAMETER ; altsyncram_75g1 ; Untyped ;
+------------------------------------+----------------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram ;
+----------------+-------+-------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------------------------------------+
; rfree ; 00 ; Unsigned Binary ;
; wwrite ; 01 ; Unsigned Binary ;
; wwtran ; 10 ; Unsigned Binary ;
; wtran ; 11 ; Unsigned Binary ;
+----------------+-------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance ;
+----------------------------+------------------------------------------------------------+
; Name ; Value ;
+----------------------------+------------------------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; uart_top:uart_top|my_fifo:rec_fifo|dcfifo:dcfifo_component ;
; -- FIFO Type ; Dual Clock ;
; -- LPM_WIDTH ; 8 ;
; -- LPM_NUMWORDS ; 16 ;
; -- LPM_SHOWAHEAD ; OFF ;
; -- USE_EAB ; ON ;
+----------------------------+------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+----------------------------------------------------------------------+
; Name ; Value ;
+-------------------------------------------+----------------------------------------------------------------------+
; Number of entity instances ; 2 ;
; Entity Instance ; uart_top:uart_top|my_ram:my_ram_rec|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 256 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
; Entity Instance ; uart_top:uart_top|my_ram:my_ram_send|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; SINGLE_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 256 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+----------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_top:uart_top|contr_fifo_send_ram:contr_fifo_send_ram" ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; rdreq ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_top:uart_top|send:uartsend" ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; clkout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_top:uart_top|contr_fifo_rec_ram:contr_fifo_rec_ram" ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; data ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_top:uart_top|my_ram:my_ram_rec" ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; q ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "uart_top:uart_top|rec:uartrec" ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; clkout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Sun Apr 15 16:00:28 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_115 -c DE2_115
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file ram/ram_top_demo.v
Info (12023): Found entity 1: ram_top_demo
Info (12021): Found 1 design units, including 1 entities, in source file ram/ram_control_demo.v
Info (12023): Found entity 1: ram_control_demo
Info (12021): Found 1 design units, including 1 entities, in source file fifo/contr_fifo_send_ram.v
Info (12023): Found entity 1: contr_fifo_send_ram
Info (12021): Found 1 design units, including 1 entities, in source file main/uart_top_tf.v
Info (12023): Found entity 1: uart_top_tf
Info (12021): Found 1 design units, including 1 entities, in source file fifo/contr_fifo_rec_ram.v
Info (12023): Found entity 1: contr_fifo_rec_ram
Info (12021): Found 1 design units, including 1 entities, in source file ram/my_ram.v
Info (12023): Found entity 1: my_ram
Info (12021): Found 1 design units, including 1 entities, in source file fifo/my_fifo.v
Info (12023): Found entity 1: my_fifo
Info (12021): Found 1 design units, including 1 entities, in source file uart/send.v
Info (12023): Found entity 1: send
Info (12021): Found 1 design units, including 1 entities, in source file uart/rec.v
Info (12023): Found entity 1: rec
Info (12021): Found 1 design units, including 1 entities, in source file main/uart_top.v
Info (12023): Found entity 1: uart_top
Info (12021): Found 1 design units, including 1 entities, in source file main/de2_115.v
Info (12023): Found entity 1: DE2_115
Info (12127): Elaborating entity "DE2_115" for the top level hierarchy
Warning (10034): Output port "LEDG" at DE2_115.v(225) has no driver
Warning (10034): Output port "LEDR" at DE2_115.v(226) has no driver
Warning (10034): Output port "HEX0" at DE2_115.v(238) has no driver
Warning (10034): Output port "HEX1" at DE2_115.v(239) has no driver
Warning (10034): Output port "HEX2" at DE2_115.v(240) has no driver
Warning (10034): Output port "HEX3" at DE2_115.v(241) has no driver
Warning (10034): Output port "HEX4" at DE2_115.v(242) has no driver