-
Notifications
You must be signed in to change notification settings - Fork 0
/
DE2_115.flow.rpt
141 lines (120 loc) · 10.7 KB
/
DE2_115.flow.rpt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Flow report for DE2_115
Sun Apr 15 16:01:36 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sun Apr 15 16:01:36 2018 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; DE2_115 ;
; Top-level Entity Name ; DE2_115 ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Total logic elements ; 83 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 83 / 114,480 ( < 1 % ) ;
; Dedicated logic registers ; 57 / 114,480 ( < 1 % ) ;
; Total registers ; 57 ;
; Total pins ; 512 / 529 ( 97 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 2,048 / 3,981,312 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/15/2018 16:00:28 ;
; Main task ; Compilation ;
; Revision Name ; DE2_115 ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------+-----------------------------------------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+--------------------------------------+-----------------------------------------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 277807412944253.152377922862368 ; -- ; -- ; -- ;
; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; uart_top_tf ;
; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; ram_demo_tf ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ;
; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; uart_top_tf ; -- ; -- ; eda_simulation ;
; EDA_NETLIST_WRITER_OUTPUT_DIR ; C:/Users/user/Documents/Fpga/WORKPLACE/DE2_115_RS232FIFO14/simulation ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ;
; EDA_TEST_BENCH_FILE ; main/uart_top_tf.v ; -- ; -- ; uart_top_tf ;
; EDA_TEST_BENCH_FILE ; RAM/ram_demo_tf.v ; -- ; -- ; ram_demo_tf ;
; EDA_TEST_BENCH_MODULE_NAME ; uart_top_tf ; -- ; -- ; uart_top_tf ;
; EDA_TEST_BENCH_MODULE_NAME ; ram_demo_tf ; -- ; -- ; ram_demo_tf ;
; EDA_TEST_BENCH_NAME ; uart_top_tf ; -- ; -- ; eda_simulation ;
; EDA_TEST_BENCH_NAME ; ram_demo_tf ; -- ; -- ; eda_simulation ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+--------------------------------------+-----------------------------------------------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 559 MB ; 00:00:03 ;
; Fitter ; 00:00:36 ; 1.1 ; 1324 MB ; 00:00:26 ;
; Assembler ; 00:00:07 ; 1.0 ; 524 MB ; 00:00:06 ;
; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 625 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 463 MB ; 00:00:01 ;
; Total ; 00:00:53 ; -- ; -- ; 00:00:41 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-QMKN178 ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-QMKN178 ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-QMKN178 ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-QMKN178 ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-QMKN178 ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off DE2_115 -c DE2_115
quartus_fit --read_settings_files=off --write_settings_files=off DE2_115 -c DE2_115
quartus_asm --read_settings_files=off --write_settings_files=off DE2_115 -c DE2_115
quartus_sta DE2_115 -c DE2_115
quartus_eda --read_settings_files=off --write_settings_files=off DE2_115 -c DE2_115