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testlist_allactive.xml
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testlist_allactive.xml
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<?xml version="1.0"?>
<testlist version="2.0">
<test name="ERI" grid="f09_g16" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERI" grid="f09_g16" compset="B1850Ws" testmods="allactive/default">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERI" grid="f09_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERI" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERR" grid="f19_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="NCK" grid="f19_g16" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 02:00 </option>
</options>
</test>
<test name="ERS_D" grid="f09_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 04:00 </option>
</options>
</test>
<test name="ERS" grid="f19_g16" compset="B1850C4L45BGCRBPRPWs" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</machines>
</test>
<test name="ERS" grid="f09_g16" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prealpha"/>
<machine name="edison" compiler="cray" category="prealpha"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="ERS" grid="f19_g16" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<!-- <test name="ERS" grid="f09_g16" compset="BRCP45C4L40CNRBDRD" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="yellowstone" compiler="intel" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 01:00 </option> -->
<!-- </options> -->
<!-- </test> -->
<test name="ERS" grid="f09_g16" compset="BRCP85C5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld7" grid="ne30_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld7" grid="f09_g16" compset="BHIST" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld3" grid="f19_g16" compset="B1850Cw" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f09_g16" compset="B1850CwWs" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERS_Ld5" grid="T31_g37" compset="B1850C5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERS_Ld5" grid="f19_g16" compset="E1850C5L45TEST" testmods="cice/default">
<machines>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld7" grid="f19_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld7" grid="ne30_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prealpha"/>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<!-- <test name="ERS_Ld7" grid="f19_g16" compset="B1850C4RCO2L40CNRWs" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="bluewaters" compiler="pgi" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 00:20 </option> -->
<!-- </options> -->
<!-- </test> -->
<test name="ERS_Ld7" grid="f09_g16" compset="BHISTC5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_Ld9" grid="ne120_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="ERS_N3_Ld7" grid="f19_g16" compset="BHISTWs" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 02:00 </option>
</options>
</test>
<!-- <test name="ERS_N3_Ld7" grid="f19_g16" compset="BHISTC5L40CNR" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="edison" compiler="intel" category="prebeta"/> -->
<!-- <machine name="yellowstone" compiler="gnu" category="prealpha"/> -->
<!-- <machine name="yellowstone" compiler="gnu" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 00:20 </option> -->
<!-- </options> -->
<!-- </test> -->
<!-- <test name="ERS_Ld7" grid="f09_g16" compset="BRCP26C4L40CNR" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="janus" compiler="intel" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 00:20 </option> -->
<!-- </options> -->
<!-- </test> -->
<test name="ERS_Ld7" grid="f09_g16" compset="BRCP85C5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="NCK_Ld5" grid="f19_g16" compset="BC5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="NCK_Ld5" grid="f19_g16" compset="BC5L45BGCRG" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="PEA_P1" grid="f45_g37" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="hobart" compiler="intel" category="prebeta"/>
<machine name="hobart" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="PET" grid="f19_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="PET" grid="ne30_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<!-- <test name="PET" grid="f19_g16" compset="B1850C5L40SPRWs" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="bluewaters" compiler="pgi" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 00:20 </option> -->
<!-- </options> -->
<!-- </test> -->
<test name="PFS" grid="f09_g16" compset="B1850" testmods="allactive/default">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="PFS" grid="f09_g16" compset="B1850" testmods="allactive/default">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="PFS" grid="f09_g16" compset="B1850" testmods="allactive/maxthroughputb">
<machines>
<machine name="yellowstone" compiler="intel" category="aux_perf"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test compset="FW1850" grid="f09_f09" name="PFS" testmods="allactive/maxthroughputfw">
<machines>
<machine name="yellowstone" compiler="intel" category="aux_perf"/>
</machines>
</test>
<test name="PFS" grid="ne30_g16" compset="B1850" testmods="allactive/default">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="SMS_D" grid="f19_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="SMS_D" grid="f09_g16" compset="BHIST" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="SMS_Ld5" grid="T31_g37_gl20" compset="B1850C5L45BGCRG" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
<machine name="yellowstone" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="SMS_Ld5" grid="T31_g37_gl20" compset="B1850C5L45BGCRG1" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prebeta">
<options>
<option name="wallclock">0:20</option>
<option name="comment">Include a fully-coupled test with CISM1, mainly to make sure the PE layout works</option>
</options>
</machine>
</machines>
</test>
<test name="SMS_Ld5" grid="T31_g37_gl20" compset="BC5L45BGCRG" testmods="allactive/defaultio">
<machines>
<machine name="hobart" compiler="nag" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<!-- <test name="SMS_Ld5" grid="f09_g16" compset="BRCP85C4L40CNRBPRP" testmods="allactive/defaultio"> -->
<!-- <machines> -->
<!-- <machine name="edison" compiler="intel" category="prebeta"/> -->
<!-- </machines> -->
<!-- <options> -->
<!-- <option name="wallclock"> 00:20 </option> -->
<!-- </options> -->
<!-- </test> -->
<test name="SMS_Ld5" grid="f09_g16_gl4" compset="J1850G" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="SMS_Ld7" grid="f09_g16" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="yellowstone" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
<test name="PRE" grid="f19_f19" compset="ADESP_TEST">
<machines>
<machine name="hobart" compiler="nag" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:20 </option>
</options>
</test>
</testlist>