Interpreter's reset behavior does not match verilator backend.

[chick]

The interpreter lower reset at a different point in the clock cycle than the verilator backend.
Although we have not strictly specified what our reset behavior is, it would be nicer if the two
agreed. Most test harnesses are not broken by this though it is not that hard to write a test that will be sensitive to the difference.

[chick]

Note: The chisel ShiftResetTester test, when run with version of chisel that tests using the interpreter, seems to be exhibit this sensitivity

[seldridge]

I think there's a broader problem of the interpreter having x's in simulation. I got bit by this today due x-optimism. Both Treadle and the Verilator backends are doing the right thing and initializing everything.

(Note: I'm not really expecting a fix here, just that we should probably move everything off of using the FIRRTL interpreter by default as part of completely deprecating the interpreter.)