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info.yaml
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info.yaml
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# Tiny Tapeout project information
project:
title: "Ricoh 2A03" # Project title
author: "@fjpolo " # Your name
discord: "@fjpolo" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Ricoh 2A03 open-source silicon. This is a toy project towards FamiCom emulation." # One line description of what your project does
language: "Verilog" # Other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 16000000 # Clock frequency in Hz (or 0 if not applicable)
# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "4x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_fjpolo_r2a03" # Your top module name
# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
source_files:
- "R2A03/apu.v"
- "R2A03/dma.v"
- "R2A03/ppu.v"
- "R2A03/top.v"
- "R2A03/t65/T65_ALU.v"
- "R2A03/t65/T65_MCode.v"
- "R2A03/t65/T65_Pack.v"
- "R2A03/t65/T65.v"
- "tt_um_fjpolo_r2a03.v"
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: "/WAIT"
ui[1]: "/INT"
ui[2]: "/NMI"
ui[3]: "/BUSRQ"
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""
# Outputs
uo[0]: "/M1, A0, A8"
uo[1]: "/MREQ, A1, A9"
uo[2]: "/IORQ, A2, A10"
uo[3]: "/RD, A3, A11"
uo[4]: "/WR, A4, A12"
uo[5]: "/RFSH, A5, A13"
uo[6]: "/HALT, A6, A14"
uo[7]: "/BUSAK, A7, A15"
# Bidirectional pins
uio[0]: "D0"
uio[1]: "D1"
uio[2]: "D2"
uio[3]: "D3"
uio[4]: "D4"
uio[5]: "D5"
uio[6]: "D6"
uio[7]: "D7"
# Do not change!
yaml_version: 6