diff --git a/down-the-stack/README.md b/down-the-stack/README.md new file mode 100644 index 00000000..27c054bc --- /dev/null +++ b/down-the-stack/README.md @@ -0,0 +1,22 @@ +# Down the Stack + +This folder contains all relevant exercise templates, demo code and solutions for the exercises in the `Down the Stack` session. + +## `apps` package +* `button.rs` - demo code for the BSC exercise +* `hello.rs` - for testing as described in the BSC exercise +* `uarte_print.rs` - demo code for the BSC exercise +* `uarte_enable.rs` - exercise template for PAC exercise + +## `dk_bsc` package +* `lib.rs` - exercise template for the BSC exercise +* `lib_solution.rs` - solution code to the BSC exercise + +## `dk_pac` package +* `Cargo.toml` - a `Cargo.toml` file for the to be generated PAC +* `nrf52.svd` - an SVD file for generating the PAC + +You will generate the remaining files during the training + +## `solutions` package +* `uarte_enable.rs` - contains the solution for the PAC exercise \ No newline at end of file diff --git a/down-the-stack/apps/.cargo/config.toml b/down-the-stack/apps/.cargo/config.toml new file mode 100644 index 00000000..abfd4b6f --- /dev/null +++ b/down-the-stack/apps/.cargo/config.toml @@ -0,0 +1,19 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# (..) +rustflags = [ + "-C", "linker=flip-link", # adds stack overflow protection + "-C", "link-arg=-Tdefmt.x", # defmt support + # (..) +] + +[target.thumbv7em-none-eabihf] +# set custom cargo runner to flash & run on embedded target when we call `cargo run` +# for more information, check out https://github.com/knurling-rs/probe-run +runner = "probe-run --chip nRF52840_xxAA" +rustflags = [ + "-C", "link-arg=-Tlink.x", +] + +[build] +# cross-compile to this target +target = "thumbv7em-none-eabihf" # = ARM Cortex-M4 \ No newline at end of file diff --git a/down-the-stack/apps/Cargo.toml b/down-the-stack/apps/Cargo.toml new file mode 100644 index 00000000..7d3372e0 --- /dev/null +++ b/down-the-stack/apps/Cargo.toml @@ -0,0 +1,49 @@ +[package] +authors = ["Tanks Transfeld "] +edition = "2018" +license = "MIT OR Apache-2.0" +name = "apps" +version = "0.0.0" + +[dependencies] +cortex-m = {version = "0.7.6", features = ["critical-section-single-core"]} +cortex-m-rt = "0.7.2" +dk_bsc = { path = "../dk_bsc" } +heapless = "0.7.16" +panic-probe = { version = "0.3.0", features = ["print-defmt"] } +defmt = "0.3.2" +defmt-rtt = "0.3.2" + +# optimize code in both profiles +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # ! +incremental = false +lto = "fat" +opt-level = 'z' # ! +overflow-checks = false + +[profile.release] +codegen-units = 1 +debug = 1 +debug-assertions = false +incremental = false +lto = "fat" +opt-level = 3 +overflow-checks = false + +[features] + + +default = [ + "other-feature" +] +other-feature = [] +# do NOT modify these features +defmt-default = [] +defmt-trace = [] +defmt-debug = [] +defmt-info = [] +defmt-warn = [] +defmt-error = [] \ No newline at end of file diff --git a/down-the-stack/apps/src/bin/button.rs b/down-the-stack/apps/src/bin/button.rs new file mode 100644 index 00000000..3195c8dd --- /dev/null +++ b/down-the-stack/apps/src/bin/button.rs @@ -0,0 +1,31 @@ +#![no_main] +#![no_std] + + +use cortex_m_rt::entry; + +// this imports `down-the-stack/apps/lib.rs` to retrieve our global logger + panicking-behavior +use apps as _; + +// ⚠️ ⚠️ ⚠️ Don't change this file! ⚠️ ⚠️ ⚠️ + +#[entry] +fn main() -> ! { + // to enable more verbose logs, go to your `Cargo.toml` and set defmt logging levels + // to `defmt-trace` by changing the `default = []` entry in `[features]` + + let board = dk_bsc::init().unwrap(); + + let mut led = board.leds; + let button_1 = board.buttons.b_1; + + loop { + if button_1.is_pushed() { + led.led_1.on(); + } else { + led.led_1.off(); + } + } + + // this program does not `exit`; use Ctrl+C to terminate it +} diff --git a/down-the-stack/apps/src/bin/hello.rs b/down-the-stack/apps/src/bin/hello.rs new file mode 100644 index 00000000..9fc37f36 --- /dev/null +++ b/down-the-stack/apps/src/bin/hello.rs @@ -0,0 +1,28 @@ +// this program does not use the standard library to avoid heap allocations. +// only the `core` library functions are available. +#![no_std] +// this program uses a custom entry point instead of `fn main()` +#![no_main] + +use cortex_m::asm; +use cortex_m_rt::entry; +// this imports `beginner/apps/lib.rs` to retrieve our global logger + panicking-behavior +use apps as _; + +// the custom entry point +// vvvvv +#[entry] +fn main() -> ! { + // ˆˆˆ + // ! is the 'never' type: this function never returns + + // initializes the peripherals + dk_bsc::init().unwrap(); + + defmt::println!("Hello, world!"); // :wave: + + loop { + // breakpoint: halts the program's execution + asm::bkpt(); + } +} diff --git a/down-the-stack/apps/src/bin/uarte_enable.rs b/down-the-stack/apps/src/bin/uarte_enable.rs new file mode 100644 index 00000000..0f380e4f --- /dev/null +++ b/down-the-stack/apps/src/bin/uarte_enable.rs @@ -0,0 +1,28 @@ +#![no_main] +#![no_std] + +use cortex_m::asm; +use cortex_m_rt::entry; + +// ^^^^ import the PAC here + +// this imports `down-the-stack/apps/lib.rs` to retrieve our global logger + panicking-behavior +use apps as _; +use defmt; +use defmt_rtt as _; // global logger + +#[entry] +fn main() -> ! { + // to enable more verbose logs, go to your `Cargo.toml` and set defmt logging levels + // to `defmt-trace` by changing the `default = []` entry in `[features]` + + // Your code goes here... + + + // this program does not `exit`; use Ctrl+C to terminate it + loop { + asm::nop(); + } +} + +// The helper function goes here... diff --git a/down-the-stack/apps/src/bin/uarte_print.rs b/down-the-stack/apps/src/bin/uarte_print.rs new file mode 100644 index 00000000..2df9c961 --- /dev/null +++ b/down-the-stack/apps/src/bin/uarte_print.rs @@ -0,0 +1,28 @@ +#![no_main] +#![no_std] + +use cortex_m::asm; +use cortex_m_rt::entry; +use core::fmt::Write; + +// this imports `down-the-stack/apps/lib.rs` to retrieve our global logger + panicking-behavior +use apps as _; + +// ⚠️ ⚠️ ⚠️ Don't change this file! ⚠️ ⚠️ ⚠️ + +#[entry] +fn main() -> ! { + // to enable more verbose logs, go to your `Cargo.toml` and set defmt logging levels + // to `defmt-trace` by changing the `default = []` entry in `[features]` + + let board = dk_bsc::init().unwrap(); + let mut uarte = board.uarte; + + let tx_buffer = "Hello, World!\n"; + uarte.write_str(tx_buffer).unwrap(); + + // this program does not `exit`; use Ctrl+C to terminate it + loop { + asm::nop(); + } +} diff --git a/down-the-stack/apps/src/lib.rs b/down-the-stack/apps/src/lib.rs new file mode 100644 index 00000000..911961c4 --- /dev/null +++ b/down-the-stack/apps/src/lib.rs @@ -0,0 +1,10 @@ +#![no_std] +// ⚠️ ⚠️ ⚠️ Don't change this file! ⚠️ ⚠️ ⚠️ +use panic_probe as _; + +// same panicking *behavior* as `panic-probe` but doesn't print a panic message +// this prevents the panic message being printed *twice* when `defmt::panic` is invoked +#[defmt::panic_handler] +fn panic() -> ! { + cortex_m::asm::udf() +} diff --git a/down-the-stack/dk_bsc/Cargo.toml b/down-the-stack/dk_bsc/Cargo.toml new file mode 100644 index 00000000..b174f74a --- /dev/null +++ b/down-the-stack/dk_bsc/Cargo.toml @@ -0,0 +1,24 @@ +[package] +authors = ["Jorge Aparicio ", "Tanks Transfeld Result<(), Box> { + let out_dir = PathBuf::from(env::var("OUT_DIR")?); + + // put memory layout (linker script) in the linker search path + fs::copy("memory.x", out_dir.join("memory.x"))?; + + println!("cargo:rustc-link-search={}", out_dir.display()); + + Ok(()) +} diff --git a/down-the-stack/dk_bsc/memory.x b/down-the-stack/dk_bsc/memory.x new file mode 100644 index 00000000..fe811307 --- /dev/null +++ b/down-the-stack/dk_bsc/memory.x @@ -0,0 +1,5 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 1024K + RAM : ORIGIN = 0x20000000, LENGTH = 256K +} diff --git a/down-the-stack/dk_bsc/src/lib.rs b/down-the-stack/dk_bsc/src/lib.rs new file mode 100644 index 00000000..52630dad --- /dev/null +++ b/down-the-stack/dk_bsc/src/lib.rs @@ -0,0 +1,259 @@ +//! Board Support Crate (BSC) for the nRF52840 Development Kit + +#![deny(missing_docs)] +#![no_std] + +use core::{ + ops, + sync::atomic::{self, Ordering}, + time::Duration, +}; + +use cortex_m::asm; +use embedded_hal::digital::v2::{OutputPin as _, StatefulOutputPin}; + +use nrf52840_hal as hal; +use hal::{ + gpio::{p0, Level, Output, Pin, Port, PushPull}, + timer::OneShot, +}; + +use defmt; +use defmt_rtt as _; // global logger + +/// Components on the boarde +// Add structs for the peripheral you want to implement. First for the buttons, later UARTE +pub struct Board { + /// LEDs + pub leds: Leds, + + /// Timer + pub timer: Timer, + + +} + +/// All LEDs on the board +pub struct Leds { + /// LED1: pin P0.13, green LED + pub led_1: Led, + /// LED2: pin P0.14, green LED + pub led_2: Led, + /// LED3: pin P0.15, green LED + pub led_3: Led, + /// LED4: pin P0.16, green LED + pub led_4: Led, +} + +/// A single LED +pub struct Led { + inner: Pin>, +} + +impl Led { + /// Turns on the LED + pub fn on(&mut self) { + defmt::trace!( + "setting P{}.{} low (LED on)", + port_as_char(&self.inner.port()), + self.inner.pin() + ); + + // NOTE this operations returns a `Result` but never returns the `Err` variant + let _ = self.inner.set_low(); + } + + /// Turns off the LED + pub fn off(&mut self) { + defmt::trace!( + "setting P{}.{} high (LED off)", + port_as_char(&self.inner.port()), + self.inner.pin() + ); + + // NOTE this operations returns a `Result` but never returns the `Err` variant + let _ = self.inner.set_high(); + } + + /// Returns `true` if the LED is in the OFF state + pub fn is_off(&self) -> bool { + self.inner.is_set_high() == Ok(true) + } + + /// Returns `true` if the LED is in the ON state + pub fn is_on(&self) -> bool { + !self.is_off() + } + + /// Toggles the state (on/off) of the LED + pub fn toggle(&mut self) { + if self.is_off() { + self.on(); + } else { + self.off() + } + } +} + +/// All buttons on the board +// todo! Add a struct that represents all buttons of the board. +// ... + +/// A single button +// todo! Add a struct that represents a single button. +// ... + + +// Add an impl block for the Button struct +// todo! Add a method that returns true, if the button is pushed. +// ... + + + +/// A timer for creating blocking delays +pub struct Timer { + inner: hal::Timer, +} + + +impl Timer { + /// Blocks program execution for at least the specified `duration` + pub fn wait(&mut self, duration: Duration) { + defmt::trace!("blocking for {:?} ...", duration); + + // 1 cycle = 1 microsecond because the underlying HAL driver + // always sets the timer to 1 MHz. + const NANOS_IN_ONE_MICRO: u32 = 1_000; + let subsec_micros = duration.subsec_nanos() / NANOS_IN_ONE_MICRO; + if subsec_micros != 0 { + self.inner.delay(subsec_micros); + } + + const MICROS_IN_ONE_SEC: u32 = 1_000_000; + // maximum number of seconds that fit in a single `delay` call without overflowing the `u32` + // argument + const MAX_SECS: u32 = u32::MAX / MICROS_IN_ONE_SEC; + let mut secs = duration.as_secs(); + while secs != 0 { + let cycles = if secs > MAX_SECS as u64 { + secs -= MAX_SECS as u64; + MAX_SECS * MICROS_IN_ONE_SEC + } else { + let cycles = secs as u32 * MICROS_IN_ONE_SEC; + secs = 0; + cycles + }; + + self.inner.delay(cycles) + } + + defmt::trace!("... DONE"); + } +} + +impl ops::Deref for Timer { + type Target = hal::Timer; + + fn deref(&self) -> &Self::Target { + &self.inner + } +} + +impl ops::DerefMut for Timer { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.inner + } +} + +/// Uarte peripheral +// todo! Add a struct that represents the Uarte +// ... + + +// todo! Implement the fmt::Write Trait for Uarte +// ... + +/// Initializes the board +/// +/// This return an `Err`or if called more than once +pub fn init() -> Result { + if let Some(periph) = hal::pac::Peripherals::take() { + + let pins = p0::Parts::new(periph.P0); + + // NOTE LEDs turn on when the pin output level is low + let led_1 = pins.p0_13.degrade().into_push_pull_output(Level::High); + let led_2 = pins.p0_14.degrade().into_push_pull_output(Level::High); + let led_3 = pins.p0_15.degrade().into_push_pull_output(Level::High); + let led_4 = pins.p0_16.degrade().into_push_pull_output(Level::High); + + + // Buttons + // todo! Assign the pins of the buttons + // ... + + + + defmt::debug!("I/O pins have been configured for digital output"); + + let timer = hal::Timer::new(periph.TIMER0); + + + // Uarte + // todo! Assign the pins of the UARTE peripheral + // ... + + // todo! Instantiate the UARTE peripheral + // ... + + + + Ok(Board { + leds: Leds { + led_1: Led { inner: led_1 }, + led_2: Led { inner: led_2 }, + led_3: Led { inner: led_3 }, + led_4: Led { inner: led_4 }, + }, + + // todo! Create an instance of the struct that contains all the single buttons. + // ... + + timer: Timer { inner: timer }, + + // todo! Create an instance of the UARTE struct + // ... + }) + } else { + Err(()) + } +} + +/// Exits the application when the program is executed through the `probe-run` Cargo runner +pub fn exit() -> ! { + unsafe { + // turn off the USB D+ pull-up before pausing the device with a breakpoint + // this disconnects the nRF device from the USB host so the USB host won't attempt further + // USB communication (and see an unresponsive device). probe-run will also reset the nRF's + // USBD peripheral when it sees the device in a halted state which has the same effect as + // this line but that can take a while and the USB host may issue a power cycle of the USB + // port / hub / root in the meantime, which can bring down the probe and break probe-run + const USBD_USBPULLUP: *mut u32 = 0x4002_7504 as *mut u32; + USBD_USBPULLUP.write_volatile(0) + } + defmt::println!("`dk::exit()` called; exiting ..."); + // force any pending memory operation to complete before the BKPT instruction that follows + atomic::compiler_fence(Ordering::SeqCst); + loop { + asm::bkpt() + } +} + +// Helper functions + +fn port_as_char(port: &Port) -> char { + match port { + Port::Port0 => '0', + Port::Port1 => '1', + } +} diff --git a/down-the-stack/dk_bsc/src/lib_solution.rs b/down-the-stack/dk_bsc/src/lib_solution.rs new file mode 100644 index 00000000..a45db637 --- /dev/null +++ b/down-the-stack/dk_bsc/src/lib_solution.rs @@ -0,0 +1,303 @@ +//! Board Support Crate (BSC) for the nRF52840 Development Kit + +#![deny(missing_docs)] +#![no_std] + +use core::{ + ops, + fmt, + sync::atomic::{self, Ordering}, + time::Duration, +}; + +use cortex_m::asm; +use embedded_hal::digital::v2::{OutputPin as _, StatefulOutputPin}; +use nrf52840_hal as hal; +pub use hal::pac::uarte0::{ + baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity}; + + +use hal::{ +gpio::{p0, Level, Output, Input, PullUp, Pin, Port, PushPull}, +timer::OneShot, prelude::InputPin, +uarte, +}; + +use defmt; +use defmt_rtt as _; // global logger + +/// Components on the board +pub struct Board { + /// LEDs + pub leds: Leds, + // 🔽 --- Button Exercise --- 🔽 + /// Buttons + pub buttons: Buttons, + // 🔼 --- Button Exercise --- 🔼 + /// Timer + pub timer: Timer, + // 🔽 --- UARTE Exercise --- 🔽 + /// uarte interface + pub uarte: Uarte, + // 🔼 --- UARTE Exercise --- 🔼 +} + +/// All LEDs on the board +pub struct Leds { + /// LED1: pin P0.13, green LED + pub led_1: Led, + /// LED2: pin P0.14, green LED + pub led_2: Led, + /// LED3: pin P0.15, green LED + pub led_3: Led, + /// LED4: pin P0.16, green LED + pub led_4: Led, +} + +/// A single LED +pub struct Led { + inner: Pin>, +} + +impl Led { + /// Turns on the LED + pub fn on(&mut self) { + defmt::trace!( + "setting P{}.{} low (LED on)", + port_as_char(&self.inner.port()), + self.inner.pin() + ); + + // NOTE this operations returns a `Result` but never returns the `Err` variant + let _ = self.inner.set_low(); + } + + /// Turns off the LED + pub fn off(&mut self) { + defmt::trace!( + "setting P{}.{} high (LED off)", + port_as_char(&self.inner.port()), + self.inner.pin() + ); + + // NOTE this operations returns a `Result` but never returns the `Err` variant + let _ = self.inner.set_high(); + } + + /// Returns `true` if the LED is in the OFF state + pub fn is_off(&self) -> bool { + self.inner.is_set_high() == Ok(true) + } + + /// Returns `true` if the LED is in the ON state + pub fn is_on(&self) -> bool { + !self.is_off() + } + + /// Toggles the state (on/off) of the LED + pub fn toggle(&mut self) { + if self.is_off() { + self.on(); + } else { + self.off() + } + } +} +// 🔽 --- Button Exercise --- 🔽 +/// All buttons on the board +pub struct Buttons { + /// BUTTON1: pin P0.11 + pub b_1: Button, + /// BUTTON2: pin P0.12 + pub b_2: Button, + /// BUTTON3: pin P0.24 + pub b_3: Button, + /// BUTTON4: pin P0.25 + pub b_4: Button, +} + +/// A single button +pub struct Button { + inner: Pin>, +} + +impl Button { + /// returns true if button is pushed + pub fn is_pushed(&self) -> bool { + self.inner.is_low() == Ok(true) + } +} +// 🔼 --- Button Exercise --- 🔼 + +/// A timer for creating blocking delays +pub struct Timer { + inner: hal::Timer, +} + + +impl Timer { + /// Blocks program execution for at least the specified `duration` + pub fn wait(&mut self, duration: Duration) { + defmt::trace!("blocking for {:?} ...", duration); + + // 1 cycle = 1 microsecond because the underlying HAL driver + // always sets the timer to 1 MHz. + const NANOS_IN_ONE_MICRO: u32 = 1_000; + let subsec_micros = duration.subsec_nanos() / NANOS_IN_ONE_MICRO; + if subsec_micros != 0 { + self.inner.delay(subsec_micros); + } + + const MICROS_IN_ONE_SEC: u32 = 1_000_000; + // maximum number of seconds that fit in a single `delay` call without overflowing the `u32` + // argument + const MAX_SECS: u32 = u32::MAX / MICROS_IN_ONE_SEC; + let mut secs = duration.as_secs(); + while secs != 0 { + let cycles = if secs > MAX_SECS as u64 { + secs -= MAX_SECS as u64; + MAX_SECS * MICROS_IN_ONE_SEC + } else { + let cycles = secs as u32 * MICROS_IN_ONE_SEC; + secs = 0; + cycles + }; + + self.inner.delay(cycles) + } + + defmt::trace!("... DONE"); + } +} + +impl ops::Deref for Timer { + type Target = hal::Timer; + + fn deref(&self) -> &Self::Target { + &self.inner + } +} + +impl ops::DerefMut for Timer { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.inner + } +} + +// 🔽 --- UARTE Exercise --- 🔽 +/// Uarte peripheral +pub struct Uarte { + inner: hal::Uarte, +} + +impl fmt::Write for Uarte { + + fn write_str(&mut self, s: &str) -> fmt::Result { + // Copy all data into an on-stack buffer so we never try to EasyDMA from + // flash. + let mut buf: [u8; 16] = [0; 16]; + for block in s.as_bytes().chunks(16) { + buf[..block.len()].copy_from_slice(block); + self.inner.write(&buf[..block.len()]).map_err(|_| fmt::Error)?; + } + + Ok(()) + } +} +// 🔼 --- UARTE Exercise --- 🔼 + +/// Initializes the board +/// +/// This return an `Err`or if called more than once +pub fn init() -> Result { + if let Some(periph) = hal::pac::Peripherals::take() { + + let pins = p0::Parts::new(periph.P0); + + // NOTE LEDs turn on when the pin output level is low + let led_1 = pins.p0_13.degrade().into_push_pull_output(Level::High); + let led_2 = pins.p0_14.degrade().into_push_pull_output(Level::High); + let led_3 = pins.p0_15.degrade().into_push_pull_output(Level::High); + let led_4 = pins.p0_16.degrade().into_push_pull_output(Level::High); + + // 🔽 --- Button Exercise --- 🔽 + // Buttons + let b_1 = pins.p0_11.degrade().into_pullup_input(); + let b_2 = pins.p0_12.degrade().into_pullup_input(); + let b_3 = pins.p0_24.degrade().into_pullup_input(); + let b_4 = pins.p0_25.degrade().into_pullup_input(); + // 🔼 --- Button Exercise --- 🔼 + + defmt::debug!("I/O pins have been configured for digital output"); + + let timer = hal::Timer::new(periph.TIMER0); + + // 🔽 --- UARTE Exercise --- 🔽 + // Uarte + let pins = hal::uarte::Pins { + rxd: pins.p0_08.degrade().into_floating_input(), + txd: pins.p0_06.degrade().into_push_pull_output(Level::High), + cts: None, + rts: None, + }; + + + let uarte = hal::uarte::Uarte::new(periph.UARTE1, pins, Parity::EXCLUDED, Baudrate::BAUD115200); + // 🔼 --- UARTE Exercise --- 🔼 + + Ok(Board { + leds: Leds { + led_1: Led { inner: led_1 }, + led_2: Led { inner: led_2 }, + led_3: Led { inner: led_3 }, + led_4: Led { inner: led_4 }, + }, + + // 🔽 --- Button Exercise --- 🔽 + buttons: Buttons { + b_1: Button { inner: b_1}, + b_2: Button { inner: b_2}, + b_3: Button { inner: b_3}, + b_4: Button { inner: b_4}, + }, + // 🔼 --- Button Exercise --- 🔼 + + timer: Timer { inner: timer }, + + // 🔽 --- UARTE Exercise --- 🔽 + uarte: Uarte { inner: uarte }, + // 🔼 --- UARTE Exercise --- 🔼 + }) + } else { + Err(()) + } +} + +/// Exits the application when the program is executed through the `probe-run` Cargo runner +pub fn exit() -> ! { + unsafe { + // turn off the USB D+ pull-up before pausing the device with a breakpoint + // this disconnects the nRF device from the USB host so the USB host won't attempt further + // USB communication (and see an unresponsive device). probe-run will also reset the nRF's + // USBD peripheral when it sees the device in a halted state which has the same effect as + // this line but that can take a while and the USB host may issue a power cycle of the USB + // port / hub / root in the meantime, which can bring down the probe and break probe-run + const USBD_USBPULLUP: *mut u32 = 0x4002_7504 as *mut u32; + USBD_USBPULLUP.write_volatile(0) + } + defmt::println!("`dk::exit()` called; exiting ..."); + // force any pending memory operation to complete before the BKPT instruction that follows + atomic::compiler_fence(Ordering::SeqCst); + loop { + asm::bkpt() + } +} + +// Helper functions + +fn port_as_char(port: &Port) -> char { + match port { + Port::Port0 => '0', + Port::Port1 => '1', + } +} diff --git a/down-the-stack/dk_pac/Cargo.toml b/down-the-stack/dk_pac/Cargo.toml new file mode 100644 index 00000000..ff30c089 --- /dev/null +++ b/down-the-stack/dk_pac/Cargo.toml @@ -0,0 +1,22 @@ +[package] +authors = ["Tanks Transfeld + + + Nordic Semiconductor + Nordic + nrf52 + nrf52 + 1 + nRF52 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2022, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 1 + 3 + 0 + + system_nrf52 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory Information Configuration Registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0xFFFFFFFF + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0xFFFFFFFF + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption Root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity Root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-write + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052832 + + + PART + Part code + 0 + 31 + + + N52832 + nRF52832 + 0x52832 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x004 + read-only + 0x41414142 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAAC + AAAC + 0x41414143 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AAB0 + AAB0 + 0x41414230 + + + ABB0 + ABB0 + 0x41424230 + + + AAE0 + AAE0 + 0x41414530 + + + ABE0 + ABE0 + 0x41424530 + + + AAGB + AAGB + 0x41414742 + + + ABGB + ABGB + 0x41424742 + + + AAG0 + AAG0 + 0x41414730 + + + ABG0 + ABG0 + 0x41424730 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0x00002000 + + + PACKAGE + Package option + 0 + 31 + + + QF + QFxx - 48-pin QFN + 0x2000 + + + CH + CHxx - 7x8 WLCSP 56 balls + 0x2001 + + + CI + CIxx - 7x8 WLCSP 56 balls + 0x2002 + + + CK + CKxx - 7x8 WLCSP 56 balls with backside coating for light protection + 0x2005 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0x00000040 + + + RAM + RAM variant + 0 + 31 + + + K16 + 16 kByte RAM + 0x10 + + + K32 + 32 kByte RAM + 0x20 + + + K64 + 64 kByte RAM + 0x40 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0x00000200 + + + FLASH + Flash variant + 0 + 31 + + + K128 + 128 kByte FLASH + 0x80 + + + K256 + 256 kByte FLASH + 0x100 + + + K512 + 512 kByte FLASH + 0x200 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-write + 0x404 + + A0 + Slope definition A0. + 0x000 + read-only + 0x00000320 + + + A + A (slope definition) register. + 0 + 11 + + + + + A1 + Slope definition A1. + 0x004 + read-only + 0x00000343 + + + A + A (slope definition) register. + 0 + 11 + + + + + A2 + Slope definition A2. + 0x008 + read-only + 0x0000035D + + + A + A (slope definition) register. + 0 + 11 + + + + + A3 + Slope definition A3. + 0x00C + read-only + 0x00000400 + + + A + A (slope definition) register. + 0 + 11 + + + + + A4 + Slope definition A4. + 0x010 + read-only + 0x00000452 + + + A + A (slope definition) register. + 0 + 11 + + + + + A5 + Slope definition A5. + 0x014 + read-only + 0x0000037B + + + A + A (slope definition) register. + 0 + 11 + + + + + B0 + y-intercept B0. + 0x018 + read-only + 0x00003FCC + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + y-intercept B1. + 0x01C + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + y-intercept B2. + 0x020 + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + y-intercept B3. + 0x024 + read-only + 0x00000012 + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + y-intercept B4. + 0x028 + read-only + 0x0000004D + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + y-intercept B5. + 0x02C + read-only + 0x00003E10 + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0. + 0x030 + read-only + 0x000000E2 + + + T + T (segment end)register. + 0 + 7 + + + + + T1 + Segment end T1. + 0x034 + read-only + 0x00000000 + + + T + T (segment end)register. + 0 + 7 + + + + + T2 + Segment end T2. + 0x038 + read-only + 0x00000014 + + + T + T (segment end)register. + 0 + 7 + + + + + T3 + Segment end T3. + 0x03C + read-only + 0x00000019 + + + T + T (segment end)register. + 0 + 7 + + + + + T4 + Segment end T4. + 0x040 + read-only + 0x00000050 + + + T + T (segment end)register. + 0 + 7 + + + + + + NFC + Unspecified + FICR_NFC + read-write + 0x450 + + TAGHEADER0 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x000 + read-only + 0xFFFFFF5F + + + MFGID + Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F + 0 + 7 + + + UD1 + Unique identifier byte 1 + 8 + 15 + + + UD2 + Unique identifier byte 2 + 16 + 23 + + + UD3 + Unique identifier byte 3 + 24 + 31 + + + + + TAGHEADER1 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x004 + read-only + 0xFFFFFFFF + + + UD4 + Unique identifier byte 4 + 0 + 7 + + + UD5 + Unique identifier byte 5 + 8 + 15 + + + UD6 + Unique identifier byte 6 + 16 + 23 + + + UD7 + Unique identifier byte 7 + 24 + 31 + + + + + TAGHEADER2 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x008 + read-only + 0xFFFFFFFF + + + UD8 + Unique identifier byte 8 + 0 + 7 + + + UD9 + Unique identifier byte 9 + 8 + 15 + + + UD10 + Unique identifier byte 10 + 16 + 23 + + + UD11 + Unique identifier byte 11 + 24 + 31 + + + + + TAGHEADER3 + Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + 0x00C + read-only + 0xFFFFFFFF + + + UD12 + Unique identifier byte 12 + 0 + 7 + + + UD13 + Unique identifier byte 13 + 8 + 15 + + + UD14 + Unique identifier byte 14 + 16 + 23 + + + UD15 + Unique identifier byte 15 + 24 + 31 + + + + + + + + UICR + User Information Configuration Registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xF + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO number P0.n onto which Reset is exposed + 0 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware + 0xFF + + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + + + Enabled + Enable + 0x00 + + + + + + + NFCPINS + Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + 0x20C + read-write + 0xFFFFFFFF + + + PROTECT + Setting of pins dedicated to NFC functionality + 0 + 0 + + + Disabled + Operation as GPIO pins. Same protection as normal GPIO pins. + 0 + + + NFC + Operation as NFC antenna pins. Configures the protection for NFC operation. + 1 + + + + + + + + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. This register can only be written once. + 0x550 + read-writeOnce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + + + BPROT + Block Protect + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + BPROT + 0x20 + + + CONFIG0 + Block protect configuration register 0 + 0x600 + read-write + + + REGION0 + Enable protection for region 0. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION1 + Enable protection for region 1. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION2 + Enable protection for region 2. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION3 + Enable protection for region 3. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION4 + Enable protection for region 4. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION5 + Enable protection for region 5. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION6 + Enable protection for region 6. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION7 + Enable protection for region 7. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION8 + Enable protection for region 8. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION9 + Enable protection for region 9. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION10 + Enable protection for region 10. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION11 + Enable protection for region 11. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION12 + Enable protection for region 12. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION13 + Enable protection for region 13. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION14 + Enable protection for region 14. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION15 + Enable protection for region 15. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION16 + Enable protection for region 16. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION17 + Enable protection for region 17. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION18 + Enable protection for region 18. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION19 + Enable protection for region 19. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION20 + Enable protection for region 20. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION21 + Enable protection for region 21. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION22 + Enable protection for region 22. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION23 + Enable protection for region 23. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION24 + Enable protection for region 24. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION25 + Enable protection for region 25. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION26 + Enable protection for region 26. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION27 + Enable protection for region 27. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION28 + Enable protection for region 28. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION29 + Enable protection for region 29. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION30 + Enable protection for region 30. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + REGION31 + Enable protection for region 31. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enable + 1 + + + + + + + CONFIG1 + Block protect configuration register 1 + 0x604 + read-write + + + REGION32 + Enable protection for region 32. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION33 + Enable protection for region 33. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION34 + Enable protection for region 34. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION35 + Enable protection for region 35. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION36 + Enable protection for region 36. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION37 + Enable protection for region 37. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION38 + Enable protection for region 38. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION39 + Enable protection for region 39. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION40 + Enable protection for region 40. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION41 + Enable protection for region 41. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION42 + Enable protection for region 42. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION43 + Enable protection for region 43. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION44 + Enable protection for region 44. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION45 + Enable protection for region 45. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION46 + Enable protection for region 46. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION47 + Enable protection for region 47. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION48 + Enable protection for region 48. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION49 + Enable protection for region 49. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION50 + Enable protection for region 50. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION51 + Enable protection for region 51. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION52 + Enable protection for region 52. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION53 + Enable protection for region 53. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION54 + Enable protection for region 54. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION55 + Enable protection for region 55. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION56 + Enable protection for region 56. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION57 + Enable protection for region 57. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION58 + Enable protection for region 58. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION59 + Enable protection for region 59. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION60 + Enable protection for region 60. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION61 + Enable protection for region 61. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION62 + Enable protection for region 62. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION63 + Enable protection for region 63. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + DISABLEINDEBUG + Disable protection mechanism in debug interface mode + 0x608 + read-write + 0x00000001 + + + DISABLEINDEBUG + Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. + 0 + 0 + + + Disabled + Disable in debug + 1 + + + Enabled + Enable in debug + 0 + + + + + + + CONFIG2 + Block protect configuration register 2 + 0x610 + read-write + + + REGION64 + Enable protection for region 64. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION65 + Enable protection for region 65. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION66 + Enable protection for region 66. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION67 + Enable protection for region 67. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION68 + Enable protection for region 68. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION69 + Enable protection for region 69. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION70 + Enable protection for region 70. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION71 + Enable protection for region 71. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION72 + Enable protection for region 72. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION73 + Enable protection for region 73. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION74 + Enable protection for region 74. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION75 + Enable protection for region 75. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION76 + Enable protection for region 76. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION77 + Enable protection for region 77. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION78 + Enable protection for region 78. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION79 + Enable protection for region 79. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION80 + Enable protection for region 80. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION81 + Enable protection for region 81. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION82 + Enable protection for region 82. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION83 + Enable protection for region 83. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION84 + Enable protection for region 84. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION85 + Enable protection for region 85. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION86 + Enable protection for region 86. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION87 + Enable protection for region 87. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION88 + Enable protection for region 88. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION89 + Enable protection for region 89. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION90 + Enable protection for region 90. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION91 + Enable protection for region 91. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION92 + Enable protection for region 92. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION93 + Enable protection for region 93. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION94 + Enable protection for region 94. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION95 + Enable protection for region 95. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + CONFIG3 + Block protect configuration register 3 + 0x614 + read-write + + + REGION96 + Enable protection for region 96. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION97 + Enable protection for region 97. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION98 + Enable protection for region 98. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION99 + Enable protection for region 99. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION100 + Enable protection for region 100. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION101 + Enable protection for region 101. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION102 + Enable protection for region 102. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION103 + Enable protection for region 103. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION104 + Enable protection for region 104. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION105 + Enable protection for region 105. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION106 + Enable protection for region 106. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION107 + Enable protection for region 107. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION108 + Enable protection for region 108. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION109 + Enable protection for region 109. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION110 + Enable protection for region 110. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION111 + Enable protection for region 111. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION112 + Enable protection for region 112. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION113 + Enable protection for region 113. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION114 + Enable protection for region 114. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION115 + Enable protection for region 115. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION116 + Enable protection for region 116. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION117 + Enable protection for region 117. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION118 + Enable protection for region 118. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION119 + Enable protection for region 119. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION120 + Enable protection for region 120. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION121 + Enable protection for region 121. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION122 + Enable protection for region 122. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION123 + Enable protection for region 123. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION124 + Enable protection for region 124. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION125 + Enable protection for region 125. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION126 + Enable protection for region 126. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION127 + Enable protection for region 127. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + + + CLOCK + Clock control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + TRACECONFIG + Clocking options for the Trace Port debug interface + 0x55C + read-write + 0x00000000 + + + TRACEPORTSPEED + Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. + 0 + 1 + + + 32MHz + 32 MHz Trace Port clock (TRACECLK = 16 MHz) + 0 + + + 16MHz + 16 MHz Trace Port clock (TRACECLK = 8 MHz) + 1 + + + 8MHz + 8 MHz Trace Port clock (TRACECLK = 4 MHz) + 2 + + + 4MHz + 4 MHz Trace Port clock (TRACECLK = 2 MHz) + 3 + + + + + TRACEMUX + Pin multiplexing of trace signals. + 16 + 17 + + + GPIO + GPIOs multiplexed onto all trace-pins + 0 + + + Serial + SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins + 1 + + + Parallel + TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. + 2 + + + + + + + + + POWER + Power control + 0x40000000 + APPROTECT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable constant latency mode + 0x78 + write-only + + + TASKS_CONSTLAT + Enable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x7C + write-only + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LPCOMP + Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP + 17 + 17 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + NFC + Reset due to wake up from System OFF mode by NFC field detect + 19 + 19 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + RAMSTATUS + Deprecated register - RAM status register + 0x428 + read-only + 0x00000000 + + + RAMBLOCK0 + RAM block 0 is on or off/powering up + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK1 + RAM block 1 is on or off/powering up + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK2 + RAM block 2 is on or off/powering up + 2 + 2 + + + Off + Off + 0 + + + On + On + 1 + + + + + RAMBLOCK3 + RAM block 3 is on or off/powering up + 3 + 3 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power failure comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power failure comparator threshold setting + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + RAMON + Deprecated register - RAM on/off register (this register is retained) + 0x524 + read-write + 0x00000003 + + + ONRAM0 + Keep RAM block 0 on or off in system ON Mode + 0 + 0 + + + RAM0Off + Off + 0 + + + RAM0On + On + 1 + + + + + ONRAM1 + Keep RAM block 1 on or off in system ON Mode + 1 + 1 + + + RAM1Off + Off + 0 + + + RAM1On + On + 1 + + + + + OFFRAM0 + Keep retention on RAM block 0 when RAM block is switched off + 16 + 16 + + + RAM0Off + Off + 0 + + + RAM0On + On + 1 + + + + + OFFRAM1 + Keep retention on RAM block 1 when RAM block is switched off + 17 + 17 + + + RAM1Off + Off + 0 + + + RAM1On + On + 1 + + + + + + + RAMONB + Deprecated register - RAM on/off register (this register is retained) + 0x554 + read-write + 0x00000003 + + + ONRAM2 + Keep RAM block 2 on or off in system ON Mode + 0 + 0 + + + RAM2Off + Off + 0 + + + RAM2On + On + 1 + + + + + ONRAM3 + Keep RAM block 3 on or off in system ON Mode + 1 + 1 + + + RAM3Off + Off + 0 + + + RAM3On + On + 1 + + + + + OFFRAM2 + Keep retention on RAM block 2 when RAM block is switched off + 16 + 16 + + + RAM2Off + Off + 0 + + + RAM2On + On + 1 + + + + + OFFRAM3 + Keep retention on RAM block 3 when RAM block is switched off + 17 + 17 + + + RAM3Off + Off + 0 + + + RAM3On + On + 1 + + + + + + + DCDCEN + DC/DC enable register + 0x578 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + 8 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 ON or OFF in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 ON or OFF in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is in OFF + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is in OFF + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port 1 + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behaviour + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + RADIO + 2.4 GHz Radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength. + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete. + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value. + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power. + 0 + 7 + + + Pos4dBm + +4 dBm + 0x04 + + + Pos3dBm + +3 dBm + 0x03 + + + 0dBm + 0 dBm + 0x00 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xFF + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Nrf_250Kbit + Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode + 2 + + + Ble_1Mbit + 1 Mbit/s Bluetooth Low Energy + 3 + + + Ble_2Mbit + 2 Mbit/s Bluetooth Low Energy + 4 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 24 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least Significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 8 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Inter Frame Spacing in us + 0x544 + read-write + + + TIFS + Inter Frame Spacing in us + 0 + 7 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSELRTS + Pin select for RTS + 0x508 + read-write + 0xFFFFFFFF + + + PSELRTS + Pin number configuration for UART RTS signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELTXD + Pin select for TXD + 0x50C + read-write + 0xFFFFFFFF + + + PSELTXD + Pin number configuration for UART TXD signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELCTS + Pin select for CTS + 0x510 + read-write + 0xFFFFFFFF + + + PSELCTS + Pin number configuration for UART CTS signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELRXD + Pin select for RXD + 0x514 + read-write + 0xFFFFFFFF + + + PSELRXD + Pin number configuration for UART RXD signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + RXD + RXD register + 0x518 + read-only + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + + + + + UARTE0 + UART with EasyDMA + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PSELSCK + Pin number configuration for SPI SCK signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + MOSI + Pin select for MOSI + 0x004 + read-write + 0xFFFFFFFF + + + PSELMOSI + Pin number configuration for SPI MOSI signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + MISO + Pin select for MISO + 0x008 + read-write + 0xFFFFFFFF + + + PSELMISO + Pin number configuration for SPI MISO signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + + RXD + RXD register + 0x518 + read-only + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered + 0 + 7 + + + + + FREQUENCY + SPI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 7 + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 7 + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSELSCL + Pin select for SCL + 0x508 + read-write + 0xFFFFFFFF + + + PSELSCL + Pin number configuration for TWI SCL signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + PSELSDA + Pin select for SDA + 0x50C + read-write + 0xFFFFFFFF + + + PSELSDA + Pin number configuration for TWI SDA signal + 0 + 31 + + + Disconnected + Disconnect + 0xFFFFFFFF + + + + + + + RXD + RXD register + 0x518 + read-only + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 7 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Which of the addresses in {ADDRESS} matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 7 + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 7 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 7 + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + NFCT + NFC-A compatible radio + 0x40005000 + + 0 + 0x1000 + registers + + + NFCT + 5 + + NFCT + 0x20 + + + TASKS_ACTIVATE + Activate NFC peripheral for incoming and outgoing frames, change state to activated + 0x000 + write-only + + + TASKS_ACTIVATE + Activate NFC peripheral for incoming and outgoing frames, change state to activated + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable NFC peripheral + 0x004 + write-only + + + TASKS_DISABLE + Disable NFC peripheral + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0x008 + write-only + + + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start transmission of a outgoing frame, change state to transmit + 0x00C + write-only + + + TASKS_STARTTX + Start transmission of a outgoing frame, change state to transmit + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C + write-only + + + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only + + + TASKS_GOIDLE + Force state machine to IDLE state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only + + + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + The NFC peripheral is ready to receive and send frames + 0x100 + read-write + + + EVENTS_READY + The NFC peripheral is ready to receive and send frames + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 + read-write + + + EVENTS_FIELDDETECTED + Remote NFC field detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 + read-write + + + EVENTS_FIELDLOST + Remote NFC field lost + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC Auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC Auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC Auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC Auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear + + + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX + 0 + 0 + + + NFCFIELDTOOSTRONG + Field level is too high at max load resistance + 2 + 2 + + + NFCFIELDTOOWEAK + Field level is too low at min load resistance + 3 + 3 + + + + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS + read-write + 0x40C + + RX + Result of last incoming frames + 0x000 + read-write + oneToClear + + + CRCERROR + No valid End of Frame detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + + + CURRENTLOADCTRL + Current value driven to the NFC Load Control + 0x430 + read-only + 0x00000000 + + + CURRENTLOADCTRL + Current value driven to the NFC Load Control + 0 + 5 + + + + + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only + + + FIELDPRESENT + Indicates the presence or not of a valid field. Available only in the activated state. + 0 + 0 + + + NoField + No valid field detected + 0 + + + FieldPresent + Valid field detected + 1 + + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + + + NotLocked + Not locked to field + 0 + + + Locked + Locked to field + 1 + + + + + + + FRAMEDELAYMIN + Minimum frame delay + 0x504 + read-write + 0x00000480 + + + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + + + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 15 + + + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C + read-write + 0x00000001 + + + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0 + 1 + + + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + 0 + + + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + 1 + + + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX + 2 + + + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 + + + + + + + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 + read-write + 0x00000000 + + + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. + 0 + 31 + + + + + MAXLEN + Size of allocated for TXD and RXD data storage buffer in Data RAM + 0x514 + read-write + + + MAXLEN + Size of allocated for TXD and RXD data storage buffer in Data RAM + 0 + 8 + + + + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Adding parity or not in the frame + 0 + 0 + + + NoParity + Parity is not added in TX frames + 0 + + + Parity + Parity is added TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits in start or at end of a Frame + 1 + 1 + + + DiscardEnd + Unused bits is discarded at end of frame + 0 + + + DiscardStart + Unused bits is discarded at start of frame + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + Start of Frame symbol not added + 0 + + + SoF + Start of Frame symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Parity expected or not in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + Start of Frame symbol is not expected in RX frames + 0 + + + SoF + Start of Frame symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + + + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 + + + NFCID1_Z + NFCID1 byte Z (very last byte sent) + 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 + + + + + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write + + + NFCID1_V + NFCID1 byte V + 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 + + + + + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 + read-write + + + NFCID1_S + NFCID1 byte S + 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 + + + + + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 + read-write + 0x00000001 + + + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the Auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade bit (controlled by hardware, write has no effect) + 2 + 2 + + + Complete + NFCID1 complete + 0 + + + NotComplete + NFCID1 not complete + 1 + + + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Analog to Digital Converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000320 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000343 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x0000035D + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000400 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000047F + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x0000037B + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00003FCC + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003F98 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003F98 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x0000006A + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x00003DD0 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000014 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x00000019 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + CCM error event + 0x108 + read-write + + + EVENTS_ERROR + CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Data rate that the CCM shall run in synch with + 16 + 16 + + + 1Mbit + In synch with 1 Mbit data rate + 0 + + + 2Mbit + In synch with 2 Mbit data rate + 1 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field is 5-bit + 0 + + + Extended + Extended length. Effective length of LENGTH field is 8-bit + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 + + + 10Smpl + 10 samples / report + 0 + + + 40Smpl + 40 samples / report + 1 + + + 80Smpl + 80 samples / report + 2 + + + 120Smpl + 120 samples / report + 3 + + + 160Smpl + 160 samples / report + 4 + + + 200Smpl + 200 samples / report + 5 + + + 240Smpl + 240 samples / report + 6 + + + 280Smpl + 280 samples / report + 7 + + + 1Smpl + 1 sample / report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 7 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + + + ISOURCE + Comparator hysteresis + 0 + 1 + + + Off + Current source disabled + 0 + + + Ien2mA5 + Current source enabled (+/- 2.5 uA) + 1 + + + Ien5mA + Current source enabled (+/- 5 uA) + 2 + + + Ien10mA + Current source enabled (+/- 10 uA) + 3 + + + + + + + + + LPCOMP + Low Power Comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-). + 0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-). + 1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 0 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0 + + + Up + Generate ANADETECT on upward crossing only + 1 + + + Down + Generate ANADETECT on downward crossing only + 2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis enable + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis disabled (typ. 50 mV) + 1 + + + + + + + + + EGU0 + Event Generator Unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event Generator Unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + EGU2 + Event Generator Unit 2 + 0x40016000 + + SWI2_EGU2 + 22 + + + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 + + SWI2_EGU2 + 22 + + + + EGU3 + Event Generator Unit 3 + 0x40017000 + + SWI3_EGU3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + SWI3_EGU3 + 23 + + + + EGU4 + Event Generator Unit 4 + 0x40018000 + + SWI4_EGU4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + SWI4_EGU4 + 24 + + + + EGU5 + Event Generator Unit 5 + 0x40019000 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 + + + + PWM0 + Pulse Width Modulation Unit 0 + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up or up and down as wave counter mode + 0 + 0 + + + Up + Up counter - edge aligned PWM duty-cycle + 0 + + + UpAndDown + Up and down counter - center aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Pre-scaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16MHz) + 0 + + + DIV_2 + Divide by 2 ( 8MHz) + 1 + + + DIV_4 + Divide by 4 ( 4MHz) + 2 + + + DIV_8 + Divide by 8 ( 2MHz) + 3 + + + DIV_16 + Divide by 16 ( 1MHz) + 4 + + + DIV_32 + Divide by 32 ( 500kHz) + 5 + + + DIV_64 + Divide by 64 ( 250kHz) + 6 + + + DIV_128 + Divide by 128 ( 125kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Amount of playback of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Amount of playback of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in Data RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in Data RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Amount of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Amount of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Amount of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 7 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write Enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in Code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in Code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. + 0x510 + read-write + + + ERASEPCR0 + Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEUICR + Register for erasing User Information Configuration Registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ICACHECNF + I-Code cache configuration register. + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-Code cache hit counter. + 0x548 + read-write + + + HITS + Number of cache hits + 0 + 31 + + + + + IMISS + I-Code cache miss counter. + 0x54C + read-write + + + MISSES + Number of cache misses + 0 + 31 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + MWU + Memory Watch Unit + 0x40020000 + + 0 + 0x1000 + registers + + + MWU + 32 + + MWU + 0x20 + + + 4 + 0x008 + EVENTS_REGION[%s] + Peripheral events. + MWU_EVENTS_REGION + read-write + 0x100 + + WA + Description cluster: Write access to region n detected + 0x000 + read-write + + + WA + Write access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + RA + Description cluster: Read access to region n detected + 0x004 + read-write + + + RA + Read access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + 2 + 0x008 + EVENTS_PREGION[%s] + Peripheral events. + MWU_EVENTS_PREGION + read-write + 0x160 + + WA + Description cluster: Write access to peripheral region n detected + 0x000 + read-write + + + WA + Write access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + RA + Description cluster: Read access to peripheral region n detected + 0x004 + read-write + + + RA + Read access to peripheral region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + REGION0WA + Enable or disable interrupt for event REGION0WA + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable interrupt for event REGION0RA + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable interrupt for event REGION1WA + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable interrupt for event REGION1RA + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable interrupt for event REGION2WA + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable 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Write '1' to enable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt 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'1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + NMIEN + Enable or disable interrupt + 0x320 + read-write + + + REGION0WA + Enable or disable interrupt for event REGION0WA + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION0RA + Enable or disable interrupt for event REGION0RA + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1WA + Enable or disable interrupt for event REGION1WA + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION1RA + Enable or disable interrupt for event REGION1RA + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2WA + Enable or disable interrupt for event REGION2WA + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION2RA + Enable or disable interrupt for event REGION2RA + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3WA + Enable or disable interrupt for event REGION3WA + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + REGION3RA + Enable or disable interrupt for event REGION3RA + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + + + REGION0WA + Write '1' to enable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION0RA + Write '1' to enable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1WA + Write '1' to enable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION1RA + Write '1' to enable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2WA + Write '1' to enable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION2RA + Write '1' to enable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + + + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 2 + 0x008 + PERREGION[%s] + Unspecified + MWU_PERREGION + read-write + 0x400 + + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching + 0x000 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + + + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching + 0x004 + read-write + oneToClear + + + SR0 + Subregion 0 in region n (write '1' to clear) + 0 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 + 31 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + + + + REGIONEN + Enable/disable regions watch + 0x510 + read-write + + + RGN0WA + Enable/disable write access watch in region[0] + 0 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable/disable write access watch in region[1] + 2 + 2 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable/disable write access watch in region[3] + 6 + 6 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable/disable read access watch in region[3] + 7 + 7 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 + + + Disable + Disable write access watch in this PREGION + 0 + + + Enable + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENSET + Enable regions watch + 0x514 + read-write + + + RGN0WA + Enable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN1WA + Enable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN1RA + Enable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN2WA + Enable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN2RA + Enable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region + 1 + + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region + 1 + + + + + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + + + + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION + 1 + + + + + + + REGIONENCLR + Disable regions watch + 0x518 + read-write + + + RGN0WA + Disable write access watch in region[0] + 0 + 0 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN0RA + Disable read access watch in region[0] + 1 + 1 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN1WA + Disable write access watch in region[1] + 2 + 2 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN1RA + Disable read access watch in region[1] + 3 + 3 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN2WA + Disable write access watch in region[2] + 4 + 4 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN2RA + Disable read access watch in region[2] + 5 + 5 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + RGN3WA + Disable write access watch in region[3] + 6 + 6 + + read + + Disabled + Write access watch in this region is disabled + 0 + + + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region + 1 + + + + + RGN3RA + Disable read access watch in region[3] + 7 + 7 + + read + + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region + 1 + + + + + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION + 1 + + + + + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + + read + + Disabled + Read access watch in this PREGION is disabled + 0 + + + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION + 1 + + + + + + + 4 + 0x010 + REGION[%s] + Unspecified + MWU_REGION + read-write + 0x600 + + START + Description cluster: Start address for region n + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster: End address of region n + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 + + START + Description cluster: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster: Subregions of region n + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse Width Modulation Unit 1 + 0x40021000 + + PWM1 + 33 + + + + PWM2 + Pulse Width Modulation Unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + 0x40025000 + + 0 + 0x1000 + registers + + + I2S + 37 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. + 0x004 + write-only + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable I2S module. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + \ No newline at end of file diff --git a/down-the-stack/solutions/.cargo/config.toml b/down-the-stack/solutions/.cargo/config.toml new file mode 100644 index 00000000..abfd4b6f --- /dev/null +++ b/down-the-stack/solutions/.cargo/config.toml @@ -0,0 +1,19 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# (..) +rustflags = [ + "-C", "linker=flip-link", # adds stack overflow protection + "-C", "link-arg=-Tdefmt.x", # defmt support + # (..) +] + +[target.thumbv7em-none-eabihf] +# set custom cargo runner to flash & run on embedded target when we call `cargo run` +# for more information, check out https://github.com/knurling-rs/probe-run +runner = "probe-run --chip nRF52840_xxAA" +rustflags = [ + "-C", "link-arg=-Tlink.x", +] + +[build] +# cross-compile to this target +target = "thumbv7em-none-eabihf" # = ARM Cortex-M4 \ No newline at end of file diff --git a/down-the-stack/solutions/Cargo.toml b/down-the-stack/solutions/Cargo.toml new file mode 100644 index 00000000..b728c4e8 --- /dev/null +++ b/down-the-stack/solutions/Cargo.toml @@ -0,0 +1,50 @@ +[package] +authors = ["Tanks Transfeld "] +edition = "2018" +license = "MIT OR Apache-2.0" +name = "solutions" +version = "0.0.0" + +[dependencies] +cortex-m = {version = "0.7.6", features = ["critical-section-single-core"]} +cortex-m-rt = "0.7.2" +dk_bsc = { path = "../dk_bsc" } +dk_pac = { path = "../dk_pac", features = ["critical-section"]} +heapless = "0.7.16" +panic-probe = { version = "0.3.0", features = ["print-defmt"] } +defmt = "0.3.2" +defmt-rtt = "0.3.2" + +# optimize code in both profiles +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # ! +incremental = false +lto = "fat" +opt-level = 'z' # ! +overflow-checks = false + +[profile.release] +codegen-units = 1 +debug = 1 +debug-assertions = false +incremental = false +lto = "fat" +opt-level = 3 +overflow-checks = false + +[features] + + +default = [ + "other-feature" +] +other-feature = [] +# do NOT modify these features +defmt-default = [] +defmt-trace = [] +defmt-debug = [] +defmt-info = [] +defmt-warn = [] +defmt-error = [] \ No newline at end of file diff --git a/down-the-stack/solutions/README.md b/down-the-stack/solutions/README.md new file mode 100644 index 00000000..29980834 --- /dev/null +++ b/down-the-stack/solutions/README.md @@ -0,0 +1,4 @@ +# Solutions + +This program does not build if the pac is not generated! +The file is only for reference. \ No newline at end of file diff --git a/down-the-stack/solutions/src/bin/uarte_enable.rs b/down-the-stack/solutions/src/bin/uarte_enable.rs new file mode 100644 index 00000000..8e7fa084 --- /dev/null +++ b/down-the-stack/solutions/src/bin/uarte_enable.rs @@ -0,0 +1,48 @@ +#![no_main] +#![no_std] + +use cortex_m::asm; +use cortex_m_rt::entry; +use dk_pac::UARTE0; + +// this imports `down-the-stack/apps/lib.rs` to retrieve our global logger + panicking-behavior +use solutions as _; +use defmt; +use defmt_rtt as _; // global logger + +#[entry] +fn main() -> ! { + // to enable more verbose logs, go to your `Cargo.toml` and set defmt logging levels + // to `defmt-trace` by changing the `default = []` entry in `[features]` + + // takes ownership of the nRF52840-DK peripherals + let periph = dk_pac::Peripherals::take().unwrap(); + let uarte = periph.UARTE0; + + is_uarte_enabled(&uarte); + + // enable the UART0 peripheral the safe way + uarte.enable.write(|w| w.enable().enabled()); + + is_uarte_enabled(&uarte); + + // disable the UART0 peripheral by writing 0 directly into the register -- the unsafe way + unsafe { + uarte.enable.write(|w| w.bits(0x00u32)); + } + + is_uarte_enabled(&uarte); + + // this program does not `exit`; use Ctrl+C to terminate it + loop { + asm::nop(); + } +} + +fn is_uarte_enabled(uarte: &UARTE0) { + if uarte.enable.read().enable().is_enabled() { + defmt::println!("Uarte0 is enabled"); + } else { + defmt::println!("Uarte0 is disabled"); + } +} \ No newline at end of file diff --git a/down-the-stack/solutions/src/lib.rs b/down-the-stack/solutions/src/lib.rs new file mode 100644 index 00000000..83c2b234 --- /dev/null +++ b/down-the-stack/solutions/src/lib.rs @@ -0,0 +1,11 @@ +#![no_std] + +// ⚠️ ⚠️ ⚠️ Don't change this file! ⚠️ ⚠️ ⚠️ so it's exactly like apps/src/lib.rs +use panic_probe as _; + +// same panicking *behavior* as `panic-probe` but doesn't print a panic message +// this prevents the panic message being printed *twice* when `defmt::panic` is invoked +#[defmt::panic_handler] +fn panic() -> ! { + cortex_m::asm::udf() +} diff --git a/embedded-workshop-book/src/SUMMARY.md b/embedded-workshop-book/src/SUMMARY.md index 1e79ec49..6f34aa05 100644 --- a/embedded-workshop-book/src/SUMMARY.md +++ b/embedded-workshop-book/src/SUMMARY.md @@ -24,6 +24,14 @@ - [Collision avoidance](./collision-avoidance.md) - [Interrupt handling](./interrupt-handling.md) - [Starting a Project from Scratch](./from-scratch.md) +- [Down the Stack Workbook](./down-the-stack.md) + - [BSC Exercise](./bsc-exercise.md) + - [Button Implementation](./button-implementation.md) + - [UARTE Implementation](./uarte-implementation.md) + - [Generating and Using a PAC](./pac-exercise.md) + - [Exercise: Generating a PAC ](./generating-pac.md) + - [Reading PAC Documentation ](./pac-docs.md) + - [Exercise: Enabling the UARTE0 Peripheral ](./enabling-uarte.md) - [Advanced Workbook](./advanced-workbook.md) - [Code Organization](./code-organisation.md) - [Listing USB Devices](./listing-usb-devices.md) diff --git a/embedded-workshop-book/src/bsc-exercise.md b/embedded-workshop-book/src/bsc-exercise.md new file mode 100644 index 00000000..42c63c84 --- /dev/null +++ b/embedded-workshop-book/src/bsc-exercise.md @@ -0,0 +1,67 @@ +# BSC Exercise + +In this exercise you will learn how to write a *Board Support Crate* (or BSC, also known as a *Board Support Package*) by implementing support for handling button presses, and support for using the UARTE peripheral. + +The template `down-the-stack/dk_bsc/src/lib.rs` already contains the LED and Timer implementations. Add your code to the designated lines. You'll find a `//todo!` there. + +You can test after each step by running the following command out of `down-the-stack/apps` +``` +cargo run --bin hello +``` +This program will not call any of the functions you are implementing, so it does not matter if they are incomplete. It will refuse to build if there are errors present in the `lib.rs`! + +`down-the-stack/dk_bsc/src/lib_solution.rs` contains the full solution code. + +## You will learn how to +* modify the `init()` function that brings up the board's peripherals +* how to configure pins +* how to write a function that checks the state of a pin +* implement functionality on a type +* implement a Trait +* to document and generate docs for your own library! + +## Prerequisites +* installation of `pyserial` or other serial terminal that you are familiar with. +* `impl` keyword +* methods and associated functions +* `pub` keyword +* usage of structs to represent registers +* Trait + +## Tasks +### Write a button implementation. This entails the following steps: +* Add `struct Buttons` with 4 fields, that represents each of the four buttons. +* Add `struct Button` that is a wrapper for the pin that a single button is connected to. +* Write a method `is_pushed` that checks if a single button is pushed. +* Initialize the pins in `fn init()`. +* Add the `struct Button` to the definition and instantiation of `struct Board`. +* Run `apps/buttons.rs` to test. +* Run `cargo doc` out of the apps folder to find all your doc comments! +### Write a UARTE implementation. This entails the following steps: +* Check the `uarte` module of the `nrf-hal` for requirements of the instantiating method. +* Add `struct Uarte` that serves as wrapper for the `UARTE1` instance. +* Initialize the UARTE1 peripheral in `fn init()` using the following settings: + * parity: included + * baudrate: 115200 baud +* Add `struct Uarte` to the definition and instantiation of `struct Board`. +* Implement the `fmt::Write` trait for `struct Uarte`. +* Connect your computer to the virtual UART port with `screen`. +* Run `apps/uarte_print.rs` to test. +## Knowledge + +### Comments +The `lib.rs` has an attribute `#![deny(missing_docs)]`. This means, that missing doc comments for structs are returned as compiler errors, to remind you to document your work properly. + +```rust +/// This is a doc comment +// This is a normal comment +``` +### Structs represent Registers + +[todo!] insert refresher from rust fundamentals +## Hardware documentation for pin configuration + +Go to [Nordic Infocenter](https://infocenter.nordicsemi.com/topic/ug_nrf52840_dk/UG/dk/intro.html) to download the User Guide. You can find all the information that is relevant to this exercise in there. + + + diff --git a/embedded-workshop-book/src/button-implementation.md b/embedded-workshop-book/src/button-implementation.md new file mode 100644 index 00000000..8c0118be --- /dev/null +++ b/embedded-workshop-book/src/button-implementation.md @@ -0,0 +1,146 @@ +# Write the Button Implementation +## Step-by-Step Solution + +### Step 1: Read the docs! + +✅ Read the [User Guide section 8.7](https://infocenter.nordicsemi.com/topic/ug_nrf52840_dk/UG/dk/hw_buttons_leds.html?cp=5_0_4_7_6) for info about pins and pin configuration related to the buttons. Note down the pins that the buttons are connected to. + +The pins need to be configured as input pins with an internal pull-up. The pins as well as the configurations are defined as types in the `nrf-hal` in the `gpio` peripheral. Add the following imports: `Input` and `PullUp`. + +### Step 2: Add the structs that represent the buttons as a group and a generic single button. + +✅ Add the struct that represents the single button. It has only one field, `inner`. The type of this button is the pin configuration: `Pin>` + +✅ Add the `struct` that represents the group of buttons has four fields, one for each button. The field name contains the number that corresponds to the button numeration on the board. The type of each field is the struct that represents the generic single button. + +✅ Add doc comments for every struct and field! + +Building this code should return a warning: field `inner` is never read. + +
+ Solution + +```rust +/// All buttons on the board +pub struct Buttons { + /// BUTTON1: pin P0.11 + pub b_1: Button, + /// BUTTON2: pin P0.12 + pub b_2: Button, + /// BUTTON3: pin P0.24 + pub b_3: Button, + /// BUTTON4: pin P0.25 + pub b_4: Button, +} + +/// A single button +pub struct Button { + inner: Pin>, +} +``` +
+ +### Step 3: Implement the button function. + +✅ Add an `impl` block for the `struct Button`. Add a method `is_pushed` that takes in the struct as `&self` and returns a bool, if the button is pushed. + +✅ Now remember, the pins the buttons are connected to are configured as active low. For buttons this means, that the pin is pulled low, when the button is pushed. + +✅ In the `nrf-hal` you can find a method to check if a single pin is low. To use it, you have to add the following line to your `nrf52840_hal` imports: `prelude::InputPin`. + + +
+ Solution + +```rust +impl Button { + /// returns true if button is pushed + pub fn is_pushed(&self) -> bool { + self.inner.is_low() == Ok(true) + } +} +``` +
+ +### Step 4: Bring up the pins! + +✅ Go to `pub fn init()`, the function that initializes the board's peripherals. + +✅ Configure each pin as degraded, pull-up input pin and bind it to a variable that makes it clear what button number it is connected to. + +Building this code brings up warnings about unused variables. + +
+ Solution + +```rust +// Buttons +let b_1 = pins.p0_11.degrade().into_pullup_input(); +let b_2 = pins.p0_12.degrade().into_pullup_input(); +let b_3 = pins.p0_24.degrade().into_pullup_input(); +let b_4 = pins.p0_25.degrade().into_pullup_input(); +``` +
+ +### Step 5: Add everything to the board struct. + +✅ In the definition of the `struct Board` add a field for the `struct Buttons`. + +✅ In the pub `fn init()` function, where `Board` is instantiated, add the button field, assigning the pins you defined earlier to the respective buttons. + +
+ Solution + +```rust +/// Components on the board +pub struct Board { + /// LEDs + pub leds: Leds, + /// Buttons + pub buttons: Buttons, + /// Timer + pub timer: Timer, +} + +// ... + +pub fn init() -> Result { + // ... + Ok(Board { + leds: Leds { + // ... + }, + buttons: Buttons { + b_1: Button { inner: b_1}, + b_2: Button { inner: b_2}, + b_3: Button { inner: b_3}, + b_4: Button { inner: b_4}, + }, + timer: Timer { inner: timer }, + }) + } else { + Err(()) + } + +} + +``` +
+ +### Step 6: Run the example! + +✅ Go to `/down-the-stack/apps`. + +✅ Run the following command: + +```shell +cargo run --bin button +``` + +### Step 7: Generate the docs! + +✅ Out of the apps folder run the following command to build the docs for this crate and to view your written documentation! + +```shell +cargo doc +``` \ No newline at end of file diff --git a/embedded-workshop-book/src/down-the-stack.md b/embedded-workshop-book/src/down-the-stack.md new file mode 100644 index 00000000..88284e98 --- /dev/null +++ b/embedded-workshop-book/src/down-the-stack.md @@ -0,0 +1,10 @@ +# Down the Stack + +In this Session you will learn more about Rust's split crate model that includes +* the Board Support Crate +* an implementation of the Hardware Abstraction Layer +* the Peripheral Access Crate + +This session consists of lectures and two blocks of exercises: +* BSC Exercise: Implementing further features in a basic BSC +* PAC Exercise: Generating a PAC from an SVD file and writing into registers using the the generated PAC. \ No newline at end of file diff --git a/embedded-workshop-book/src/enabling-uarte.md b/embedded-workshop-book/src/enabling-uarte.md new file mode 100644 index 00000000..10eebb4f --- /dev/null +++ b/embedded-workshop-book/src/enabling-uarte.md @@ -0,0 +1,103 @@ +# Enabling the UARTE0 peripheral + +Write a simple program which uses the PAC to enable the UARTE0. See how writing arbitrary values to the ENABLE field in the ENABLE register is unsafe, because only values 0 or 8 should be used. + +## In this exercise you will learn how to: +* to safely write into a register +* how to write raw bits into a register +* how to read a register + +## Prerequisites +* basic use of closures +* usage of the svd2rust's read/write/modify API + +## Tasks +* Find out which values can be written into the `enable` register. +* Take ownership of the board's peripherals +* Write a helper function that reads `UARTE0`'s `enable` register and prints the enable status. +* Enable the UARTE0 peripheral using a safe method. +* Disable the UARTE0 peripheral by writing raw bits in it (unsafe). + +Final terminal output: + +```terminal +Uarte0 is disabled. +Uarte0 is ensabled. +Uarte0 is disabled. +``` + +Find the starter code in `down-the-stack/apps/src/bin/uarte_enable.rs` +Find the full solution in `down-the-stack/solutions/src/bin/uarte_enable.rs` + + +## Step-by-Step Solution + +### Step 1: Find the values that can be written in the `enable` register: + +0: disabled +8: enabled + +### Step 2: Import the PAC + +In the Cargo configuration file for the `apps` package, `down-the-stack/apps/Cargo.toml`, add: + +``` +dk_pac = { path = "../dk_pac", features = ["critical-section"]} +``` +In the main source file for the `uarte_enable` binary, `apps/bin/uarte_enable.rs`, add: + +```rust +use dk_pac::UARTE0; +``` + +### Step 3: Take ownership of the peripherals with `take()` + +Take ownership of the peripherals with `take()`. Be aware, the take returns an `Option` so that needs to be taken care of. Bind the `UARTE0` peripheral to its own variable. + +```rust +let periph = dk_pac::Peripherals::take().unwrap(); +let uarte = periph.UARTE0; +``` + +### Step 4: Write a helper function to get the status of the register. + +The helper function either reads the raw bits of the enable register or makes use of the specific method available. + +The function prints "Uarte0 is enabled" or "Uarte0 is disabled" depending on the case. Add a function call to `fn main()`. + +Run the code. The terminal output should read: "Uarte0 is disabled". + +```rust +fn is_uarte_enabled(uarte: &UARTE0) { + if uarte.enable.read().enable().is_enabled() { + defmt::println!("Uarte0 is enabled"); + } else { + defmt::println!("Uarte0 is disabled"); + } +} +``` + +### Step 5: Enable the peripheral safely. + +Enable the peripheral safely by passing `w.enable().enabled()` in the closure of a call to `write()` on the `enable` field of our UARTE object. Call the helper function after this new line and run your code. + +It should print: + +```terminal +Uarte0 is disabled. +Uarte0 is ensabled. +``` + +```rust +uarte.enable.write(|w| w.enable().enabled()); +``` + +### Step 6: Disable the peripheral unsafely by writing raw bits into the register. + +Write 0 into the register to disable it by passing the closure `|w| w.bits(0u32)` to the `write()` method. This action is unsafe, so it needs to be in an unsafe block. Call the helper function once more and run your code. Compare your output with the expected output on top of this page. + +```rust +unsafe { + uarte.enable.write(|w| w.bits(0x00 as u32)); + } +``` diff --git a/embedded-workshop-book/src/generating-pac.md b/embedded-workshop-book/src/generating-pac.md new file mode 100644 index 00000000..9f817894 --- /dev/null +++ b/embedded-workshop-book/src/generating-pac.md @@ -0,0 +1,79 @@ +# Generating the PAC + +Generate your own PAC from an SVD file. + +## In this exercise you will learn how to +* generate a PAC from an SVD file. +* format the generated code. +* split the single PAC file into one file per module. + +## Prerequisites +* usage of cargo install +* generating docs + +## Tasks +* Install `svd2rust` and `form` via cargo. +* Run `svd2rust` on `nrf52.svd` using the `cortex-m` target. +* Split the file into its modules using `form`. +* Format the generated file to make it readable. +* Check the documentation. + +## Step-by-Step Solution + + +✅ Install the necessary tools using the following commands: + +```terminal +cargo install svd2rust +cargo install form +``` + +✅ Go `down-the-stack/dk-pac`. The folder contains the SVD file `nrf52.svd`. We also provide a `Cargo.toml` file, as it will not be generated by svd2rust. + +✅ In the terminal, go to the SVD file's location. Run `svd2rust` with the SVD file to generate a PAC using the `cortex-m` target. + +``` +svd2rust --target cortex-m -i nrf52.svd +``` +If you check the folder `down-the-stack/dk-pac` now, you see three new files: +* lib.rs - the file that contains the generated code for the pac +* device.x - linker script that weakly aliases all the interrupt handlers to the default exception handler (DefaultHandler). +* build.rs - build script that places device.x somewhere the linker can find. + +✅ Make an `/src` and move the generated `lib.rs` into it. + +✅ Open the generated `lib.rs` with an editor. +Notice how it's barely correctly formatted. + +✅ Look at the PAC docs with the following command: + +```terminal +cargo doc --open +``` + +✅ Format the crate using `cargo fmt`. +This does not change to the docs, but `lib.rs` is a bit more readable. + +✅ Use form to process the `lib.rs` to split it into modules, so that each module in in it's own file. + +```terminal +form -i src/lib.rs -o src/ +``` + +✅ Re-run `cargo fmt`. + + + +## Troubleshooting + +### `form` + +In case the `form` command above causes problems, try this instead: + +1. Move `lib.rs` out of `/src`. + +2. Run the following command: + +```terminal +form -i ./lib.rs -o ./src +``` \ No newline at end of file diff --git a/embedded-workshop-book/src/installation.md b/embedded-workshop-book/src/installation.md index d4104a17..92c7bc73 100644 --- a/embedded-workshop-book/src/installation.md +++ b/embedded-workshop-book/src/installation.md @@ -157,3 +157,6 @@ $ cargo install nrfdfu (..) Installed package `nrfdfu v0.1.3` (..) ``` +## pySerial for Down The Stack + +If you don't have a serial terminal you're familiar with, we recommend using `pySerial`. Follow the installation instructions [here](https://pythonhosted.org/pyserial/pyserial.html#installation). This may require an update of your python installation. This is needed for the second day of the 3 day embedded training. \ No newline at end of file diff --git a/embedded-workshop-book/src/pac-docs.md b/embedded-workshop-book/src/pac-docs.md new file mode 100644 index 00000000..f3b91824 --- /dev/null +++ b/embedded-workshop-book/src/pac-docs.md @@ -0,0 +1,47 @@ +# Reading PAC Documentation +(This should be covered or at least preceded by a lecture that includes basic use of closures and the read/write/modify API) + +Generate and open the PAC's docs using the following command: + +``` +cargo doc --open +``` + +In the `Structs` section look for the `struct Peripherals`. Taking ownership of it will be the first step later on. Note that only the method `steal()` is documented. It is an unsafe method, and to be avoided. `Peripherals` has a field named `UARTE0`. + +In the `modules` section, look for the `uarte0` module. It is divided into submodules. `enable` is the register we are concerned about. Clicking on it shows the associated type definitions. + +* `W` - the writer proxy for the ENABLE register, with the following methods: + * `enable()` returns the field ENABLE writer `ENABLE_W`. + * `unsafe bits()` writes raw bits into the register. +* `R` - the reader proxy for the ENABLE register, with the following methods: + * `enable()` returns the field ENABLE reader `ENABLE_R`. + * `bits()` reads raw bits from the register. + +The types `ENABLE_R` and `ENABLE_W` have methods that you can use if you don't want to deal with raw bits. Check them out! + +Usage: If you want to write or read something from the uarte register and you want to avoid dealing with raw bits, you first have to call a method that gives you access to the respective reader or writer, and then call the method that does what you want. + +Example: + +```rust +// this reads the enable register, and returns true if the register is disabled. +uarte.enable.read().is_disabled() +``` + +Note the difference between the struct field `UARTE0` in `Peripherals` and the module `uarte0`. + +## Finding corresponding sections in the PAC + +* `dk_pac/src/lib.rs` defines the singleton peripherals as part of a larger `struct Peripherals`. There are two methods for this struct: `take()` and `steal()`. `take()` assures, that only one instance of this can exist. Hence, it's safe. Note that `take()` is only available with the `critical-section` feature enabled. + +To generate documentation that includes `take()`, pass the `critical-section` feature flag when generating the docs: + +``` +cargo doc --open --features critical-section +``` + +* `dk_pac/src/uarte0.rs` defines a struct that contains all the registers of the `UARTE0` peripheral. The `enable` field represents the register of the same name. + +* `dk_pac/src/uarte0/enable.rs` defines the types associated with this register that you already saw in the docs. + diff --git a/embedded-workshop-book/src/pac-exercise.md b/embedded-workshop-book/src/pac-exercise.md new file mode 100644 index 00000000..8f308612 --- /dev/null +++ b/embedded-workshop-book/src/pac-exercise.md @@ -0,0 +1,5 @@ +# Generating and Using a PAC + +In this module you will learn how to generate a PAC (Peripheral Access Crate) from an SVD file, read its documentation and write a small program that enables the UARTE0 peripheral. + + diff --git a/embedded-workshop-book/src/uarte-implementation.md b/embedded-workshop-book/src/uarte-implementation.md new file mode 100644 index 00000000..02953d4d --- /dev/null +++ b/embedded-workshop-book/src/uarte-implementation.md @@ -0,0 +1,204 @@ +# Write the Uarte implementation +## Step-by-Step Solution + +### Step 1: Check Documentation. + +The UART protocol requires up to four pins, two are mandatory, additional two are optional. they are usually labelled: +* RXD +* TXD +* CTS (optional) +* RTS (optional) + +We will only use the mandatory ones. + +✅ Check the [User Guide in section 7.2](https://infocenter.nordicsemi.com/topic/ug_nrf52840_dk/UG/dk/vir_com_port.html) to find to find out which pins are reserved for these and what their configuration needs to be. + +### Step 2: Explore the `nrf-hal` to find out what needs to be done. + + +The `nrf52840-hal` is a crate that exports all the `52840` flagged features from the `nrf-hal-common`. Let's take a look at the `nrf52840-hal`'s [Uarte module](https://github.com/nrf-rs/nrf-hal/blob/v0.14.1/nrf-hal-common/src/uarte.rs). + +In line 16 we see, that the nRF52840 uses the `hal::pac::UARTE1` peripheral. +In line 44 you find the `struct Uarte(T)`, the interface to a UARTE instance `T`. Besides the instance `T`, the instantiating method takes variables of the following types as arguments: `Pins`, `Parity` and `Baudrate`. + +A quick search of the document reveals where to find all of them: +* `Pins`: Line 463 +* `Parity` and `Baudrate`: Re-export on line 34 + +✅ Add the following lines as import: + +``` +use hal::pac::uarte0::{ + baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity}; +use hal::uarte; +``` + +### Step 3: Add `struct Uarte` + +✅ Add `struct Uarte` that serves as a wrapper for underlying HAL UART driver. + +The struct has one field labelled `inner` which is of type `hal::Uarte` but with the type parameter `T` being set to `hal::pac::UARTE1`. + +The main difference between using our `Uarte` object and the underlying HAL `Uarte` object is that *ours* will be pre-configured for the correct pins and baud rate, according to the layout of our nRF52840-DK board and the Virtual COM Port interface chip on the other end of the UART link. + +
+ Solution + +```rust +pub struct Uarte { + inner: hal::Uarte, +} +``` +
+ +### Step 4: Bring up the peripheral in the `fn init()` + +✅ Take a closer look at the definition of the `uarte::Pins` struct in the `nrf-hal`. Compare the pin type configurations with the ones you have already imported in `lib.rs`. Add the ones you're missing. + +✅ Create an instance of this struct in `fn init()` with the appropriate pins and configurations. Set the output pin's level to `Level::High`. +Note, that the third and fourth pin are each wrapped in an `Option`: Their type is `None` in this case. + +✅ Create a Uarte driver with `hal::uarte::Uarte::new(...)` and bind it to a variable called `uarte` - we will stash this in our own `Uarte` struct later. + +Creating the Uarte driver requires four arguments: +* The `UARTE1` instance can be found in the `periph` variable. +* Your instance of the `uarte::Pins` struct. +* Set parity to `Parity::EXCLUDED` +* set the baud rate to `Baudrate::BAUD115200`. + +
+ Solution + +```rust + let pins = hal::uarte::Pins { + rxd: pins.p0_08.degrade().into_floating_input(), + txd: pins.p0_06.degrade().into_push_pull_output(Level::High), + cts: None, + rts: None, + }; + + + let uarte = hal::uarte::Uarte::new(periph.UARTE1, pins, Parity::EXCLUDED, Baudrate::BAUD115200); +``` +
+ +### Step 5: Board struct + +✅ Add a field for the `Uarte` struct in the `Board` struct. +add the field to the instance of the `Board` struct in `fn init()`. + +
+ Solution + +```rust + +pub struct Board { + /// LEDs + pub leds: Leds, + /// Buttons + pub buttons: Buttons, + /// Timer + pub timer: Timer, + /// uarte interface + pub uarte: Uarte, +} + +// ... + +pub fn init() -> Result { + + // ... + + Ok(Board { + leds: Leds { + // ... + }, + + buttons: Buttons { + // ... + }, + // 🔼 --- Button Exercise --- 🔼 + + timer: Timer { inner: timer }, + + uarte: Uarte { inner: uarte }, + }) + } else { + Err(()) + } +``` + +
+ +### Step 6: Implementing the `fmt::Write` trait + +We want to implement the `fmt::Write` trait so that users can call `write!` on our Uarte object + +When implementing this, we can't just write to the `Uarte` instance because a simple write of a string literal would try and read the string literal from flash memory. This does not work because the EasyDMA peripheral in the nRF52 series can only access RAM, not flash. + +Instead our implementation must ensure all the strings are copied to a stack allocated buffer and that buffer is passed to the Uarte's `write` method. + +✅ Add `use::core::fmt;` to your imports. + +✅ Create a public method `write_str`. It takes a mutable reference to self and a `&str` as argument. It returns an `fmt::Result` + +✅ Create a buffer. The type is an `array` of 16 u8, set to all 0. + +✅ To copy all data into an on-stack buffer, *iterate* over *chunks* of the string and copy them into the buffer (noting that the chunk length may be less than the requested size if you are at the end of the input string). + +
+ Solution + +```rust +impl fmt::Write for Uarte { + + fn write_str(&mut self, s: &str) -> fmt::Result { + // Copy all data into an on-stack buffer so we never try to EasyDMA from + // flash. + let mut buf: [u8; 16] = [0; 16]; + for block in s.as_bytes().chunks(16) { + buf[..block.len()].copy_from_slice(block); + self.inner.write(&buf[..block.len()]).map_err(|_| fmt::Error)?; + } + + Ok(()) + } +} +``` +
+ +### Step 7: Connect your computer to the virtual UART + +✅ Use the following command to find the address of the nRF52840-DK on your computer. + +Linux: +``` +$ ls /dev/ttyACM* +``` + +MacOS: + +``` +ls /dev/tty.usbmodem* +``` + +Windows: +a USB Serial Device (COM port) in the Device Manager under the Ports section. + +✅ Run the following command to run `miniterm` with the nRF52840-DK with 115200 baud. This includes the default settings of no parity, 8 data bits, 1 stop bit + +``` +python3 -m serial.tools.miniterm
115200 + +``` + +### Step 8: Run the example. + +✅ In another terminal window go into the folder `down-the-stack/apps` and use the following command. + +``` +cargo run --bin uarte_print +``` + +On your terminal window where `miniterm` runs, "Hello, World" should appear. +