Other RISC-V cores, and requirements to fit your project?

[likewise]

My interest is in running smaller RISC-V cores such as Ibex which are 3 to 4 times smaller than 32-bit Rocket, whilst still using your work for debugging etc. I am currently running the Ibex on a ZCU102 but using OpenOCD.

This approach does not allow concurrent logic ILA debugging as well as RISC-V software debugging.

What are the requirements for the RISC-V core to be supported by your work allowing easy debugging with Xilinx Vivado / Eclipse TCF/RISC-V?

The Ibex has a RISC-V compliant debug module.

[eugene-tarassov]

This repo provides 2 options to connect RISC-V compliant debug module:

1. Debug Module Interface adapter - faster and smaller, connects directly to RISC-V compliant Debug Module, replaces JTAG Debug Transport Module.

2. Debug Bridge (in BSCAN Primitive mode) to JTAG adapter - implements standard JTAG, connects to RISC-V JTAG Debug Transport Module, can be used to connect any IP with JTAG slave port.

Both allow concurrent logic ILA debugging as well as RISC-V software debugging.

[likewise]

Thank you Eugene.

Currently I have the Ibex RISC-V (6k LUT, 5k FF) running on my ZCU102 board. It claims the debug module is according to the RISC-V debug specification v0.13.1. I can debug using vanilla OpenOCD 0.11.0. https://github.com/pulp-platform/riscv-dbg

This module uses two BSCANE2s: https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_bscane_tap.sv

Can I then also use XSCT 2020.2 to debug this core?

xsct% targets
1 PS TAP
2 PMU
3 PL
4 Legacy Debug Hub
5 PSU
6 RPU (Reset)
7 Cortex-R5 #0 (RPU Reset)
8 Cortex-R5 #1 (RPU Reset)
9 APU (L2 Cache Reset)
10 Cortex-A53 #0 (APU Reset)
11 Cortex-A53 #1 (APU Reset)
12 Cortex-A53 #2 (APU Reset)
13 Cortex-A53 #3 (APU Reset)

[eugene-tarassov]

No, two BSCANE2s dmi_bscane_tap.sv is not supported by Xilinx tools. XSCT needs one of 2 adapters I mentioned, or external (second) JTAG. You have to change you design to allow XSCT access to RISC-V cores.

XSCT version 2020.2 should work OK to debug the core, but it is better to use latest version 2021.2 - there were a lot of improvements in RISC-V support.

[rickoco]

@likewise and @eugene-tarassov - you might also want to have a look at the OpenHW CORE-V cores which originated at ETH Zurich and have support for various Xilinx platforms. @eugene-tarassov it would be great to sync your project with the work underway in the OpenHW open-source community.

[likewise]

I am aware. Ibex also originated at ETH Zurich.

[likewise]

Thank you Eugene. Your project goals might be out-of-scope for me, but I was mostly intrigued by this:

Latest Xilinx tools (Ver. 2020.1+) support debugging of RISC-V software over JTAG.

Together with the fact that concurrent access to FPGA logic and RISC-V debug module would be possible.

• Where can I find the documentation on the RISC-V debugging support in latest Vivado tools? Which tools are involved?
• I would be greatly helped already if I can hook up my cross RISC-V GDB to XSCT (similar how I hook it up to OpenOCD).
• I am familiar with TCF a bit from Linux development, but does it apply to bare-metal as well?

If you could provide a bit of help here, that is much appreciated, thank you.

[eugene-tarassov]

RISC-V is supported by Xilinx Hardware Server.
No setup needed, RISC-V is autodetected same way as ARM and MicroBlaze cores.
All XSDB, XSCT, Hardware Server documentation apply to RISC-V.

Since Hardware Server is a customized TCF agent, it includes TCF implementation of GDB Server protocol: gdb-rsp.c.
However, GDB support is considered to be legacy feature - Hardware Server itself provides source level debugging.

I can hook up my cross RISC-V GDB to XSCT

I guess you mean "GDB to Hardware Server". XSCT is just a Tcl script, which can talk to the Hardware Server or any other TCF agent. Connecting GDB to XSCT does not make sense.

Also, see https://wiki.eclipse.org/TCF/RISC-V

[likewise]

Thank you Eugene.

[likewise]

I have added the Debug Module Interface adapter you referred to, to the Ibex RISC-V. That part seamed easy.

However, xsct does not recognize the RISC-V target with Vivado 2020.2.

How could I further proceed debugging this?

xsct% connect
tcfchan#0
xsct% jtag targets
  1  Xilinx Alveo-DMBv1 FT4232H 500202A507FAA
     2  xcu50_u55n (idcode 14b77093 irlen 12 fpga)

`ifdef XILINX_RISCV_JTAG
  //typedef struct packed {
   // logic [6:0]  addr;
   // dtm_op_e     op;
   // logic [31:0] data;
  //} dmi_req_t;

  //typedef struct packed  {
   // logic [31:0] data;
   // logic [1:0]  resp;
  //} dmi_resp_t;

  // JTAG TAP (from https://github.com/eugene-tarassov)
  JtagSeries7 #(.JTAG_CHAIN(2)) dmi_tap_xilinx (
    .clock(clk_i),
    .reset(!rst_ni),
    // Debug Module interface
    .dmi_o_ready(dmi_req_ready),
    .dmi_o_valid(dmi_req_valid),
    .dmi_o_addr(dmi_req.addr),
    .dmi_o_data(dmi_req.data),
    .dmi_o_op(dmi_req.op),

    .dmi_i_ready(dmi_rsp_ready),
    .dmi_i_valid(dmi_rsp_valid),
    .dmi_i_data(dmi_rsp.data),
    .dmi_i_resp(dmi_rsp.resp)
  );
`else
  // JTAG TAP (PULP)
  dmi_jtag #(
    .IdcodeValue    (IdcodeValue)
  ) dap (
    .clk_i            (clk_i),
    .rst_ni           (rst_ni),
    .testmode_i       (testmode_i),

    .dmi_rst_no       (dmi_rst_n),
    .dmi_req_o        (dmi_req),
    .dmi_req_valid_o  (dmi_req_valid),
    .dmi_req_ready_i  (dmi_req_ready),

    .dmi_resp_i       (dmi_rsp      ),
    .dmi_resp_ready_o (dmi_rsp_ready),
    .dmi_resp_valid_i (dmi_rsp_valid),

    //JTAG
    .tck_i            (1'b0),
    .tms_i            (1'b0),
    .trst_ni          (1'b0),
    .td_i             (1'b0),
    .td_o             (),
    .tdo_oe_o         ()
  );
`endif // XILINX_RISCV_JTAG

[eugene-tarassov]

What does targets command show?

[likewise]

Thanks, XSDB/XSCT is a bit new to me (again). Indeed targets shows the RISC-V. (I was purely using jtag targets). Proceeding further.

xsct% targets
  1  xcu50_u55n
     2  RISC-V JTAG DTM (Debug Transport Module timeout)
     3  Legacy Debug Hub

[eugene-tarassov]

If you exit xsct and manually start hw_server with additional arguments -L- -ljtag, then reconnect xsct, hw_server will print a log of all JTAG activity. It can help to debug "Debug Transport Module timeout".