Alveo_U280 Support Seeking

[MrJimbo2002]

Hi Mr.Eugene, many thanks for your such detailed open-source project sharing.

I am new to FPGA and Vivado and please accept my apologies asking not deep questions:

I want to port your U250 design to U280 but encountered the problems below:

I have checked with the documents of QSFP28 Interface, but not sure how to modify the LOC parameter of "dict" as N4, N3 ... AU22 listed in top.xdc.

In terms of the Memory Core Error, I attempted to grep riscv_i/DDR/ddr4_0 and seems that there is no indication of SRL(Super Regional Logic block) and hence no I/O banks for each SLR were found.

Could you help me to debug the above critical warnings and error messages?

Thank you very much in advance for your time commitment and help~