RiscV Jtag and FPGA Bscan

[HaogeL]

Hi Eugene,

In the README, you mentioned that Latest Xilinx tools (Ver. 2020.1+) support debugging of RISC-V software over JTAG.
What is the prerequisite for that? Do I have to instantiate Bscane2 primitive in RiscV to use the same JTAG as FPGA to make this happen? What is the mechanism behind this? Any reference?

I am mapping rocket-chip to VCU128 and trying to access RiscV debug Jtag via Bscane2 primitive by openocd nested tap, refer to
https://github.com/sifive/fpga-shells/blob/master/src/main/scala/ip/xilinx/bscan/bscan.scala
https://github.com/riscv/riscv-openocd/blob/8bb25e007972a153653d3437e63bb50eb8e916e2/src/target/riscv/riscv.c#L254
Unfortunately, I haven't succeeded yet.

Sorry for bothering you with these questions. Thank you in advance!

Best regards,
HG

[eugene-tarassov]

Projects in this repo are configured to support Xilinx tools: HW Server, XSDB, Vitis, etc.
They use BSCANE2 primitive (see jtag.vhdl) and provide same level of debugging support as OpenOCD + GDB.
However, it is not same RTL as SiFive/OpenOCD.
To use OpenOCD, you need to change the design to use SiFive version of BSCAN debug adapter.

[HaogeL]

Thank you for the answer!

I see, this repo uses Bscane2 primitive to provide debug input (in JTAG and DMI) to RV core from FPGA TAP.
jtag.vhdl and JtagExtBscan.vhdl converts the BSCAN/JTAG to DMI. The difference is that for JtagExtBscan.vhdl we need to provide Bscan input externally.

Besides, bscan2jtag.vhdl converts Xilinx XSDB BSCAN/JTAG to RV debug JTAG, and we need to provide Bscan input externally.

Do I understand it correctly?

/HG

[eugene-tarassov]

jtag.vhdl and JtagExtBscan.vhdl converts the BSCAN/JTAG to DMI.

Yes

The difference is that for JtagExtBscan.vhdl we need to provide Bscan input externally.

Yes. Note that you have to use BSCAN Switch between BSCAN and JtagExtBscan. The idea is to share single BSCAN register between multiple IPs.

Besides, bscan2jtag.vhdl converts Xilinx XSDB BSCAN/JTAG to RV debug JTAG, and we need to provide Bscan input externally.

Yes, but it is not just for RV. It is generic JTAG adapter, it will work with any JTAG slave.
And it also requires BSCAN Switch.

[coolwinner]

Hi Eugene,

As you mentioned above, the RTL design is different for supporting Xilinx tools (such as xsdb) and OpenOCD. So I want to ask if one RTL design can support them in the meanwhile? If yes ,could you give some suggestions?

Looking forward to your reply.

Thank you very much！

BRs，
cw