LiteDRAM core targeting DDR3 issues activate command twice for a write operation

[dinaabdelbaky]

Hi I have generated the code as in issue #344, I issued a write command on the wishbone interface, then a read command to the same location. I got read data mismatch, please refer to figure one. The same issue happened with more than one seed and on the AXI interface as well. This only happens for the first write read operation for the rest of the test there is no mismatch. After further digging the first write command the activate takes place twice at the same time, one on phase2, please refer to figure2. Also, for the read operation the rddata_en sent to the dfi seemed not correct. Please refer to figure 3. Kindly advise