ulx3s example does not work #329
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I finally got this to work by crossreferencing some stuff from https://github.com/BrunoLevy/learn-fpga The core problem turned out to be that the dram module seems to need to run at 50MHz, and the dram clock must be pahse offset from the system clock To make it work, for anyone reading: Generate a dram controller Set up a custom build.sh: build.ys lpf.lpf Finally, you'll need a module top(
input wire clk25,
input wire rst,
output reg uart_tx,
input wire uart_rx,
output wire [12:0] sdram_a,
output wire [1:0] sdram_ba,
output wire sdram_ras_n,
output wire sdram_cas_n,
output wire sdram_we_n,
output wire sdram_cs_n,
output wire [1:0] sdram_dm,
input wire [15:0] sdram_dq,
output wire sdram_cke,
output wire init_done,
output wire init_error,
output wire sdram_clock,
output wire user_rst
);
wire main_ecp5pll0_clkout0;
wire main_ecp5pll0_clkout1;
wire sys_ps_clk;
(* FREQUENCY_PIN_CLKI = "25.0", FREQUENCY_PIN_CLKOP = "50.0", FREQUENCY_PIN_CLKOS = "50.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *)
EHXPLLL #(
.CLKFB_DIV(5'd16),
.CLKI_DIV(1'd1),
.CLKOP_CPHASE(3'd7),
.CLKOP_DIV(4'd8),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_FPHASE(1'd0),
.CLKOS2_CPHASE(1'd0),
.CLKOS2_DIV(1'd1),
.CLKOS2_ENABLE("ENABLED"),
.CLKOS2_FPHASE(1'd0),
.CLKOS_CPHASE(4'd9),
.CLKOS_DIV(4'd8),
.CLKOS_ENABLE("ENABLED"),
.CLKOS_FPHASE(1'd0),
.FEEDBK_PATH("INT_OS2")
) EHXPLLL (
.CLKI(clk25),
.RST(main_pll_reset),
.STDBY(main_pll_stdby),
.CLKOP(main_ecp5pll0_clkout0),
.CLKOS(main_ecp5pll0_clkout1),
.CLKOS2(builder_basesoc_ecp5pll0_ecp5pll),
.LOCK(builder_basesoc_ecp5pll0_locked)
);
sdram_controller sub
( .uart_tx(uart_tx)
, .uart_rx(uart_rx)
, .clk(main_ecp5pll0_clkout0)
, .rst(rst)
, .sdram_a(sdram_a)
, .sdram_ba(sdram_ba)
, .sdram_ras_n(sdram_ras_n)
, .sdram_cas_n(sdram_cas_n)
, .sdram_we_n(sdram_we_n)
, .sdram_cs_n(sdram_cs_n)
, .sdram_dm(sdram_dm)
, .sdram_dq(sdram_dq)
, .sdram_cke(sdram_cke)
, .init_done(init_done)
, .init_error(init_error)
, .user_clk(user_clk)
, .user_rst(user_rst)
);
assign sys_ps_clk = main_ecp5pll0_clkout1;
ODDRX1F ODDRX1F(
.D0(1'd1),
.D1(1'd0),
.SCLK(sys_ps_clk),
.Q(sdram_clock)
);
endmodulePerhaps there are better ways to achieve this, but at least this gets it working. |
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Hi @TheZoq2, sorry for the delay and good to know you've got it running. The approach used seems fine. Thanks for sharing your project, this will be useful for users willing do the the same. I'll also probably add a link to it in the wiki. |
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Cool! Thanks for your work on this project, it is really useful! |
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I'm trying to generate a litedram core for my ulx3s, but am having some trouble. As a first step, I want to see if I can get it working in the simplest configuration possible, so I removed all
user_portsfrom the ulx3s example, modified the device from -45F to -85F as that's the device I have, and I changed the CPU to vexriscv instead of serv, to make the init process faster.Finally, I changed the sys_clk_freq to 25e6 instead of 50e6, which is what the ulx3s clock is natively.
This is my modified yml
I built it with
The core boots fine, but sdram_init fails
I also tried changing the sdram_module to
IS42S16160as that is what is included on pre-2022 ulx3s boards https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#board-versionsFinally I use this lpf file
in which I copied most configurations from https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
The only significant changes I made to it was to remove
sdram_clkand replace it byuser_clk(under the assumption thatuser_clkonly forwards thesys_clk. I also renamedsdram_dqmfrom the original file withsdram_dmAm I missing something here that makes this not work?
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