Merge pull request #203 from emu-russia/167-add-pal-ppu-support-ppusim

PAL PPU Logic

BreaksPPU/PPUSim/debug.cpp

@@ -278,16 +278,6 @@ namespace PPUSim
 		return ((uint16_t)PATop << 8) | PABot;
 	}
 
-	void PPU::Dbg_RandomizePicture(bool enable)
-	{
-		vid_out->Dbg_RandomizePicture(enable);
-	}
-
-	void PPU::Dbg_FixedPicture(bool enable)
-	{
-		vid_out->Dbg_FixedPicture(enable);
-	}
-
 	void PPU::Dbg_RenderAlwaysEnabled(bool enable)
 	{
 		regs->Debug_RenderAlwaysEnabled(enable);

BreaksPPU/PPUSim/fsm.cpp

@@ -275,18 +275,18 @@ namespace PPUSim
 			case Revision::RP2C07_0:
 			{
 				ctrl_latch1.set(NOT(HPLA[23]), n_PCLK);
+				ctrl_latch2.set(VPLA[8], n_PCLK);
 			}
 			break;
 
 			default:
 			{
 				ctrl_latch1.set(NOR(HPLA[23], EvenOddOut), n_PCLK);
+				ctrl_latch2.set(VPLA[2], n_PCLK);
 			}
 			break;
 		}
 
-		ctrl_latch2.set(VPLA[2], n_PCLK);
-
 		ppu->wire.HC = ctrl_latch1.nget();
 		ppu->wire.VC = NOR(NOT(ppu->wire.HC), ctrl_latch2.nget());
 	}

BreaksPPU/PPUSim/ppu.h

@@ -474,8 +474,6 @@ namespace PPUSim
 		void Dbg_CRAMWriteByte(size_t addr, uint8_t val);
 		uint8_t Dbg_GetCRAMAddress();
 		uint16_t Dbg_GetPPUAddress();
-		void Dbg_RandomizePicture(bool enable);
-		void Dbg_FixedPicture(bool enable);
 		void Dbg_RenderAlwaysEnabled(bool enable);
 		void Dbg_SetCTRL0(uint8_t val);
 		void Dbg_SetCTRL1(uint8_t val);

BreaksPPU/PPUSim/regs.cpp

@@ -207,7 +207,20 @@ namespace PPUSim
 		ppu->wire.O8_16 = NOT(o816_latch.nget());
 
 		ppu->wire.n_SLAVE = PPU_CTRL0[6].get();
-		ppu->wire.VBL = PPU_CTRL0[7].get();
+
+		switch (ppu->rev)
+		{
+			// The PAL PPU uses a hidden latch for the VBL signal, which is stored between the open transistor and the inverter in the VBlank INT circuit.
+
+			case Revision::RP2C07_0:
+				vbl_latch.set(PPU_CTRL0[7].get(), NOT(W0_Enable));
+				ppu->wire.VBL = vbl_latch.get();
+				break;
+
+			default:
+				ppu->wire.VBL = PPU_CTRL0[7].get();
+				break;
+		}
 
 		// CTRL1
 

BreaksPPU/PPUSim/regs.h

@@ -38,6 +38,7 @@ namespace PPUSim
 		BaseLogic::FF BLACK_FF2;
 		BaseLogic::DLatch black_latch1;
 		BaseLogic::DLatch black_latch2;
+		BaseLogic::DLatch vbl_latch;
 
 		void sim_RegularRegOps();
 		void sim_W56RegOps();

BreaksPPU/PPUSim/sprite_eval.cpp

@@ -141,18 +141,47 @@ namespace PPUSim
 	void OAMEval::sim_MainCounterControl()
 	{
 		TriState n_PCLK = ppu->wire.n_PCLK;
+		TriState PCLK = ppu->wire.PCLK;
 		TriState I_OAM2 = ppu->fsm.IOAM2;
 		TriState n_VIS = ppu->fsm.nVIS;
 		TriState H0_DD = ppu->wire.H0_Dash2;
 		TriState OFETCH = ppu->wire.OFETCH;
 		TriState n_W3 = ppu->wire.n_W3;
 		TriState n_DBE = ppu->wire.n_DBE;
+		TriState ZOMG{};
+
+		switch (ppu->rev)
+		{
+			// For the PAL PPU, the $2003 write delay is screwed on. This is most likely how they fight OAM Corruption.
+
+			case Revision::RP2C07_0:
+			{
+				auto W3 = NOR(n_W3, n_DBE);
+				W3_FF1.set(NOR(NOR(W3, W3_FF1.get()), w3_latch3.nget()));
+				auto w3_ff1_out = NOR(W3_FF1.nget(), W3);
+				W3_FF2.set(NOT(NOT(MUX(PCLK, W3_FF2.get(), w3_ff1_out))));
+				w3_latch1.set(W3_FF2.nget(), n_PCLK);
+				w3_latch2.set(w3_latch1.nget(), PCLK);
+				w3_latch3.set(w3_latch2.nget(), n_PCLK);
+				w3_latch4.set(w3_latch3.nget(), PCLK);
+				W3_Enable = NOR(w3_latch4.get(), w3_latch2.nget());
+
+				// ZOMG comes from the circuit located in the same place as the EVEN/ODD circuit for the NTSC PPU (to the right of the V Decoder).
+
+				ZOMG = ppu->wire.EvenOddOut;
+				break;
+			}
 
-		auto W3_Enable = NOR(n_W3, n_DBE);
+			default:
+				W3_Enable = NOR(n_W3, n_DBE);
+				// In order not to change the logic below the pseudo-ZOMG is made equal to 0 and NOR becomes NOT.
+				ZOMG = TriState::Zero;
+				break;
+		}
 
 		init_latch.set(NAND(NOR(I_OAM2, n_VIS), H0_DD), n_PCLK);
 		ofetch_latch.set(OFETCH, n_PCLK);
-		OMSTEP = NAND(OR(init_latch.get(), n_PCLK), NOT(NOR(ofetch_latch.nget(), n_PCLK)));
+		OMSTEP = NAND(OR(init_latch.get(), n_PCLK), NOR(NOR(ofetch_latch.nget(), n_PCLK), ZOMG));
 		OMOUT = NOR(OMSTEP, W3_Enable);
 	}
 
@@ -164,11 +193,8 @@ namespace PPUSim
 		TriState PAR_O = ppu->fsm.PARO;
 		TriState OMOUT = this->OMOUT;
 		TriState OMSTEP = this->OMSTEP;
-		TriState n_W3 = ppu->wire.n_W3;
-		TriState n_DBE = ppu->wire.n_DBE;
 		TriState n_out[8]{};
 		auto Mode4 = NOR(BLNK, NOT(OMFG));
-		auto W3_Enable = NOR(n_W3, n_DBE);
 		TriState carry_in;
 		TriState carry_out;
 
@@ -291,8 +317,23 @@ namespace PPUSim
 		TriState n_VIS = ppu->fsm.nVIS;
 		TriState H0_DD = ppu->wire.H0_Dash2;
 		TriState BLNK = ppu->fsm.BLNK;
+		TriState OAP{};
+
+		switch (ppu->rev)
+		{
+			case Revision::RP2C07_0:
+			{
+				TriState n_PCLK = ppu->wire.n_PCLK;
+				blnk_latch.set(BLNK, n_PCLK);
+				OAP = NAND(OR(n_VIS, H0_DD), blnk_latch.nget());
+				break;
+			}
+
+			default:
+				OAP = NAND(OR(n_VIS, H0_DD), NOT(BLNK));
+				break;
+		}
 
-		auto OAP = NAND(OR(n_VIS, H0_DD), NOT(BLNK));
 		ppu->wire.OAM8 = NOT(OAP);
 
 		for (size_t n = 0; n < 3; n++)

BreaksPPU/PPUSim/sprite_eval.h

@@ -71,6 +71,16 @@ namespace PPUSim
 		BaseLogic::TriState DO_COPY = BaseLogic::TriState::X;
 		BaseLogic::TriState COPY_OVF = BaseLogic::TriState::X;
 		BaseLogic::TriState OB_Bits[8]{};
+		BaseLogic::TriState W3_Enable = BaseLogic::TriState::X;
+
+		// For PAL PPU
+		BaseLogic::DLatch blnk_latch;
+		BaseLogic::FF W3_FF1;
+		BaseLogic::FF W3_FF2;
+		BaseLogic::DLatch w3_latch1;
+		BaseLogic::DLatch w3_latch2;
+		BaseLogic::DLatch w3_latch3;
+		BaseLogic::DLatch w3_latch4;
 
 		BaseLogic::DLatch init_latch;
 		BaseLogic::DLatch ofetch_latch;