Multi pins

[kraemv]

Hey everyone,
I'm always frustrated when dealing with verilog netlists, that have buses as inputs. HAL does not allow me to write a verilog netlist, that has module inputs or outputs with a certain bus width.

At the moment, a netlist with:
input [1:0] a;
is written as:
input a(0);
input a(1);

This limits interoperability with commercial tools that require the first notation to denote buses.
It would be great to have some notion to detect buses, such as grouped input pins.
In the following netlist I would expect the groupings:
a, b, y

input_grouping_example.txt

[nils1603]

Hey kraemv,

not sure what exactly what you mean. Is your issue with parsing a netlist and the way nets are presented or using the HAL netlist verilog writer?

Currently we resolve all buses into single nets. Multi nets/buses are not supported and support is not planned, as it would require a significant rewrite of core functions.

However, we have started to implement module pin groups. For example, you can create a module and create a pin group. In the GUI nets are not grouped into buses.
https://emsec.github.io/hal/pydoc/module_pin_group.html