From 368eea0366fe1d62e5e7445c66510b6569da9d92 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Mon, 21 Oct 2024 10:48:30 +0300 Subject: [PATCH 1/4] feat: expose some CTS options Signed-off-by: Kareem Farid --- openlane/scripts/openroad/cts.tcl | 11 ++++++++++- openlane/steps/openroad.py | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/openlane/scripts/openroad/cts.tcl b/openlane/scripts/openroad/cts.tcl index 60faa3441..38226c234 100755 --- a/openlane/scripts/openroad/cts.tcl +++ b/openlane/scripts/openroad/cts.tcl @@ -50,11 +50,20 @@ lappend arg_list -sink_clustering_enable if { $::env(CTS_DISTANCE_BETWEEN_BUFFERS) != 0 } { lappend arg_list -distance_between_buffers $::env(CTS_DISTANCE_BETWEEN_BUFFERS) } - if { $::env(CTS_DISABLE_POST_PROCESSING) } { lappend arg_list -post_cts_disable } +if { [info exists ::env(CTS_OBSTRUCTION_AWARE)] && $::env(CTS_OBSTRUCTION_AWARE) } { + lappend arg_list -obstruction_aware +} +if { [info exists ::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT)] } { + lappend arg_list -sink_buffer_max_cap_derate [expr $::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT) / 100.0] +} +if { [info exists ::env(CTS_BALANCE_LEVELS)] && $::env(CTS_BALANCE_LEVELS) } { + lappend arg_list -balance_levels +} +puts "clock_tree_synthesis {*}$arg_list" clock_tree_synthesis {*}$arg_list set_propagated_clock [all_clocks] diff --git a/openlane/steps/openroad.py b/openlane/steps/openroad.py index a358145e0..3f2e42e09 100644 --- a/openlane/steps/openroad.py +++ b/openlane/steps/openroad.py @@ -2011,6 +2011,25 @@ class CTS(ResizerStep): OpenROADStep.config_vars + dpl_variables + [ + # sink_buffer_max_cap_derate + Variable( + "CTS_BALANCE_LEVELS", + Optional[bool], + "Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).", + ), + Variable( + "CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT", + Optional[Decimal], + "Controls automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value." + + "The value of 100 means no derating of max cap limit", + units="%", + ), + Variable( + "CTS_OBSTRUCTION_AWARE", + Optional[bool], + "Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. " + + "This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.", + ), Variable( "CTS_SINK_CLUSTERING_SIZE", int, From 933db4892d988dcee1d976aa6dad9aa52e80b887 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Mon, 21 Oct 2024 10:51:58 +0300 Subject: [PATCH 2/4] test variables Signed-off-by: Kareem Farid --- openlane/steps/openroad.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openlane/steps/openroad.py b/openlane/steps/openroad.py index 3f2e42e09..b21a69402 100644 --- a/openlane/steps/openroad.py +++ b/openlane/steps/openroad.py @@ -2016,6 +2016,7 @@ class CTS(ResizerStep): "CTS_BALANCE_LEVELS", Optional[bool], "Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).", + default=True, ), Variable( "CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT", @@ -2029,6 +2030,7 @@ class CTS(ResizerStep): Optional[bool], "Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. " + "This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.", + default=True, ), Variable( "CTS_SINK_CLUSTERING_SIZE", From fb92ee2d3d38a7b1b14f7528c9f5eb5d440d3309 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Tue, 22 Oct 2024 11:15:16 +0300 Subject: [PATCH 3/4] Revert "test variables" This reverts commit 933db4892d988dcee1d976aa6dad9aa52e80b887. --- openlane/steps/openroad.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/openlane/steps/openroad.py b/openlane/steps/openroad.py index b21a69402..3f2e42e09 100644 --- a/openlane/steps/openroad.py +++ b/openlane/steps/openroad.py @@ -2016,7 +2016,6 @@ class CTS(ResizerStep): "CTS_BALANCE_LEVELS", Optional[bool], "Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).", - default=True, ), Variable( "CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT", @@ -2030,7 +2029,6 @@ class CTS(ResizerStep): Optional[bool], "Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. " + "This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.", - default=True, ), Variable( "CTS_SINK_CLUSTERING_SIZE", From 7cb04fc7c87d9774f947c86ab0992267bb1f9792 Mon Sep 17 00:00:00 2001 From: Kareem Farid Date: Tue, 22 Oct 2024 11:17:38 +0300 Subject: [PATCH 4/4] add changelog --- .Changelog-dev.md | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 .Changelog-dev.md diff --git a/.Changelog-dev.md b/.Changelog-dev.md new file mode 100644 index 000000000..244dee2ec --- /dev/null +++ b/.Changelog-dev.md @@ -0,0 +1,7 @@ +# Dev + +## Steps + +* `OpenROAD.CTS` + * Added flags `CTS_OBSTRUCTION_AWARE` and `CTS_BALANCE_LEVELS` + * Added `CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT`