diff --git a/openlane/config/pdk_compat.py b/openlane/config/pdk_compat.py
index 0b0b5056a..fba99f9a7 100644
--- a/openlane/config/pdk_compat.py
+++ b/openlane/config/pdk_compat.py
@@ -214,6 +214,7 @@ def process_sta(key: str):
                 "max_ss_100C_1v60",
                 "max_ff_n40C_1v95",
             ]
+            new["SYNTH_CORNER"] = "*_ss_100C_1v60"
         elif new["PDK"].startswith("gf180mcu"):
             new["STA_CORNERS"] = [
                 "nom_tt_025C_5v00",
@@ -226,6 +227,7 @@ def process_sta(key: str):
                 "max_ss_125C_4v50",
                 "max_ff_n40C_5v50",
             ]
+            new["SYNTH_CORNER"] = "*_ss_125C_4v50"
 
         new["DEFAULT_CORNER"] = f"nom_{default_pvt}"
         new["LIB"] = lib_sta
diff --git a/openlane/steps/pyosys.py b/openlane/steps/pyosys.py
index 5b2935358..c2f12fd8b 100644
--- a/openlane/steps/pyosys.py
+++ b/openlane/steps/pyosys.py
@@ -237,6 +237,12 @@ class PyosysStep(Step):
             "Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.",
             default="ALL",
         ),
+        Variable(
+            "SYNTH_CORNER",
+            Optional[str],
+            "IPVT corners to use during resizer optimizations. If unspecified, the value for `STA_CORNERS` from the PDK will be used.",
+            pdk=True,
+        ),
     ]
 
     @abstractmethod
@@ -271,7 +277,9 @@ def get_command(self, state_in: State) -> List[str]:
         cmd = super().get_command(state_in)
 
         blackbox_models = []
-        scl_lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
+        scl_lib_list = self.toolbox.filter_views(
+            self.config, self.config["LIB"], self.config.get("SYNTH_CORNER")
+        )
         if self.power_defines and self.config["CELL_VERILOG_MODELS"] is not None:
             blackbox_models.extend(
                 [