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verified_IPs.json
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verified_IPs.json
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{
"IP_Utilities": {
"description": "A set of utilities that can be used to develop digital IPs in Verilog HDL",
"repo": "github.com/efabless/IP_Utilities",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "Apache 2.0",
"tags": [
"fifo",
"clock mux"
],
"release": {
"v1.0.0": {
"date": "30-09-2024",
"bus": [
],
"type": "soft",
"width": "0",
"height": "0",
"supply_voltage": [
"n/a"
],
"sha256": "c0ae31fb4252e40d4237623558d70e0fee1239e1c29f1e2ff906f1763f2aa690"
}
}
},
"EF_PSRAM_CTRL": {
"description": "A Controller for Quad I/O SPI PSRAM",
"repo": "github.com/efabless/EF_PSRAM_CTRL",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "Apache 2.0",
"tags": [
"memory",
"psram"
],
"release": {
"v1.0.0": {
"date": "4-01-2023",
"maturity": "Implemented",
"bus": [
"AHBL",
"WB"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "1a2530d23671d2fcfa711eb829b3018be30d6392da6b4936f1341366c5074e2a"
}
}
},
"EF_PSRAM_CTRL_V2": {
"description": "A Controller for Quad I/O SPI PSRAM",
"repo": "github.com/efabless/EF_PSRAM_CTRL_V2",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "Apache 2.0",
"tags": [
"memory",
"psram"
],
"release": {
"v1.0.0": {
"date": "4-01-2023",
"maturity": "Implemented",
"bus": [
"AHBL",
"WB"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "242120c67a172f6ff549e10770e8f12d317eda0e7dc2cd5d75cc1eb9ea5b7c8c"
},
"v1.0.1": {
"date": "4-01-2023",
"maturity": "Implemented",
"bus": [
"AHBL",
"WB"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "85cb2c2ca2d843f59fd7118cef477e2d8b5104a92d8a2308b54f55e369a10f8f"
},
"v1.0.2": {
"date": "4-01-2023",
"maturity": "Implemented",
"bus": [
"AHBL",
"WB"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "82f3819a519a66bd0713a649bb85456338b90796d484c2a80884d89cc2f6b6f0"
},
"v1.0.3": {
"date": "4-01-2023",
"maturity": "Integrated",
"bus": [
"AHBL",
"WB"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "da50e1b58d426bf4146775ede2757a3a173211fb93d9572fdcaa3fff0c5b4ef5"
},
"v1.0.4": {
"date": "07-05-2024",
"maturity": "Implemented",
"bus": [
"AHBL"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "b5c5f2b72cea9c93d6188e594404b488e6411c9acd551b528024393322031be6"
},
"v1.0.5": {
"date": "07-05-2024",
"maturity": "Implemented",
"bus": [
"AHBL"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "34659055f3fbf1e9a930ccb901d93b29a5b55724a4fc537a5b5da3ece57860c4"
},
"v1.0.6": {
"date": "5-11-2024",
"maturity": "Implemented",
"bus": [
"AHBL"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "f02a6c1753c36941fe125db44da58c0ac2f75741498904ce642246a776d46510"
},
"v1.0.7": {
"date": "8-11-2024",
"maturity": "Implemented",
"bus": [
"AHBL"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "17b9c15f92ff1bbfd153acb438a23daf59443ae2dcefdae8c2e7b0e5d377f99a"
},
"v1.0.8": {
"date": "27-11-2024",
"maturity": "Implemented",
"bus": [
"AHBL"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "530",
"clock_freq_mhz": "40",
"supply_voltage": [
"n/a"
],
"sha256": "98dd74a3263a468e557852b035a051ed6cd0590c6303e910295a54e2af834d9b"
}
}
},
"EF_UART": {
"description": "UART with a programmable baud rate generator and RX/TX FIFOs",
"repo": "github.com/efabless/EF_UART",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "APACHE 2.0",
"tags": [
"peripheral",
"comm"
],
"release": {
"v1.0.0": {
"date": "3-18-2023",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1057",
"clock_freq_mhz": "10",
"supply_voltage": [
"n/a"
],
"sha256": "ca1e8118e4420260237f7b7f81a8cab01b4020f3458f6a1634ffca3538e1d253"
},
"v1.1.0": {
"date": "15-4-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "6d15efb722dca3c7a7085b9c67ef0e6aba1dee2c5654a32e5adcc1f521890805"
},
"v1.1.1": {
"date": "07-5-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "6d15efb722dca3c7a7085b9c67ef0e6aba1dee2c5654a32e5adcc1f521890805"
},
"v1.1.2": {
"date": "12-5-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "66d0c6c38812a4f7dc6eb0e6026d5a6e04a4239d90065d91a1315e9cd964b7ed"
},
"v1.1.3": {
"date": "20-5-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "87cc3e08b380460e5f945d551e496012057af2a2006ff406faccf5357b270f8b"
},
"v1.1.4": {
"date": "20-5-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "7c09e4d49b50b68539d5f4e71036fc916c53aaaac2b9e0316f473c5ec5205e23"
},
"v1.1.5": {
"date": "20-5-2024",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "0a6850e5ecdc17ca726c8d7ce5f56f602fc31cb991f92c201e1ae99d5d0337f8"
},
"v1.1.6": {
"date": "20-5-2024",
"maturity": "Integrated",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "6678df8ec61a856054f9331cac9e9835a840becd82edb415828f9024dc716dd5"
},
"v1.1.7": {
"date": "17-09-2024",
"maturity": "Integrated",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "0c0069205a5d509e081405f214435661005e0b5302f00b6409ca4e4269e172d8"
},
"v1.1.8": {
"date": "4-11-2024",
"maturity": "Integrated",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "1590",
"clock_freq_mhz": "277",
"supply_voltage": [
"n/a"
],
"sha256": "23d908170beb4161e592dde1cb79d6f1583fa6327779d5790b41538101a6f8fe"
}
}
},
"EF_PWM32": {
"description": "A 32-bit dual channel PWM generator with a clock divider.",
"repo": "github.com/efabless/EF_PWM32",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "APACHE 2.0",
"tags": [
"peripheral",
"PWM",
"control"
],
"release": {
"v1.0.0": {
"date": "3-18-2023",
"maturity": "Integrated",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "730",
"clock_freq_mhz": "10",
"supply_voltage": [
"n/a"
],
"sha256": "47d1cdf641b3cb9e72ab4864df685997984c92d7a7b93122bd294483b3edebd4"
}
}
},
"EF_TCC32": {
"description": "A 32-bit Timer/Counter/Capture peripheral.",
"repo": "github.com/efabless/EF_TCC32",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Efabless Corp.",
"category": "digital",
"technology": "n/a",
"license": "APACHE 2.0",
"tags": [
"peripheral",
"timer",
"counter",
"capture"
],
"release": {
"v1.0.0": {
"date": "3-18-2023",
"maturity": "Implemented",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "690",
"clock_freq_mhz": "10",
"supply_voltage": [
"n/a"
],
"sha256": "a7e1cb939c5003a5aaa28ef5a8391326f95a9f77e8cc529ae5fc56bbc9957f56"
},
"v1.0.1": {
"date": "3-18-2023",
"maturity": "Integrated",
"bus": [
"generic"
],
"type": "soft",
"width": "0",
"height": "0",
"cell_count": "690",
"clock_freq_mhz": "10",
"supply_voltage": [
"n/a"
],
"sha256": "64cee8c74e4fd81b5e8e2a4563c5a326376cbfe4de1deceb2b2f888a33fa15f9"
}
}
},
"MS_CLK_RST": {
"description": "All digital Clock and Reset Manager.",
"repo": "github.com/efabless/MS_CLK_RST",
"author": "Mohamed Shalan",
"email": "[email protected]",
"owner": "Mohamed Shalan",
"category": "digital",
"technology": "sky130A",
"license": "APACHE 2.0",
"tags": [
"clock",
"reset",
"low power",
"frequency scaling"
],
"release": {
"v1.0.0": {
"date": "1-01-2020",
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