diff --git a/lvs/user_project_wrapper/lvs_config.json b/lvs/user_project_wrapper/lvs_config.json
new file mode 100644
index 000000000..65dfe3765
--- /dev/null
+++ b/lvs/user_project_wrapper/lvs_config.json
@@ -0,0 +1,30 @@
+{
+    "TOP_SOURCE": "user_project_wrapper",
+    "TOP_LAYOUT": "$TOP_SOURCE",
+    "EXTRACT_FLATGLOB": [
+        ""
+    ],
+    "EXTRACT_ABSTRACT": [
+        "*__fill_*",
+        "*__fakediode_*",
+        "*__tapvpwrvgnd_*"
+    ],
+    "LVS_FLATTEN": [
+        ""
+    ],
+    "LVS_NOFLATTEN": [
+        ""
+    ],
+    "LVS_IGNORE": [
+        ""
+    ],
+    "LVS_SPICE_FILES": [
+        "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
+        "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+    ],
+    "LVS_VERILOG_FILES": [
+        "$UPRJ_ROOT/verilog/gl/user_proj_example.v",
+        "$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
+    ],
+    "LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
+}
\ No newline at end of file
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
new file mode 100644
index 000000000..087d69edb
--- /dev/null
+++ b/openlane/user_proj_example/config.json
@@ -0,0 +1,29 @@
+{
+	"PDK": "gf180mcuC",
+	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+	"DESIGN_NAME": "user_proj_example",
+	"VERILOG_FILES": [
+		"dir::../../verilog/rtl/defines.v",
+		"dir::../../verilog/rtl/user_proj_example.v"
+	],
+	"DESIGN_IS_CORE": 0,
+	"CLOCK_PORT": "wb_clk_i",
+	"CLOCK_NET": "counter.clk",
+	"CLOCK_PERIOD": "24.0",
+	"FP_SIZING": "absolute",
+	"DIE_AREA": "0 0 900 600",
+	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"PL_BASIC_PLACEMENT": 0,
+	"PL_TARGET_DENSITY": 0.45,
+	"FP_CORE_UTIL": 40,
+	"SYNTH_MAX_FANOUT": 4,
+	"RT_MAX_LAYER": "met4",
+	"VDD_NETS": [
+		"vccd1"
+	],
+	"GND_NETS": [
+		"vssd1"
+	],
+	"DIODE_INSERTION_STRATEGY": 4,
+	"RUN_CVC": 1
+}
\ No newline at end of file
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
deleted file mode 100644
index 48e913c2d..000000000
--- a/openlane/user_proj_example/config.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-set ::env(PDK) "gf180mcuC"
-set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
-
-set ::env(DESIGN_NAME) user_proj_example
-
-set ::env(VERILOG_FILES) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
-
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "24.0"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(PL_BASIC_PLACEMENT) 0
-set ::env(PL_TARGET_DENSITY) 0.45
-
-set ::env(FP_CORE_UTIL) 40
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Maximum layer used for routing is metal 4.
-# This is because this macro will be inserted in a top level (user_project_wrapper) 
-# where the PDN is planned on metal 5. So, to avoid having shorts between routes
-# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
-# 
-set ::env(RT_MAX_LAYER) {Metal4}
-
-# You can draw more power domains if you need to 
-set ::env(VDD_NETS) [list {vdd}]
-set ::env(GND_NETS) [list {vss}]
-
-set ::env(DIODE_INSERTION_STRATEGY) 4 
-# If you're going to use multiple power domains, then disable cvc run.
-set ::env(RUN_CVC) 1
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
new file mode 100644
index 000000000..076fa9c0a
--- /dev/null
+++ b/openlane/user_project_wrapper/config.json
@@ -0,0 +1,63 @@
+{
+	"PDK": "gf180mcuC",
+	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+	"VERILOG_FILES": [
+		"dir::../../verilog/rtl/defines.v",
+		"dir::../../verilog/rtl/user_project_wrapper.v"
+	],
+	"CLOCK_PORT": "user_clock2",
+	"CLOCK_NET": "mprj.clk",
+	"CLOCK_PERIOD": "10",
+	"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
+	"MACRO_PLACEMENT_CFG": "macro.cfg",
+	"VERILOG_FILES_BLACKBOX": [
+		"dir::../../verilog/gl/user_proj_example.v"
+	],
+	"FP_PDN_CHECK_NODES": 0,
+	"SYNTH_ELABORATE_ONLY": 1,
+	"PL_RANDOM_GLB_PLACEMENT": 1,
+	"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
+	"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
+	"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
+	"PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
+	"FP_PDN_ENABLE_RAILS": 0,
+	"DIODE_INSERTION_STRATEGY": 0,
+	"RUN_FILL_INSERTION": 0,
+	"RUN_TAP_DECAP_INSERTION": 0,
+	"CLOCK_TREE_SYNTH": 0,
+	"MAGIC_ZEROIZE_ORIGIN": 0,
+	"FP_SIZING": "absolute",
+	"DIE_AREA": "0 0 2980.2 2980.2",
+	"CORE_AREA": "12 12 2968.2 2968.2",
+	"RUN_CVC": 0,
+	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"UNIT": 2.4,
+	"FP_IO_VEXTEND": "expr::2 * $UNIT",
+	"FP_IO_HEXTEND": "expr::2 * $UNIT",
+	"FP_IO_VLENGTH": "expr::$UNIT",
+	"FP_IO_HLENGTH": "expr::$UNIT",
+	"FP_IO_VTHICKNESS_MULT": 4,
+	"FP_IO_HTHICKNESS_MULT": 4,
+	"FP_PDN_CORE_RING": 1,
+	"FP_PDN_CORE_RING_VWIDTH": 3.1,
+	"FP_PDN_CORE_RING_HWIDTH": 3.1,
+	"FP_PDN_CORE_RING_VOFFSET": 14,
+	"FP_PDN_CORE_RING_HOFFSET": 16,
+	"FP_PDN_CORE_RING_VSPACING": 1.7,
+	"FP_PDN_CORE_RING_HSPACING": 1.7,
+	"FP_PDN_HOFFSET": 5,
+	"FP_PDN_HPITCH_MULT": 1,
+	"FP_PDN_HPITCH": "expr::60 + $FP_PDN_HPITCH_MULT * 30",
+	"FP_PDN_VWIDTH": 3.1,
+	"FP_PDN_HWIDTH": 3.1,
+	"FP_PDN_VSPACING": "expr::5 * $FP_PDN_CORE_RING_VWIDTH",
+	"FP_PDN_HSPACING": 26.9,
+	"VDD_NETS": [
+		"vdd"
+	],
+	"GND_NETS": [
+		"vss"
+	],
+	"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
+	"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def"
+}
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
deleted file mode 100644
index df1916069..000000000
--- a/openlane/user_project_wrapper/config.tcl
+++ /dev/null
@@ -1,83 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Base Configurations. Don't Touch
-# section begin
-
-set ::env(PDK) "gf180mcuC"
-set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
-
-# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
-source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
-
-set ::env(DESIGN_NAME) user_project_wrapper
-#section end
-
-# User Configurations
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
-
-## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
-
-set ::env(CLOCK_PERIOD) "10"
-
-## Internal Macros
-### Macro PDN Connections
-set ::env(FP_PDN_MACRO_HOOKS) "\
-	mprj vdd vss vdd vss"
-
-### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
-
-### Black-box verilog and views
-set ::env(VERILOG_FILES_BLACKBOX) "\
-	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
-
-set ::env(EXTRA_LEFS) "\
-	$::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
-
-set ::env(EXTRA_GDS_FILES) "\
-	$::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
-
-set ::env(RT_MAX_LAYER) {Metal4}
-
-# disable pdn check nodes becuase it hangs with multiple power domains.
-# any issue with pdn connections will be flagged with LVS so it is not a critical check.
-set ::env(FP_PDN_CHECK_NODES) 0
-
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_ELABORATE_ONLY) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-set ::env(FP_PDN_ENABLE_RAILS) 0
-
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(RUN_FILL_INSERTION) 0
-set ::env(RUN_TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
-
-# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
-source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
deleted file mode 100644
index 66a5084e4..000000000
--- a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
+++ /dev/null
@@ -1,28 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
-
-# PDN Horizontal Pitch as mutliples of 30. Horizontal Pitch = 60 + FP_PDN_HPITCH_MULT * 30. 
-# FP_PDN_HPITCH_MULT is an integer. Minimum value is 0.
-set ::env(FP_PDN_HPITCH_MULT) 1
-
-##
-# PDN Vertical Pitch. Can be changed to any value.
-set ::env(FP_PDN_VPITCH) 90
-
-##
-# PDN vertical Offset. Can be changed to any value.
-set ::env(FP_PDN_VOFFSET) 5
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
deleted file mode 100644
index 636e68bb9..000000000
--- a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
+++ /dev/null
@@ -1,59 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# DON'T TOUCH THE FOLLOWING SECTIONS
-
-# This makes sure that the core rings are outside the boundaries
-# of your block.
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-# Area Configurations. DON'T TOUCH.
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2980.2 2980.2"
-set ::env(CORE_AREA) "12 12 2968.2 2968.2"
-
-set ::env(RUN_CVC) 0
-
-# Pin Configurations. DON'T TOUCH
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::unit 2.4
-set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
-set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
-set ::env(FP_IO_VLENGTH) $::unit
-set ::env(FP_IO_HLENGTH) $::unit
-
-set ::env(FP_IO_VTHICKNESS_MULT) 4
-set ::env(FP_IO_HTHICKNESS_MULT) 4
-
-# Power & Pin Configurations. DON'T TOUCH.
-set ::env(FP_PDN_CORE_RING) 1
-set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
-set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
-set ::env(FP_PDN_CORE_RING_VOFFSET) 14
-set ::env(FP_PDN_CORE_RING_HOFFSET) 16
-set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
-set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
-set ::env(FP_PDN_HOFFSET) 5
-set ::env(FP_PDN_HPITCH) [expr 60 + abs(int($::env(FP_PDN_HPITCH_MULT))) * 30]
-
-set ::env(FP_PDN_VWIDTH) 3.1
-set ::env(FP_PDN_HWIDTH) 3.1
-set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
-set ::env(FP_PDN_HSPACING) 26.9
-
-set ::env(VDD_NETS) [list {vdd}]
-set ::env(GND_NETS) [list {vss}]
-set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
\ No newline at end of file