diff --git a/README.md b/README.md index 0c49da161..1e60c5c8b 100644 --- a/README.md +++ b/README.md @@ -7,8 +7,4 @@ ## Please fill in your project documentation in this README.md file -Refer to [README](docs/source/index.rst#section-quickstart) for a quickstart of how to use caravel_user_project - -Refer to [README](docs/source/index.rst) for this sample project documentation. - -Refer to the following [readthedocs](https://caravel-sim-infrastructure.readthedocs.io/en/latest/index.html) for how to add cocotb tests to your project. \ No newline at end of file +Refer to [README](docs/source/index.md) for this sample project documentation. \ No newline at end of file diff --git a/docs/source/_static/.DS_Store b/docs/source/_static/.DS_Store new file mode 100644 index 000000000..5d435a1e2 Binary files /dev/null and b/docs/source/_static/.DS_Store differ diff --git a/docs/source/_static/option1.png b/docs/source/_static/option1.png index a88350b09..045cef447 100644 Binary files a/docs/source/_static/option1.png and b/docs/source/_static/option1.png differ diff --git a/docs/source/_static/option3.png b/docs/source/_static/option3.png index 7e346b36f..ed1ebf7b7 100644 Binary files a/docs/source/_static/option3.png and b/docs/source/_static/option3.png differ diff --git a/docs/source/index.md b/docs/source/index.md new file mode 100644 index 000000000..3ecfa65a9 --- /dev/null +++ b/docs/source/index.md @@ -0,0 +1,308 @@ +# Caravel User Project + +[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![User CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) + +## Table of Contents + +- [Overview](#overview) +- [Quickstart](#quickstart) +- [Caravel Integration](#caravel-integration) + - [Repo Integration](#repo-integration) + - [Verilog Integration](#verilog-integration) + - [GPIO Configuration](#gpio-configuration) + - [Layout Integration](#layout-integration) +- [Running Full Chip Simulation](#running-full-chip-simulation) +- [User Project Wrapper Requirements](#user-project-wrapper-requirements) +- [Hardening the User Project using OpenLane](#hardening-the-user-project-using-openlane) +- [Running Timing Analysis on Existing Projects](#running-timing-analysis-on-existing-projects) +- [Checklist for Open-MPW Submission](#checklist-for-open-mpw-submission) + +## Overview + +This repository contains a sample user project for the [Caravel](https://github.com/efabless/caravel.git) chip user space. It includes a simple counter demonstrating how to use Caravel's utilities such as IO pads, logic analyzer probes, and the Wishbone port. The repository also follows the recommended structure for open-mpw shuttle projects. + +## Prerequisites + +- Docker: [Linux](https://docs.docker.com/desktop/install/linux-install/r) | [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) | [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) | [Mac with M1 Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) +- Python 3.8+ with PIP + +## Quickstart + +### Starting Your Project + +1. Create a new repository based on the [caravel_user_project](https://github.com/efabless/caravel_user_project/) template. Ensure your repo is public and includes a README. + + - Follow [this link](https://github.com/efabless/caravel_user_project/generate) to create your repository. + - Clone the repository using: + + ```bash + git clone + ``` + +2. Set up your local environment: + + ```bash + cd + make setup + ``` + + This command installs: + + - caravel_lite + - Management core for simulation + - OpenLane for design hardening + - PDK + - Timing scripts + +3. Start hardening your design: + + - For hardening, provide an RTL Verilog model of your design to OpenLane. + - Create a subdirectory for each macro in your project under the `openlane/` directory with OpenLane configuration files. + + ```bash + make + ``` + + Refer to [Hardening the User Project using OpenLane](#hardening-the-user-project-using-openlane) for examples. + +4. Integrate modules into the user_project_wrapper: + + - Update environment variables `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS`, and `EXTRA_GDS_FILES` in `openlane/user_project_wrapper/config.tcl` to point to your module. + - Instantiate your module(s) in `verilog/rtl/user_project_wrapper.v`. + - Harden the user_project_wrapper with your module(s): + + ```bash + make user_project_wrapper + ``` + +5. Run cocotb simulation on your design: + + - Update `rtl/gl/gl+sdf` files in `verilog/includes/includes..caravel_user_project`. + - Run `gen_gpio_defaults.py` script to generate `caravel_core.v`. + - Run RTL tests: + + ```bash + make cocotb-verify-all-rtl + ``` + + - For GL simulation: + + ```bash + make cocotb-verify-all-gl + ``` + + - To add cocotb tests, refer to [Adding cocotb test](https://caravel-sim-infrastructure.readthedocs.io/en/latest/usage.html#adding-a-test). + +6. Run opensta on your design: + + - Extract parasitics for `user_project_wrapper` and its macros: + + ```bash + make extract-parasitics + ``` + + - Create a spef mapping file: + + ```bash + make create-spef-mapping + ``` + + - Run opensta: + + ```bash + make caravel-sta + ``` + + > [!NOTE] + > To update timing scripts, run `make setup-timing-scripts`. + +7. Run the precheck locally: + + ```bash + make precheck + make run-precheck + ``` + +8. You're done! Submit your project at [Efabless Open Shuttle Program](https://efabless.com/open_shuttle_program/). + +### GPIO Configuration + +Specify the power-on default configuration for each GPIO in Caravel in `verilog/rtl/user_defines.v`. GPIO[5] to GPIO[37] require configuration, while GPIO[0] to GPIO[4] are preset and cannot be changed. + +### Layout Integration + +The Caravel layout includes an empty golden wrapper in the user space. Provide a valid `user_project_wrapper` GDS file. Your hardened `user_project_wrapper` will be integrated into the Caravel layout during tapeout. + +![Layout](./_static/layout.png) + +Ensure your hardened `user_project_wrapper` meets the requirements in [User Project Wrapper Requirements](#user-project-wrapper-requirements). + +### Running Full Chip Simulation + +Refer to [ReadTheDocs](https://caravel-sim-infrastructure.readthedocs.io/en/latest/index.html) for adding cocotb tests. + +1. Install the simulation environment: + + ```bash + make setup-cocotb + ``` + +2. Run RTL simulation: + + ```bash + make cocotb-verify--rtl + ``` + +3. After physical implementation, run full gate-level simulations to verify your design. + + ```bash + make cocotb-verify--gl + ``` + +## User Project Wrapper Requirements + +Your hardened `user_project_wrapper` must match the [golden user_project_wrapper](https://github.com/efabless/caravel/blob/master/gds/user_project_wrapper_empty.gds.gz) in: + +- Area (2.920um x 3.520um) +- Top module name "user_project_wrapper" +- Pin Placement +- Pin Sizes +- Core Rings Width and Offset +- PDN Vertical and Horizontal Straps Width + +![Empty](./_static/empty.png) + +You can change the PDN Vertical and Horizontal Pitch & Offset. + +![Pitch](./_static/pitch.png) + +We run an XOR check between your hardened `user_project_wrapper` GDS and the golden wrapper GDS as part of the [mpw-precheck](https://github.com/efabless/mpw_precheck) tool. + +## Hardening the User Project using OpenLane + +### OpenLane Installation + +Install OpenLane with: + +```bash +make openlane +``` + +For more detailed instructions, refer to the [ReadTheDocs](https://openlane.readthedocs.io/en/latest/getting_started/index.html). + +### Hardening Options + +There are three options for hardening the user project macro using OpenLane: + +1. **Option 1**: Harden the user macro(s) first, then insert it into the user project wrapper with no standard cells at the top level. + + ![Option 1](./_static/option1.png) + + Example: [caravel_user_project](https://github.com/efabless/caravel_user_project) + +2. **Option 2**: Flatten the user macro(s) with the user_project_wrapper. + + ![Option 2](./_static/option2.png) + +3. **Option 3**: Place multiple macros in the wrapper along with standard cells at the top level. + + ![Option 3](./_static/option3.png) + + Example: [clear](https://github.com/efabless/clear) + +For more details, refer to the [Knowledgebase article](https://info.efabless.com/knowledge-base/top-level-integration-and-power-management). + +### Running OpenLane + +For this project, we chose the first option: harden the user macro first, then insert it into the user project wrapper without standard cells at the top level. + +![Wrapper](./_static/wrapper.png) + +To reproduce this process, run: + +```bash +# DO NOT cd into openlane + +# Harden user_proj_example +make user_proj_example + +# Harden user_project_wrapper +make user_project_wrapper +``` + +For more information, refer to the [OpenLane Documentation](https://openlane.readthedocs.io/en/latest/index.html). + +## Running Transistor Level LVS + +To pass precheck, a custom LVS configuration file (`lvs_config.json`) is needed for your design. The configuration file should include: + +Required variables: + +- **TOP_SOURCE**: Top source cell name. +- **TOP_LAYOUT**: Top layout cell name. +- **LAYOUT_FILE**: Layout GDS data file. +- **LVS_SPICE_FILES**: List of spice files. +- **LVS_VERILOG_FILES**: List of Verilog files (child modules should be listed before parent modules). + +Optional variables: + +- **INCLUDE_CONFIGS**: List of configuration files to read recursively. +- **EXTRACT_FLATGLOB**: List of cell names to flatten before extraction. +- **EXTRACT_ABSTRACT**: List of cells to extract as abstract devices. +- **LVS_FLATTEN**: List of cells to flatten before comparing. +- **LVS_NOFLATTEN**: List of cells not to flatten in case of a mismatch. +- **LVS_IGNORE**: List of cells to ignore during LVS. + +> [!NOTE] +> Missing files and undefined variables result in fatal errors. + +## Running MPW Precheck Locally + +Install the [mpw-precheck](https://github.com/efabless/mpw_precheck) by running: + +```bash +make precheck +``` + +Run the precheck with: + +```bash +make run-precheck +``` + +To disable LVS/Soft/ERC connection checks: + +```bash +DISABLE_LVS=1 make run-precheck +``` + +## Running Timing Analysis on Existing Projects + +Update the Makefile for your project: + +```bash +make setup-timing-scripts +``` + +Run timing analysis: + +```bash +make extract-parasitics + +make create-spef-mapping + +make caravel-sta +``` + +A summary of timing results is provided at the end. + +## Checklist for Shuttle Submission + +- ✔️ The project repo follows the directory structure in this repo. +- ✔️ Top level macro is named `user_project_wrapper`. +- ✔️ Full Chip Simulation passes for RTL and GL. +- ✔️ Hardened Macros are LVS and DRC clean. +- ✔️ Contains a gate-level netlist for `user_project_wrapper` at `verilog/gl/user_project_wrapper.v`. +- ✔️ Hardened `user_project_wrapper` matches the [pin order](https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg). +- ✔️ Matches the [fixed wrapper configuration](https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl). +- ✔️ Design passes the [mpw-precheck](https://github.com/efabless/mpw_precheck). diff --git a/docs/source/index.rst b/docs/source/index.rst deleted file mode 100644 index bb272cbbc..000000000 --- a/docs/source/index.rst +++ /dev/null @@ -1,672 +0,0 @@ -.. raw:: html - - - -Caravel User Project -==================== - -|License| |User CI| |Caravel Build| - -Table of contents -================= - -- `Overview <#overview>`__ -- `Quickstart <#quickstart>`__ -- `Caravel Integration <#caravel-integration>`__ - - - `Repo Integration <#repo-integration>`__ - - `Verilog Integration <#verilog-integration>`__ - - `GPIO Configuration <#gpio-configuration>`__ - - `Layout Integration <#layout-integration>`__ - -- `Running Full Chip Simulation <#running-full-chip-simulation>`__ -- `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ -- `Hardening the User Project using - Openlane <#hardening-the-user-project-using-openlane>`__ -- `Running Timing Analysis on Existing Projects <#running-timing-analysis-on-existing-projects>`__ -- `Checklist for Open-MPW - Submission <#checklist-for-open-mpw-submission>`__ - -Overview -======== - -This repo contains a sample user project that utilizes the -`caravel `__ chip user space. -The user project is a simple counter that showcases how to make use of -`caravel's `__ user space -utilities like IO pads, logic analyzer probes, and wishbone port. The -repo also demonstrates the recommended structure for the open-mpw -shuttle projects. - -Prerequisites -============= - -- Docker: `Linux `_ || `Windows `_ || `Mac with Intel Chip `_ || `Mac with M1 Chip `_ - -- Python 3.6+ with PIP - - -Quickstart -=========== - ---------------------- -Starting your project ---------------------- - -#. To start the project you first need to create a new repository based on the `caravel_user_project `_ template and make sure your repo is public and includes a README. - - * Follow https://github.com/efabless/caravel_user_project/generate to create a new repository. - * Clone the reposity using the following command: - - .. code:: bash - - git clone - -#. To setup your local environment run: - - .. code:: bash - - cd # project_name is the name of your repo - - # export the PDK variant depending on your shuttle, if you don't know leave it to the default - - # for sky130 MPW shuttles.... - export PDK=sky130A - - # for the gf180 GFMPW shuttles... - export PDK=gf180mcuC - - - - make setup - -* This command will setup your environment by installing the following - - - caravel_lite (a lite version of caravel) - - management core for simulation - - openlane to harden your design - - pdk - - -#. Now you can start hardening your design - - * To start hardening you project you need - - RTL verilog model for your design for OpenLane to harden - - A subdirectory for each macro in your project under ``openlane/`` directory, each subdirectory should include openlane configuration files for the macro - - .. code:: bash - - make - .. - - For an example of hardening a project please refer to `Hardening the User Project using OpenLane`_. . - -#. Integrate modules into the user_project_wrapper - - * Change the environment variables ``VERILOG_FILES_BLACKBOX``, ``EXTRA_LEFS`` and ``EXTRA_GDS_FILES`` in ``openlane/user_project_wrapper/config.tcl`` to point to your module - * Instantiate your module(s) in ``verilog/rtl/user_project_wrapper.v`` - * Harden the user_project_wrapper including your module(s), using this command: - - .. code:: bash - - make user_project_wrapper - -#. Run simulation on your design - - * You need to include your rtl/gl/gl+sdf files in ``verilog/includes/includes..caravel_user_project`` - - **NOTE:** You shouldn't include the files inside the verilog code - - .. code:: bash - - # you can then run RTL simulations using - make verify--rtl - - # OR GL simulation using - make verify--gl - - # OR for GL+SDF simulation using - # sdf annotated simulation is slow - make verify--gl-sdf - - # for example - make verify-io_ports-rtl - -#. Run cocotb simulation on your design - - * rtl/gl/gl+sdf files in ``verilog/includes/includes..caravel_user_project`` should be updated - * To run GL simulation script ``/scripts/gen_gpio_defaults.py`` should be run to generate ``caravel_core.v`` - - * To make sure the cocotb flow works, run the following commands for testing the counter example - - .. code:: bash - # To run all tests in user_project_tests list found at ``verilog/dv/cocotb/user_project_tests/user_project_tests.yaml`` - # RTL tests - make cocotb-verify-all-rtl - # OR GL simulation using - make cocotb-verify-all-gl - # To run any test under ``verilog/dv/cocotb/*`` - # RTL - make cocotb-verify--rtl - # GL - make cocotb-verify--gl - * To run cocotb tests on your design, Follow the steps below - * Add cocotb tests under ``verilog/dv/cocotb`` follow steps at `Adding_cocotb_test `_ - * Run cocotb tests using ``caravel_cocotb`` command steps at `Running_cocotb_tests `_ - -#. Run opensta on your design - - * Extract spefs for ``user_project_wrapper`` and macros inside it: - - .. code:: bash - - make extract-parasitics - - * Create spef mapping file that maps instance names to spef files: - - .. code:: bash - - make create-spef-mapping - - * Run opensta: - - .. code:: bash - - make caravel-sta - - **NOTE:** To update timing scripts run ``make setup-timing-scripts`` - -#. Run standalone LVS - - .. code:: bash - - make lvs- # macro is the name of the macro you want to run LVS on - - **NOTE:** You have to create a new config file for each macro under ``lvs//lvs_config.json`` - -#. Run the precheck locally - - .. code:: bash - - make precheck - make run-precheck - -#. You are done! now go to https://efabless.com/open_shuttle_program/ to submit your project! - - -Caravel Integration -=================== - ----------------- -Repo Integration ----------------- - -Caravel files are kept separate from the user project by having caravel -as submodule. The submodule commit should point to the latest of -caravel/caravel-lite master/main branch. The following files should have a symbolic -link to `caravel's `__ -corresponding files: - -- `Openlane Makefile <../../openlane/Makefile>`__: This provides an easier - way for running openlane to harden your macros. Refer to `Hardening - the User Project Macro using - Openlane <#hardening-the-user-project-using-openlane>`__. Also, - the makefile retains the openlane summary reports under the signoff - directory. - -- `Pin order <../../openlane/user_project_wrapper/pin_order.cfg>`__ file for - the user wrapper: The hardened user project wrapper macro must have - the same pin order specified in caravel's repo. Failing to adhere to - the same order will fail the gds integration of the macro with - caravel's back-end. - -The symbolic links are automatically set when you run ``make install``. - -------------------- -Verilog Integration -------------------- - -You need to create a wrapper around your macro that adheres to the -template at -`user\_project\_wrapper `__. -The wrapper top module must be named ``user_project_wrapper`` and must -have the same input and output ports as the golden wrapper `template `__. The wrapper gives access to the -user space utilities provided by caravel like IO ports, logic analyzer -probes, and wishbone bus connection to the management SoC. - -For this sample project, the user macro makes use of: - -- The IO ports for displaying the count register values on the IO pads. - -- The LA probes for supplying an optional reset and clock signals and - for setting an initial value for the count register. - -- The wishbone port for reading/writing the count value through the - management SoC. - -Refer to `user\_project\_wrapper <../../verilog/rtl/user_project_wrapper.v>`__ -for more information. - -.. raw:: html - -

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- -------------------- -GPIO Configuration -------------------- - -You are required to specify the power-on default configuration for each GPIO in Caravel. The default configuration provide the state the GPIO will come up on power up. The configuration can be changed by the management SoC during firmware execution. - -Configuration settings define whether the GPIO is configured to connect to the user project area or the managment SoC. They also determine whether IOs are inputs or outputs, digital or analog, as well as whether pull-up or pull-down resistors are configured for inputs. - -GPIOs are configured by assigning predefined values for each IO in the file `verilog/rtl/user_defines.v `_ in your project. - -You need to assigned configuration values for GPIO[5] thru GPIO[37]. - -GPIO[0] thru GPIO[4] are preset and cannot be changed. - -The following values are redefined for assigning to GPIOs. - - -- GPIO_MODE_MGMT_STD_INPUT_NOPULL -- GPIO_MODE_MGMT_STD_INPUT_PULLDOWN -- GPIO_MODE_MGMT_STD_INPUT_PULLUP -- GPIO_MODE_MGMT_STD_OUTPUT -- GPIO_MODE_MGMT_STD_BIDIRECTIONAL -- GPIO_MODE_MGMT_STD_ANALOG - -- GPIO_MODE_USER_STD_INPUT_NOPULL -- GPIO_MODE_USER_STD_INPUT_PULLDOWN -- GPIO_MODE_USER_STD_INPUT_PULLUP -- GPIO_MODE_USER_STD_OUTPUT -- GPIO_MODE_USER_STD_BIDIRECTIONAL -- GPIO_MODE_USER_STD_OUT_MONITORED -- GPIO_MODE_USER_STD_ANALOG - - -MPW_Prececk includes a check to confirm each GPIO is assigned a valid value. - -------------------- -Layout Integration -------------------- - -The caravel layout is pre-designed with an empty golden wrapper in the user space. You only need to provide us with a valid ``user_project_wrapper`` GDS file. And, as part of the tapeout process, your hardened ``user_project_wrapper`` will be inserted into a vanilla caravel layout to get the final layout shipped for fabrication. - -.. raw:: html - -

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- -To make sure that this integration process goes smoothly without having any DRC or LVS issues, your hardened ``user_project_wrapper`` must adhere to a number of requirements listed at `User Project Wrapper Requirements <#user-project-wrapper-requirements>`__ . - - -Running Full Chip Simulation -============================ - -First, you will need to install the simulation environment, by - -.. code:: bash - - make simenv - -This will pull a docker image with the needed tools installed. - -Then, run the RTL simulation by - -.. code:: bash - - export PDK_ROOT= - make verify--rtl - - # For example - make verify-io_ports-rtl - -Once you have the physical implementation done and you have the gate-level netlists ready, it is crucial to run full gate-level simulations to make sure that your design works as intended after running the physical implementation. - -Run the gate-level simulation by: - -.. code:: bash - - export PDK_ROOT= - make verify--gl - - # For example - make verify-io_ports-gl - -To make sure that your design is timing clean, one way is running sdf annotated gate-level simulation -Run the sdf annotated gate-level simulation by: - -.. code:: bash - - export PDK_ROOT= - make verify--gl-sdf - - # For example - make verify-io_ports-gl-sdf - -This sample project comes with four example testbenches to test the IO port connection, wishbone interface, and logic analyzer. The test-benches are under the -`verilog/dv `__ directory. For more information on setting up the -simulation environment and the available testbenches for this sample -project, refer to `README `__. - - -User Project Wrapper Requirements -================================= - -Your hardened ``user_project_wrapper`` must match the `golden user_project_wrapper `__ in the following: - -- Area ``(2.920um x 3.520um)`` -- Top module name ``"user_project_wrapper"`` -- Pin Placement -- Pin Sizes -- Core Rings Width and Offset -- PDN Vertical and Horizontal Straps Width - - -.. raw:: html - -

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- -You are allowed to change the following if you need to: - -- PDN Vertical and Horizontal Pitch & Offset - -.. raw:: html - -

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- -To make sure that you adhere to these requirements, we run an exclusive-or (XOR) check between your hardened ``user_project_wrapper`` GDS and the golden wrapper GDS after processing both layouts to include only the boundary (pins and core rings). This check is done as part of the `mpw-precheck `__ tool. - - -Hardening the User Project using OpenLane -========================================== - ---------------------- -OpenLane Installation ---------------------- - -You will need to install openlane by running the following - -.. code:: bash - - export OPENLANE_ROOT= - - # you can optionally specify the openlane tag to use - # by running: export OPENLANE_TAG= - # if you do not set the tag, it defaults to the last verfied tag tested for this project - - make openlane - -For detailed instructions on the openlane and the pdk installation refer -to -`README `__. - ------------------ -Hardening Options ------------------ - -There are three options for hardening the user project macro using -openlane: - -+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+ -| Option 1 | Option 2 | Option 3 | -+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+ -| Hardening the user macro(s) first, then inserting it in the | Flattening the user macro(s) with the | Placing multiple macros in the wrapper | -| user project wrapper with no standard cells on the top level | user_project_wrapper | along with standard cells on the top level | -+==============================================================+============================================+============================================+ -| |pic1| | |pic2| | |pic3| | -| | | | -+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+ -| ex: |link1| | | ex: |link2| | -+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+ - -.. |link1| replace:: `caravel_user_project `__ - -.. |link2| replace:: `caravel_ibex `__ - - -.. |pic1| image:: ./_static/option1.png - :width: 48% - -.. |pic2| image:: ./_static/option2.png - :width: 140% - -.. |pic3| image:: ./_static/option3.png - :width: 72% - -For more details on hardening macros using openlane, refer to `README `__. - ------------------ -Running OpenLane ------------------ - -For this sample project, we went for the first option where the user -macro is hardened first, then it is inserted in the user project -wrapper without having any standard cells on the top level. - -.. raw:: html - -

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- -To reproduce hardening this project, run the following: - -.. code:: bash - - # DO NOT cd into openlane - - # Run openlane to harden user_proj_example - make user_proj_example - # Run openlane to harden user_project_wrapper - make user_project_wrapper - - -For more information on the openlane flow, check `README `__. - -Runing transistor level LVS -============================ - -For the design to pass precheck, a custom lvs configuration file for your design is needed, config file can be found under `lvs//lvs_config.json` - -The `lvs_config.json` files are a possibly hierarchical set of files to set parameters for device level LVS - -Required variables: -- **TOP_SOURCE** : Top source cell name. -- **TOP_LAYOUT** : Top layout cell name. -- **LAYOUT_FILE** : Layout gds data file. -- **LVS_SPICE_FILES** : A list of spice files. -- **LVS_VERILOG_FILES** : A list of verilog files. Note: files with child modules should be listed before parent modules. Not needed for purely analog designs. - -Files must be defined as a absolute path beginning with a shell variable such as `$PDK_ROOT` or `$UPRJ_ROOT`. - -Optional variable lists: -Hierarchical config files: -- **INCLUDE_CONFIGS** : List of configuration files to read recursively. - -Extraction related. `*` may be used as a wild card character. -- **EXTRACT_FLATGLOB** : List of cell names to flatten before extraction. - Cells without text tend to work better if flattened. - Note: it is necessary to flatten all sub cells of any cells listed. -- **EXTRACT_ABSTRACT** : List of cells to extract as abstract devices. - Normally, cells that do not contain any devices will be flattened during netlisting. - Using this variable can prevent unwanted flattening of empty cells. - This has no effect of cells that are flattened because of a small number of layers. - Internal connectivity is maintained (at least at the top level). - -LVS related. `*` may be used as a wild card character. -- **LVS_FLATTEN** : List of cells to flatten before comparing, - Sometimes matching topologies with mismatched pins cause errors at a higher level. - Flattening these cells can yield a match. -- **LVS_NOFLATTEN** : List of cells not to be flattened in case of a mismatch. - Lower level errors can propagate to the top of the chip resulting in long run times. - Specify cells here to prevent flattening. May still cause higher level problems if there are pin mismatches. -- **LVS_IGNORE** : List of cells to ignore during LVS. - Cells ignored result in LVS ending with a warning. - Generally, should only be used when debugging and not on the final netlist. - Ignoring cells results in a non-zero return code. - -**NOTE**: Missing files and undefined variables result in fatal errors. - -Running MPW Precheck Locally -================================= - -You can install the `mpw-precheck `__ by running - -.. code:: bash - - # By default, this install the precheck in your home directory - # To change the installtion path, run "export PRECHECK_ROOT=" - make precheck - -This will clone the precheck repo and pull the latest precheck docker image. - - -Then, you can run the precheck by running - -.. code:: bash - - make run-precheck - -This will run all the precheck checks on your project and will produce the logs under the ``checks`` directory. - -To disable running LVS/Soft/ERC connection checks: - -.. code:: bash - - DISABLE_LVS=1 make run-precheck - -Running Timing Analysis on Existing Projects -======================================================== - -Start by updating the Makefile for your project. Starting in the project root... - -.. code:: bash - - curl -k https://raw.githubusercontent.com/efabless/caravel_user_project/main/Makefile > Makefile - - make setup-timing-scripts - - make install - - make install_mcw - - -This will update Caravel design files and install the scripts for running timing. - - -Then, you can run then run timing by the following... - -.. code:: bash - - make extract-parasitics - - make create-spef-mapping - - make caravel-sta - - -A summary of timing results is provided at the end of the flow. - - -Other Miscellaneous Targets -============================ - -The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane's flow. - -Run ``make help`` to display available targets. - -Run lvs on the mag view, - -.. code:: bash - - make lvs- - -Run lvs on the gds, - -.. code:: bash - - make lvs-gds- - -Run lvs on the maglef, - -.. code:: bash - - make lvs-maglef- - -Run drc using magic, - -.. code:: bash - - make drc- - -Run antenna check using magic, - -.. code:: bash - - make antenna- - -Run XOR check, - -.. code:: bash - - make xor-wrapper - - - - -Checklist for Open-MPW Submission -================================= - -- ✔️ The project repo adheres to the same directory structure in this - repo. -- ✔️ The project repo contain info.yaml at the project root. -- ✔️ Top level macro is named ``user_project_wrapper``. -- ✔️ Full Chip Simulation passes for RTL and GL (gate-level) -- ✔️ The hardened Macros are LVS and DRC clean -- ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v -- ✔️ The hardened ``user_project_wrapper`` adheres to the same pin - order specified at - `pin\_order `__ -- ✔️ The hardened ``user_project_wrapper`` adheres to the fixed wrapper configuration specified at `fixed_wrapper_cfgs `__ -- ✔️ XOR check passes with zero total difference. -- ✔️ Openlane summary reports are retained under ./signoff/ -- ✔️ The design passes the `mpw-precheck `__ - -.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg - :target: https://opensource.org/licenses/Apache-2.0 -.. |User CI| image:: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg - :target: https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml -.. |Caravel Build| image:: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg - :target: https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml