fix bug in rtl (appears when using Ofast)

efabless · Nov 27, 2024 · 9bbd713 · 9bbd713
1 parent bf0455e
commit 9bbd713
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Showing 2 changed files with 19 additions and 5 deletions.
diff --git a/EF_PSRAM_CTRL_V2.yaml b/EF_PSRAM_CTRL_V2.yaml
@@ -7,8 +7,8 @@ info:
   license: Apache 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.7
-  date: 16-09-2024
+  version: v1.0.8
+  date: 27-11-2024
   category: digital
   tags:
     - memory

diff --git a/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_V2_ahbl.v b/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_V2_ahbl.v
@@ -70,7 +70,8 @@ module EF_PSRAM_CTRL_V2_ahbl #(parameter REGISTER_HWDATA = 1)
                         (last_HSIZE == 1) ? 2 :
                         (last_HSIZE == 2) ? 4 : 4;
 
-    wire        data_cfg        =   ~HADDR[23];
+    // wire        data_cfg        =   ~HADDR[23];
+    reg data_cfg;
     wire        last_data_cfg   =   ~last_HADDR[23];
     wire        control         =   HADDR[22];
     wire        ahb_addr_phase  =   HTRANS[1] & HSEL & HREADY;
@@ -163,17 +164,24 @@ module EF_PSRAM_CTRL_V2_ahbl #(parameter REGISTER_HWDATA = 1)
             last_HADDR      <= 0;
             last_HWRITE     <= 0;
             last_HTRANS     <= 0;
-            last_HSIZE      <= 0;
+            // last_HSIZE      <= 0;
         end
         else if(HREADY) begin
             last_HSEL       <= HSEL;
             last_HADDR      <= HADDR;
             last_HWRITE     <= HWRITE;
             last_HTRANS     <= HTRANS;
-            last_HSIZE      <= HSIZE;
+            // last_HSIZE      <= HSIZE;
         end
     end
 
+    always@(posedge HCLK or negedge HRESETn) begin 
+        if(!HRESETn) 
+            last_HSIZE <= 0;
+        else if (HTRANS[1])
+                last_HSIZE<=HSIZE;
+    end
+
     // Configuration Interface
     reg [7:0]   RD_CMD_REG;
     reg [7:0]   WR_CMD_REG;
@@ -285,6 +293,12 @@ module EF_PSRAM_CTRL_V2_ahbl #(parameter REGISTER_HWDATA = 1)
 
             assign  start   =   ( last_ahb_addr_phase & (state == ST_IDLE ) & data_cfg );
 
+        always@(posedge HCLK or negedge HRESETn)
+        if(!HRESETn)
+            data_cfg <= 0;
+        else if (ahb_addr_phase)
+            data_cfg <= ~HADDR[23];
+
         //end 
         //else begin
         /*