{"payload":{"header_redesign_enabled":false,"results":[{"id":"86497447","archived":false,"color":"#b2b7f8","followers":230,"has_funding_file":false,"hl_name":"dpretet/async_fifo","hl_trunc_description":"A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":86497447,"name":"async_fifo","owner_id":2131563,"owner_login":"dpretet","updated_at":"2024-04-30T04:54:43.690Z","has_issues":true}},"sponsorable":true,"topics":["asic","fpga","async","verification","verilog","synthesis","icarus-verilog","fifo","cdc","hdl","verilog-hdl","fifo-queue","fifo-cache","verilator","asic-design","cross-clock-domain"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":85,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Adpretet%252Fasync_fifo%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/dpretet/async_fifo/star":{"post":"FMelTqh8CJ24vWdfp06RAgyvJMHOfuVatVC41btyzuqnSPEAjTZMszbI-SdNqeP6mCR5wPClLpqqmHuFPzXAeA"},"/dpretet/async_fifo/unstar":{"post":"Uq8yrP8bmouPxED6vZrVPIttWLPDSJzBHHhlXCShf9kj7X76T1dhwszwYQT5Wa_kmGvUzFW5X1B-IxCZlzqv0w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"EaQoiTeOif5YfjnsPsfi09hOx4wG5Jx5EMG3qR3EjnCrFHAg6RyjXieU3GCqzzrAuhyuXwjvu4kX2kGZKOTeDQ"}}},"title":"Repository search results"}