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cpucore_z80.cpp
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cpucore_z80.cpp
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// -----------------------------------------------------------------------------
// Altair 8800 Simulator
// Copyright (C) 2018 David Hansel
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
// -----------------------------------------------------------------------------
#include "cpucore.h"
#include "timer.h"
#include "mem.h"
#include "numsys.h"
#include "disassembler.h"
#include "Altair8800.h"
#if USE_Z80 != 0
// additional Z80 status flags
// (proper PS_UNUSED flag handling is necessary to pass the "zexall" test)
#define PS_ADDSUB 0x02
#define PS_UNUSED08 0x08
#define PS_OVERFLOW PS_PARITY
#define PS_UNUSED20 0x20
#define PS_UNUSED (PS_UNUSED08 | PS_UNUSED20)
extern union unionIXY
{
struct { byte L, H; };
uint16_t HL;
} regIX, regIY;
// additional Z80 registers
union unionAF regAF_;
union unionBC regBC_;
union unionDE regDE_;
union unionHL regHL_;
union unionIXY regIX, regIY;
byte regRL, regRH, regI;
byte *registers[8] = {®B, ®C, ®D, ®E, ®H, ®L, NULL, ®A };
uint16_t *registers_wide[4] = {®BC.BC, ®DE.DE, ®HL.HL, ®SP};
#define setCarryBit(v) if(v) regS |= PS_CARRY; else regS &= ~PS_CARRY
static const byte parity_table[256] =
{1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1};
inline uint16_t MEM_READ_WORD(uint16_t addr)
{
if( host_read_status_led_WAIT() )
{
byte l, h;
l = MEM_READ_STEP(addr);
addr++;
h = MEM_READ_STEP(addr);
return l | (h * 256);
}
else
{
byte l, h;
#if USE_REAL_MREAD_TIMING>0
l = MEM_READ(addr);
for(uint8_t i=0; i<5; i++) asm("NOP");
addr++;
h = MEM_READ(addr);
#else
host_set_status_leds_READMEM();
host_set_addr_leds(addr);
l = MREAD(addr);
host_set_data_leds(l);
for(uint8_t i=0; i<5; i++) asm("NOP");
addr++;
host_set_addr_leds(addr);
h = MREAD(addr);
host_set_data_leds(h);
#endif
return l | (h * 256);
}
}
inline void MEM_WRITE_WORD(uint16_t addr, uint16_t v)
{
if( host_read_status_led_WAIT() )
{
MEM_WRITE_STEP(addr, v & 255);
addr++;
MEM_WRITE_STEP(addr, v / 256);
}
else
{
byte b;
#if SHOW_MWRITE_OUTPUT>0
b = v & 255;
MEM_WRITE(addr, b);
for(uint8_t i=0; i<5; i++) asm("NOP");
b = v / 256;
addr++;
MEM_WRITE(addr, b);
#else
host_set_status_leds_WRITEMEM();
host_set_data_leds(0xff);
host_set_addr_leds(addr);
b = v & 255;
MWRITE(addr, b);
for(uint8_t i=0; i<5; i++) asm("NOP");
addr++;
host_set_addr_leds(addr);
b = v / 256;
MWRITE(addr, b);
#endif
}
}
static void pushStackSlow(byte valueH, byte valueL)
{
if( altair_isreset() )
{
host_set_status_led_STACK();
regSP--;
MEM_WRITE_STEP(regSP, valueH);
if( altair_isreset() )
{
regSP--;
MEM_WRITE_STEP(regSP, valueL);
}
host_clr_status_led_STACK();
}
}
static void popStackSlow(byte *valueH, byte *valueL)
{
if( altair_isreset() )
{
host_set_status_led_STACK();
*valueL = MEM_READ_STEP(regSP);
if( altair_isreset() )
{
regSP++;
*valueH = MEM_READ_STEP(regSP);
if( altair_isreset() ) regSP++;
}
host_clr_status_led_STACK();
}
}
#if SHOW_MWRITE_OUTPUT>0
#define pushStack(valueH, valueL) \
if( !host_read_status_led_WAIT() ) \
{ \
host_set_status_led_STACK(); \
regSP--; \
MEM_WRITE(regSP, valueH); \
regSP--; \
MEM_WRITE(regSP, valueL); \
host_clr_status_led_STACK(); \
} \
else pushStackSlow(valueH, valueL);
#else
#define pushStack(valueH, valueL) \
if( !host_read_status_led_WAIT() ) \
{ \
host_set_status_led_STACK(); \
host_set_status_leds_WRITEMEM(); \
regSP--; \
host_set_addr_leds(regSP); \
MWRITE(regSP, valueH); \
regSP--; \
host_set_addr_leds(regSP); \
MWRITE(regSP, valueL); \
host_clr_status_led_STACK(); \
} \
else pushStackSlow(valueH, valueL);
#endif
#if USE_REAL_MREAD_TIMING>0
#define popStack(valueH, valueL) \
if( !host_read_status_led_WAIT() ) \
{ \
host_set_status_led_STACK(); \
valueL = MEM_READ(regSP); \
regSP++; \
valueH = MEM_READ(regSP); \
regSP++; \
host_clr_status_led_STACK(); \
} \
else popStackSlow(&valueH, &valueL);
#else
#define popStack(valueH, valueL) \
if( !host_read_status_led_WAIT() ) \
{ \
host_set_status_leds_READMEM_STACK(); \
host_set_addr_leds(regSP); \
valueL = MREAD(regSP); \
regSP++; \
host_set_addr_leds(regSP); \
valueH = host_set_data_leds(MREAD(regSP)); \
regSP++; \
host_clr_status_led_STACK(); \
} \
else popStackSlow(&valueH, &valueL);
#endif
inline void pushStackWord(uint16_t v)
{
host_set_status_led_STACK();
regSP -= 2;
MEM_WRITE_WORD(regSP, v);
host_clr_status_led_STACK();
}
inline uint16_t popStackWord()
{
uint16_t v;
host_set_status_led_STACK();
v = MEM_READ_WORD(regSP);
regSP += 2;
host_clr_status_led_STACK();
return v;
}
#define pushPC() pushStack(regPCU.H, regPCU.L)
#define popPC() regPC = popStackWord()
inline void setStatusBitsLogic(byte value, byte f)
{
regS = (value & (PS_SIGN|PS_UNUSED)) | f;
if( value==0 ) regS |= PS_ZERO;
if( parity_table[value] ) regS |= PS_PARITY;
}
inline byte inc(byte n)
{
n++;
regS = (regS & PS_CARRY) | (n & (PS_SIGN|PS_UNUSED));
if( n == 0x00 ) regS |= PS_ZERO;
if( (n&0x0F)==0 ) regS |= PS_HALFCARRY;
if( n == 0x80 ) regS |= PS_OVERFLOW;
return n;
}
inline byte dec(byte n)
{
n--;
regS = (regS & PS_CARRY) | (n & (PS_SIGN|PS_UNUSED)) | PS_ADDSUB;
if( n == 0x00 ) regS |= PS_ZERO;
if( (n&0x0F)==0x0F ) regS |= PS_HALFCARRY;
if( n == 0x7F ) regS |= PS_OVERFLOW;
return n;
}
inline byte add(byte opd1, byte opd2, byte c)
{
byte res;
uint16_t w = opd1 + opd2 + c;
uint16_t b = opd1 ^ opd2 ^ w;
res = (byte) w;
regS = (w & (PS_SIGN|PS_UNUSED)) | (b & PS_HALFCARRY);
if( res == 0 ) regS |= PS_ZERO;
if( w&0x100 ) regS |= PS_CARRY;
if( (((b >> 1) ^ b) & 0x80) ) regS |= PS_OVERFLOW;
return res;
}
inline byte sub(byte opd1, byte opd2, byte c)
{
byte res;
uint16_t w = opd1 - opd2 - c;
uint16_t b = opd1 ^ opd2 ^ w;
res = (byte) w;
regS = (w & (PS_SIGN|PS_UNUSED)) | (b & PS_HALFCARRY) | PS_ADDSUB;
if( res==0 ) regS |= PS_ZERO;
if( w&0x100 ) regS |= PS_CARRY;
if( (((b >> 1) ^ b) & 0x80) ) regS |= PS_OVERFLOW;
return res;
}
inline void cp(byte opd1, byte opd2)
{
uint16_t r = opd1 - opd2;
uint16_t b = opd1 ^ opd2 ^ r;
regS = (r & PS_SIGN) | (opd2 & PS_UNUSED) | (b & PS_HALFCARRY) | PS_ADDSUB;
if( r==0 ) regS |= PS_ZERO;
if( r&0x100 ) regS |= PS_CARRY;
if( (((b >> 1) ^ b) & 0x80) ) regS |= PS_OVERFLOW;
}
inline void cpnc(byte opd1, byte opd2)
{
// similar to cp() but does not affect carry (used for cpi/cpir/cpdr)
byte r = opd1 - opd2;
byte b = opd1 ^ opd2 ^ r;
regS = (regS & PS_CARRY) | (r & PS_SIGN) | (b & PS_HALFCARRY) | PS_ADDSUB;
if( r==0 ) regS |= PS_ZERO;
r -= (regS & PS_HALFCARRY)/PS_HALFCARRY;
regS |= (r & PS_UNUSED08) | ((r & 0x02) ? PS_UNUSED20 : 0);
}
inline uint16_t addw(uint16_t opd1, uint16_t opd2, byte c)
{
uint16_t res;
uint32_t lw = (uint32_t) opd1 + (uint32_t) opd2 + (uint32_t) c;
uint32_t b = (opd1 ^ opd2 ^ lw) >> 8;
res = lw;
regS = ((lw>>8) & PS_UNUSED) | (b & PS_HALFCARRY);
if( res & 0x8000 ) regS |= PS_SIGN;
if( res==0 ) regS |= PS_ZERO;
if( lw&0x10000 ) regS |= PS_CARRY;
if( (((b >> 1) ^ b) & 0x80) ) regS |= PS_OVERFLOW;
return res;
}
inline uint16_t subw(uint16_t opd1, uint16_t opd2, byte c)
{
uint16_t res;
uint32_t lw = (uint32_t) opd1 - (uint32_t) opd2 - (uint32_t) c;
uint32_t b = (opd1 ^ opd2 ^ lw) >> 8;
res = lw;
regS = ((lw>>8) & PS_UNUSED) | (b & PS_HALFCARRY) | PS_ADDSUB;
if( res & 0x8000 ) regS |= PS_SIGN;
if( res==0 ) regS |= PS_ZERO;
if( lw&0x10000 ) regS |= PS_CARRY;
if( (((b >> 1) ^ b) & 0x80) ) regS |= PS_OVERFLOW;
return res;
}
inline uint16_t addw2(uint16_t opd1, uint16_t opd2)
{
// similar to addw() but only affects CARRY, HALFCARRY and ADDSUB
uint16_t res;
uint32_t lw = (uint32_t) opd1 + (uint32_t) opd2;
uint32_t b = (opd1 ^ opd2 ^ lw) >> 8;
res = lw;
regS = (regS & ~(PS_CARRY|PS_HALFCARRY|PS_ADDSUB|PS_UNUSED)) | ((lw>>8) & PS_UNUSED) | (b & PS_HALFCARRY);
if( lw&0x10000 ) regS |= PS_CARRY;
return res;
}
// -------------------------------------------- load/exchange --------------------------------------------------
static void cpu_lda() /* ld a, (NNNN) */
{
uint16_t addr = MEM_READ_WORD(regPC);
regA = MEM_READ(addr);
regPC += 2;
TIMER_ADD_CYCLES(13);
}
static void cpu_sta() /* ld (NNNN), a */
{
uint16_t addr = MEM_READ_WORD(regPC);
MEM_WRITE(addr, regA);
regPC += 2;
TIMER_ADD_CYCLES(13);
}
#define CPU_LDX(REG) /* ld a, <(bc),(de)> */ \
static void cpu_ldx ## REG() \
{ \
regA = MEM_READ(reg##REG.REG); \
TIMER_ADD_CYCLES(7); \
}
#define CPU_STX(REG) /* ld <(bc),(de)>, a */ \
static void cpu_stx ## REG() \
{ \
MEM_WRITE(reg##REG.REG, regA); \
TIMER_ADD_CYCLES(7); \
}
static void cpu_lhld() /* ld hl,(NNNN) */
{
uint16_t addr = MEM_READ_WORD(regPC);
regL = MEM_READ(addr);
regH = MEM_READ(addr+1);
regPC += 2;
TIMER_ADD_CYCLES(16);
}
static void cpu_shld() /* ld (NNNN), hl */
{
uint16_t addr = MEM_READ_WORD(regPC);
MEM_WRITE(addr, regL);
MEM_WRITE(addr+1u, regH);
regPC += 2;
TIMER_ADD_CYCLES(16);
}
static void cpu_lxiSP() /* ld sp, NNNN */
{
regSP = MEM_READ_WORD(regPC);
regPC += 2;
TIMER_ADD_CYCLES(10);
}
#define CPU_LXI(REGH,REGL) /* ld <BC,DE,HL>, NNNN */ \
static void cpu_lxi ## REGH ## REGL() \
{ \
reg ## REGL = MEM_READ(regPC); \
reg ## REGH = MEM_READ(regPC+1); \
regPC += 2; \
TIMER_ADD_CYCLES(10); \
}
#define CPU_LDRR(REGTO,REGFROM) /* ld <b,c,d,e,h,l,a>, <b,c,d,e,h,l,a> */ \
static void cpu_ld ## REGTO ## REGFROM () \
{ \
reg ## REGTO = reg ## REGFROM; \
TIMER_ADD_CYCLES(4); \
}
#define CPU_LDMR(REGFROM) /* ld (hl), <b,c,d,e,h,l,a> */ \
static void cpu_ldM ## REGFROM() \
{ \
MEM_WRITE(regHL.HL, reg ## REGFROM); \
TIMER_ADD_CYCLES(7); \
}
#define CPU_LDRM(REGTO) /* ld <b,c,d,e,h,l,a>, (hl) */ \
static void cpu_ld ## REGTO ## M() \
{ \
reg ## REGTO = MEM_READ(regHL.HL); \
TIMER_ADD_CYCLES(7); \
}
#define CPU_LDRI(REGTO) /* ld <b,c,d,e,h,l,a>, NN */ \
static void cpu_ld ## REGTO ## I() \
{ \
reg ## REGTO = MEM_READ(regPC); \
regPC++; \
TIMER_ADD_CYCLES(7); \
}
static void cpu_ldMI() /* ld (hl), NN */
{
MEM_WRITE(regHL.HL, MEM_READ(regPC));
regPC++;
TIMER_ADD_CYCLES(10);
}
static void cpu_ldSP() /* ld sp, hl */
{
regSP = regHL.HL;
TIMER_ADD_CYCLES(6);
}
static void cpu_exsp() /* ex (sp), hl */
{
byte b;
b = MEM_READ(regSP+1u); MEM_WRITE(regSP+1u, regH); regH = b;
b = MEM_READ(regSP); MEM_WRITE(regSP, regL); regL = b;
TIMER_ADD_CYCLES(18);
}
static void cpu_exde() /* ex de, hl */
{
byte b;
b = regD; regD = regH; regH = b;
b = regE; regE = regL; regL = b;
TIMER_ADD_CYCLES(4);
}
static void cpu_exaf() /* ex af, af' */
{
uint16_t w;
w = regAF.AF; regAF.AF = regAF_.AF; regAF_.AF = w;
TIMER_ADD_CYCLES(4);
}
static void cpu_exx() /* exx */
{
uint16_t w;
w = regBC.BC; regBC.BC = regBC_.BC; regBC_.BC = w;
w = regDE.DE; regDE.DE = regDE_.DE; regDE_.DE = w;
w = regHL.HL; regHL.HL = regHL_.HL; regHL_.HL = w;
TIMER_ADD_CYCLES(4);
}
CPU_LDX(BC);
CPU_LDX(DE);
CPU_STX(BC);
CPU_STX(DE);
CPU_LXI(B,C);
CPU_LXI(D,E);
CPU_LXI(H,L);
CPU_LDRR(B, B);
CPU_LDRR(B, C);
CPU_LDRR(B, D);
CPU_LDRR(B, E);
CPU_LDRR(B, H);
CPU_LDRR(B, L);
CPU_LDRR(B, A);
CPU_LDRM(B);
CPU_LDMR(B);
CPU_LDRI(B);
CPU_LDRR(C, B);
CPU_LDRR(C, C);
CPU_LDRR(C, D);
CPU_LDRR(C, E);
CPU_LDRR(C, H);
CPU_LDRR(C, L);
CPU_LDRR(C, A);
CPU_LDRM(C);
CPU_LDMR(C);
CPU_LDRI(C);
CPU_LDRR(D, B);
CPU_LDRR(D, C);
CPU_LDRR(D, D);
CPU_LDRR(D, E);
CPU_LDRR(D, H);
CPU_LDRR(D, L);
CPU_LDRR(D, A);
CPU_LDRM(D);
CPU_LDMR(D);
CPU_LDRI(D);
CPU_LDRR(E, B);
CPU_LDRR(E, C);
CPU_LDRR(E, D);
CPU_LDRR(E, E);
CPU_LDRR(E, H);
CPU_LDRR(E, L);
CPU_LDRR(E, A);
CPU_LDRM(E);
CPU_LDMR(E);
CPU_LDRI(E);
CPU_LDRR(H, B);
CPU_LDRR(H, C);
CPU_LDRR(H, D);
CPU_LDRR(H, E);
CPU_LDRR(H, H);
CPU_LDRR(H, L);
CPU_LDRR(H, A);
CPU_LDRM(H);
CPU_LDMR(H);
CPU_LDRI(H);
CPU_LDRR(L, B);
CPU_LDRR(L, C);
CPU_LDRR(L, D);
CPU_LDRR(L, E);
CPU_LDRR(L, H);
CPU_LDRR(L, L);
CPU_LDRR(L, A);
CPU_LDRM(L);
CPU_LDMR(L);
CPU_LDRI(L);
CPU_LDRR(A, B);
CPU_LDRR(A, C);
CPU_LDRR(A, D);
CPU_LDRR(A, E);
CPU_LDRR(A, H);
CPU_LDRR(A, L);
CPU_LDRR(A, A);
CPU_LDRM(A);
CPU_LDMR(A);
CPU_LDRI(A);
// ------------------------------------------ arithmetic/logic/rotate ------------------------------------------------
#define CPU_ADC(REG) /* adc a,<b,c,d,e,h,l,a> */ \
static void cpu_adc ## REG () \
{ \
regA = add(regA, reg ## REG, regS & PS_CARRY); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_ADD(REG) /* add a,<b,c,d,e,h,l,a> */ \
static void cpu_add ## REG () \
{ \
regA = add(regA, reg ## REG, 0); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_SBC(REG) /* sbc a,<b,c,d,e,h,l,a> */ \
static void cpu_sbc ## REG () \
{ \
regA = sub(regA, reg ## REG, regS & PS_CARRY); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_SUB(REG) /* sub a,<b,c,d,e,h,l,a> */ \
static void cpu_sub ## REG () \
{ \
regA = sub(regA, reg ## REG, 0); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_AND(REG) /* and <b,c,d,e,h,l,a> */ \
static void cpu_and ## REG () \
{ \
regA &= reg ## REG; \
setStatusBitsLogic(regA, PS_HALFCARRY); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_XOR(REG) /* xor <b,c,d,e,h,l,a> */ \
static void cpu_xor ## REG () \
{ \
regA ^= reg ## REG; \
setStatusBitsLogic(regA, 0); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_OR(REG) /* or <b,c,d,e,h,l,a> */ \
static void cpu_or ## REG () \
{ \
regA |= reg ## REG; \
setStatusBitsLogic(regA, 0); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_CP(REG) /* cp <b,c,d,e,h,l,a> */ \
static void cpu_cp ## REG () \
{ \
cp(regA, reg ## REG); \
TIMER_ADD_CYCLES(4); \
}
static void cpu_adcM() /* adc a,(hl) */
{
regA = add(regA, MEM_READ(regHL.HL), regS & PS_CARRY);
TIMER_ADD_CYCLES(7);
}
static void cpu_addM() /* add a,(hl) */
{
regA = add(regA, MEM_READ(regHL.HL), 0);
TIMER_ADD_CYCLES(7);
}
static void cpu_sbcM() /* sbc a,(hl) */
{
regA = sub(regA, MEM_READ(regHL.HL), regS & PS_CARRY);
TIMER_ADD_CYCLES(7);
}
static void cpu_subM() /* sub a,(hl) */
{
regA = sub(regA, MEM_READ(regHL.HL), 0);
TIMER_ADD_CYCLES(7);
}
static void cpu_andM() /* and (hl) */
{
regA &= MEM_READ(regHL.HL);
setStatusBitsLogic(regA, PS_HALFCARRY);
TIMER_ADD_CYCLES(7);
}
static void cpu_xorM() /* xor (hl) */
{
regA ^= MEM_READ(regHL.HL);
setStatusBitsLogic(regA, 0);
TIMER_ADD_CYCLES(7);
}
static void cpu_orM() /* or (hl) */
{
regA |= MEM_READ(regHL.HL);
setStatusBitsLogic(regA, 0);
TIMER_ADD_CYCLES(7);
}
static void cpu_cpM() /* cp (hl) */
{
cp(regA, MEM_READ(regHL.HL));
TIMER_ADD_CYCLES(7);
}
static void cpu_add() /* add a,NN */
{
regA = add(regA, MEM_READ(regPC), 0);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_adc() /* adc a,NN */
{
regA = add(regA, MEM_READ(regPC), regS & PS_CARRY);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_sub() /* sub a,NN */
{
regA = sub(regA, MEM_READ(regPC), 0);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_sbc() /* sbc a,NN */
{
regA = sub(regA, MEM_READ(regPC), regS & PS_CARRY);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_and() /* and NN */
{
regA &= MEM_READ(regPC);
setStatusBitsLogic(regA, PS_HALFCARRY);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_xor() /* xor NN */
{
regA ^= MEM_READ(regPC);
setStatusBitsLogic(regA, 0);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_or() /* or NN */
{
regA |= MEM_READ(regPC);
setStatusBitsLogic(regA, 0);
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_cpi() /* cp NN */
{
cp(regA, MEM_READ(regPC));
regPC++;
TIMER_ADD_CYCLES(7);
}
static void cpu_rlca() /* rlca */
{
byte b = regA & 128;
regA = (regA * 2) | (b ? 1 : 0) ;
regS = (regS & ~(PS_HALFCARRY | PS_ADDSUB | PS_CARRY | PS_UNUSED)) | (regA & PS_UNUSED);
if( b ) regS |= PS_CARRY;
TIMER_ADD_CYCLES(4);
}
static void cpu_rrca() /* rrca */
{
byte b = regA & 1;
regA = (regA / 2) | (b ? 128 : 0) ;
regS = (regS & ~(PS_HALFCARRY | PS_ADDSUB | PS_CARRY | PS_UNUSED)) | (regA & PS_UNUSED);
if( b ) regS |= PS_CARRY;
TIMER_ADD_CYCLES(4);
}
static void cpu_rla() /* rla */
{
byte b = regA & 128;
regA = (regA * 2) | ((regS & PS_CARRY) ? 1 : 0) ;
regS = (regS & ~(PS_HALFCARRY | PS_ADDSUB | PS_CARRY | PS_UNUSED)) | (regA & PS_UNUSED);
if( b ) regS |= PS_CARRY;
TIMER_ADD_CYCLES(4);
}
static void cpu_rra() /* rra */
{
byte b = regA & 1;
regA = (regA / 2) | ((regS & PS_CARRY) ? 128 : 0) ;
regS = (regS & ~(PS_HALFCARRY | PS_ADDSUB | PS_CARRY | PS_UNUSED)) | (regA & PS_UNUSED);
if( b ) regS |= PS_CARRY;
TIMER_ADD_CYCLES(4);
}
#define CPU_DAD(REG) /* add hl, <bc,de,hl> */ \
static void cpu_dad ## REG() \
{ \
regHL.HL = addw2(regHL.HL, reg ## REG.REG); \
TIMER_ADD_CYCLES(10); \
}
static void cpu_dadSP() /* add hl, sp */
{
regHL.HL = addw2(regHL.HL, regSP);
TIMER_ADD_CYCLES(10);
}
CPU_ADC(B);
CPU_ADC(C);
CPU_ADC(D);
CPU_ADC(E);
CPU_ADC(H);
CPU_ADC(L);
CPU_ADC(A);
CPU_ADD(B);
CPU_ADD(C);
CPU_ADD(D);
CPU_ADD(E);
CPU_ADD(H);
CPU_ADD(L);
CPU_ADD(A);
CPU_SBC(B);
CPU_SBC(C);
CPU_SBC(D);
CPU_SBC(E);
CPU_SBC(H);
CPU_SBC(L);
CPU_SBC(A);
CPU_SUB(B);
CPU_SUB(C);
CPU_SUB(D);
CPU_SUB(E);
CPU_SUB(H);
CPU_SUB(L);
CPU_SUB(A);
CPU_AND(B);
CPU_AND(C);
CPU_AND(D);
CPU_AND(E);
CPU_AND(H);
CPU_AND(L);
CPU_AND(A);
CPU_XOR(B);
CPU_XOR(C);
CPU_XOR(D);
CPU_XOR(E);
CPU_XOR(H);
CPU_XOR(L);
CPU_XOR(A);
CPU_OR(B);
CPU_OR(C);
CPU_OR(D);
CPU_OR(E);
CPU_OR(H);
CPU_OR(L);
CPU_OR(A);
CPU_CP(B);
CPU_CP(C);
CPU_CP(D);
CPU_CP(E);
CPU_CP(H);
CPU_CP(L);
CPU_CP(A);
CPU_DAD(BC);
CPU_DAD(DE);
CPU_DAD(HL);
// -------------------------------------------- increment/decrement ---------------------------------------------------
#define CPU_DEC(REG) /* dec <b,c,d,e,h,l,a> */ \
static void cpu_dec ## REG () \
{ \
reg ## REG = dec(reg ## REG); \
TIMER_ADD_CYCLES(4); \
}
#define CPU_INC(REG) /* inc <b,c,d,e,h,l,a> */ \
static void cpu_inc ## REG() \
{ \
reg ## REG = inc(reg ## REG); \
TIMER_ADD_CYCLES(4); \
}
static void cpu_decM() /* dec (hl) */
{
byte res = dec(MEM_READ(regHL.HL));
MEM_WRITE(regHL.HL, res);
TIMER_ADD_CYCLES(11);
}
static void cpu_incM() /* inc (hl) */
{
byte res = inc(MEM_READ(regHL.HL));
MEM_WRITE(regHL.HL, res);
TIMER_ADD_CYCLES(11);
}
#define CPU_DCX(REG) /* dec <bc,de,hl> */ \
static void cpu_dcx ## REG () \
{ \
reg##REG.REG--; \
TIMER_ADD_CYCLES(6); \
}
static void cpu_dcxSP() /* dec sp */
{
regSP--;
TIMER_ADD_CYCLES(6);
}
#define CPU_INX(REG) /* inc <bc,de,hl> */ \
static void cpu_inx ## REG () \
{ \
reg##REG.REG++; \
TIMER_ADD_CYCLES(6); \
}
static void cpu_inxSP() /* inc sp */
{
regSP++;
TIMER_ADD_CYCLES(6);
}
CPU_DEC(B);
CPU_DEC(C);
CPU_DEC(D);
CPU_DEC(E);
CPU_DEC(H);
CPU_DEC(L);
CPU_DEC(A);
CPU_INC(B);
CPU_INC(C);
CPU_INC(D);
CPU_INC(E);
CPU_INC(H);
CPU_INC(L);
CPU_INC(A);